WO2012147480A1 - 電子部品モジュールの製造方法及び電子部品モジュール - Google Patents

電子部品モジュールの製造方法及び電子部品モジュール Download PDF

Info

Publication number
WO2012147480A1
WO2012147480A1 PCT/JP2012/059305 JP2012059305W WO2012147480A1 WO 2012147480 A1 WO2012147480 A1 WO 2012147480A1 JP 2012059305 W JP2012059305 W JP 2012059305W WO 2012147480 A1 WO2012147480 A1 WO 2012147480A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic component
bumps
component module
substrate
bare
Prior art date
Application number
PCT/JP2012/059305
Other languages
English (en)
French (fr)
Inventor
紳弥 清野
祥明 佐竹
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to KR1020137027639A priority Critical patent/KR101489146B1/ko
Priority to EP12775989.2A priority patent/EP2704185A4/en
Priority to JP2013511987A priority patent/JP5626460B2/ja
Priority to CN201280020504.9A priority patent/CN103493191B/zh
Publication of WO2012147480A1 publication Critical patent/WO2012147480A1/ja
Priority to US14/062,767 priority patent/US9532495B2/en
Priority to US15/353,362 priority patent/US10177108B2/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04Mounting of components, e.g. of leadless components
    • H05K13/046Surface mounting
    • H05K13/0465Surface mounting by soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11312Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11318Manufacturing methods by local deposition of the material of the bump connector in liquid form by dispensing droplets
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/115Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/11505Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/115Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/11515Curing and solidification, e.g. of a photosensitive bump material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • H01L2224/13013Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • H01L2224/13014Shape in top view being circular or elliptic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/14104Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605Shape
    • H01L2224/16052Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605Shape
    • H01L2224/16057Shape in side view
    • H01L2224/16058Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701Structure
    • H01L2224/1703Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/17104Disposition relative to the bonding areas, e.g. bond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/17104Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H01L2224/17107Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114Guiding structures outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81194Lateral distribution of the bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • H01L2924/3841Solder bridging
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing an electronic component module in which a plurality of external terminals of an electronic component are respectively joined to a plurality of bumps provided on one surface of a substrate, and an electronic component module manufactured by the manufacturing method.
  • Patent Document 1 discloses a bump forming method for bonding a semiconductor device to a substrate via a bump.
  • FIG. 1 is a schematic cross-sectional view showing a conventional method for manufacturing an electronic component module.
  • a metal paste 4 is discharged from an ink head 3 on a surface electrode 10 of a substrate 9 and dried to form bumps 6.
  • the bare IC 1 is mounted on the substrate 9 and is pressed and heated to deform the bumps 6 to join the external terminals 2 and mount the bare IC 1 on the substrate 9. To do.
  • the deformed bump 6 goes around to the side surface of the bare IC 1 and the surface electrode 10 of the substrate 9 and the internal wiring of the bare IC 1 become conductive. There was a fear. Therefore, the electronic component module manufactured by the conventional manufacturing method described above may deteriorate the characteristics of the bare IC 1.
  • FIG. 2 is a cross-sectional view showing a configuration of an electronic component module manufactured by a conventional manufacturing method.
  • the joint 7 between the external terminal 2 of the bare IC 1 and the surface electrode 10 of the substrate 9 goes around the side of the bare IC 1, and the joint 7 and the side of the bare IC 1 Touch.
  • the internal wiring is often exposed on the side surface of the bare IC 1.
  • the joint portion 7 and the side surface of the bare IC 1 are in contact with each other, the surface electrode 10 of the substrate 9 and the internal wiring of the bare IC 1 are electrically connected, so that the characteristics of the bare IC 1 are deteriorated.
  • the present invention has been made in view of such circumstances, and a method of manufacturing an electronic component module in which joints between a plurality of external terminals of an electronic component and a surface electrode of a substrate do not contact the side surface of the electronic component.
  • An object of the present invention is to provide an electronic component module manufactured by the manufacturing method.
  • an electronic component module manufacturing method includes an electronic component module manufacturing method in which a plurality of external terminals of an electronic component are respectively bonded to a plurality of bumps provided on one surface of a substrate.
  • the plurality of bumps are configured with a thick portion that is a thick portion and a thin portion that is a thin portion, and the thick portion corresponds when the electronic component is viewed in plan view.
  • the thin-walled portion is positioned on the center side of the electronic component of each external terminal, and the thin-walled portion is positioned on the opposite side of the center side of the electronic component of each corresponding external terminal.
  • the plurality of bumps are composed of a thick portion that is a thick portion and a thin portion that is a thin portion.
  • the thin-walled portion of the corresponding external terminal of the electronic component is positioned so that the thick-walled portion is positioned on the center side of the corresponding external terminal. It is formed on one surface of the substrate so as to be located on the side opposite to the center side.
  • a plurality of joints obtained by deforming a plurality of formed bumps and joining a plurality of external terminals have a height opposite to the center side of the electronic component than the height of the center side of the electronic component when the electronic component is viewed in plan view. Since the joint is not in contact with the side surface of the electronic component and the internal wiring is exposed on the side surface of the electronic component due to the dicer cut, the characteristics of the electronic component are There is no deterioration.
  • the height of the joint portion on the side opposite to the center side of the electronic component is lower than the height on the center side of the electronic component when the electronic component is viewed in plan view. Even if the junction does not contact the side surface of the electronic component and the internal wiring is exposed on the side surface of the electronic component due to the dicer cut, the characteristics of the electronic component are deteriorated. There is nothing to do.
  • the plurality of bumps are formed by an ink jet method.
  • the plurality of bumps are formed by the ink jet method, it is possible to easily form the thin portion and the thick portion having different thicknesses by adjusting the number of discharges of the metal paste. Moreover, the thin part to the thick part can be formed at a stretch, and the manufacturing cost can be reduced.
  • an electronic component module includes a substrate, a plurality of bumps provided on one surface of the substrate, an electronic component having a plurality of external terminals, and a plurality of the components.
  • the plurality of joints are the electrons in a plan view of the electronic component. It is characterized in that the height on the opposite side to the center side of the electronic component is lower than the height on the center side of the component.
  • the plurality of joints are formed so that the height on the opposite side of the center side of the electronic component is lower than the height on the center side of the electronic component when the electronic component is viewed in plan view. Even when the joint does not contact the side surface of the electronic component and the internal wiring is exposed on the side surface of the electronic component due to dicer cutting, the characteristics of the electronic component do not deteriorate.
  • the plurality of bumps are arranged in pairs so as to face each other across the center when the electronic component is viewed in plan.
  • the plurality of bumps are arranged in pairs so as to face each other across the center when the electronic component is viewed in plan view. Since the deformation state of the plurality of bumps can be made uniform, it is possible to prevent the bonding strength from being biased.
  • the plurality of bumps are composed of a thick portion that is a thick portion and a thin portion that is a thin portion.
  • the thin-walled portion of the corresponding external terminal of the electronic component is positioned so that the thick-walled portion is positioned on the center side of the corresponding external terminal. It is formed on one surface of the substrate so as to be located on the side opposite to the center side.
  • a plurality of joints obtained by deforming a plurality of formed bumps and joining a plurality of external terminals have a height opposite to the center side of the electronic component than the height of the center side of the electronic component when the electronic component is viewed in plan view. Since the joint is not in contact with the side surface of the electronic component and the internal wiring is exposed on the side surface of the electronic component due to the dicer cut, the characteristics of the electronic component are There is no deterioration.
  • FIG. 3 is a cross-sectional view showing the configuration of the electronic component module according to the embodiment of the present invention before mounting the bare IC.
  • the surface electrode 10 is provided on one surface of the substrate 9, and the bumps 6 are formed on the surface electrode 10 in a step shape.
  • the bump 6 includes a thin portion 61 that is a thin portion and a thick portion 62 that is a thick portion.
  • the thin-walled portion 61 is positioned at the center of the corresponding external terminal 2 when the electronic component is viewed in plan view. 2 is formed on one surface of the substrate 9 so as to be located on the side opposite to the center side when the electronic component is viewed in plan.
  • a bare IC which is an electronic component with external terminals, is mounted will be described as an example.
  • FIG. 4 is a cross-sectional view showing the configuration of the electronic component module according to the embodiment of the present invention.
  • the bump 6 is deformed and the portion where the external terminal 2 is joined is used as the joint 7.
  • the joint portion 7 is formed such that the height on the opposite side to the center side when the bear IC 1 is viewed in plan is lower than the height of the center side when the bear IC 1 is viewed in plan. Therefore, the deformed bump 6 does not reach the side surface of the bare IC 1. As a result, chipping occurs during the dicer cut of the bare IC 1, and even if the internal wiring is exposed on the side surface of the bare IC 1, the surface electrode 10 of the substrate 9 and the internal wiring of the bare IC 1 may be electrically connected. In addition, the characteristics of the bare IC 1 are not deteriorated.
  • FIG. 5 is an enlarged cross-sectional view showing a part of the substrate 9.
  • the substrate 9 is formed of a flexible resin, and a surface electrode 10 is provided on one surface of the substrate 9 as shown in FIG.
  • the surface electrode 10 is configured by applying an Au plating 101 on a nickel layer 102 and a copper layer 103 which are bases.
  • Bumps 6 are formed in a desired shape on the Au plating 101 by discharging a metal paste from the ink head.
  • a metal paste For example, an Ag paste is used as the metal paste.
  • the method of forming the bumps 6 is not limited to the ink jet method.
  • the bumps 6 may be formed by a screen printing method.
  • the screen printing method it is necessary to form the thin portion 61 and then dry it once to replace the screen plate, and then form the thick portion 62 in a part of the thin portion 61.
  • the bumps 6 are formed by the ink jet method, the thin portion 61 to the thick portion 62 can be formed all at once, and the manufacturing cost can be reduced.
  • the external terminal 2 of the bare IC 1 has an inverted truncated cone shape, and is formed by an Au wire bump on an Al pad that is an external electrode of the bare IC 1.
  • the outer diameter of the Au wire bump is 85 ⁇ m and the height is 25 ⁇ m.
  • an Au plating bump, a Cu wire bump, or a Cu plating bump may be used.
  • the external terminal 2 may be formed in a disk shape by a plating bump.
  • FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the electronic component module according to the embodiment of the present invention.
  • the metal paste 4 is discharged from the ink head 3 onto the surface electrode 10 of the substrate 9 to form a thin portion 61 as shown in FIG. 6B.
  • the metal paste 4 is discharged while moving the table on which the ink head 3 or the substrate 9 is placed.
  • An Ag paste is used as the metal paste 4, and one dot of the Ag paste discharged from the ink head 3 is 1 pl (1 ⁇ 10 ⁇ 15 m 3 ).
  • a thin part 61 having a thickness of 20 ⁇ m is formed by discharging the metal paste 4 twice while moving the table on which the ink head 3 is placed in the horizontal direction (left and right direction in FIG. 6). is doing.
  • a thick portion 62 is formed. Also for the thick portion 62, the metal paste 4 is discharged eight times while moving the table on which the ink head 3 is placed in the horizontal direction. Thereby, a bump 6 having a thickness of 100 ⁇ m at the center when the bare IC 1 is viewed in plan is formed. Then, the formed bump 6 is dried. Since the discharged metal paste 4 is a fine droplet, it can be naturally dried without using a special drying apparatus.
  • the ratio of the thickness of the thick part 62 to the thickness of the thin part 61 is about 5: 1.
  • the ratio is not particularly limited to this, and the bare IC 1 is mounted when the bare IC 1 is mounted. If the bump 6 deformed to the side surface does not go around, for example, 2: 1 may be used.
  • the width in the horizontal direction (left-right direction in FIG. 6) is 50 ⁇ m for the thick portion 62 and 100 ⁇ m for the thin portion 61 in the present embodiment, but is not particularly limited thereto.
  • the width of 62 may be 10 ⁇ m.
  • the bare IC 1 is mounted on the substrate 9 and pressed and heated to deform the bumps 6 to join the external terminals 2, and the bare IC 1 is mounted on the substrate 9. To do.
  • the center of the external terminal 2 of the bare IC 1 is aligned so that it does not overlap the thick portion 62. This makes it difficult for the deformed bump 6 to go around the side surface of the bare IC 1.
  • FIG. 7 is a plan perspective view showing the arrangement of the bumps 6 in the electronic component module according to the embodiment of the present invention.
  • the external terminals 2 of the bare IC 1 are indicated by white circles, and the bumps 6 are hatched.
  • the plurality of bumps 6 are arranged in pairs so as to face each other across the center 71 when the bare IC 1 is viewed in plan.
  • the thick portions 62 of the bumps 6 are formed in pairs so as to face each other across the center 71 when the bare IC 1 is viewed in plan. Accordingly, when the bare IC 1 is mounted, the pressing force can be balanced and the deformation state of the plurality of bumps 6 can be made uniform, so that it is possible to prevent the bonding strength from being biased in advance. It becomes possible.
  • the bump 6 is not limited to a rectangular shape in plan view as shown in FIG.
  • FIG. 8 is a plan perspective view showing the arrangement of the bumps 6 when the shapes of the bumps 6 in the electronic component module according to the embodiment of the present invention are different.
  • a bump having a substantially elliptical shape with a thin portion 61 having a substantially elliptical shape in plan view and a thick portion 62 having a substantially elliptical shape in plan view. 6 may be configured.
  • the bumps 6 are arranged in pairs so as to face each other across the center 71 when the bare IC 1 is viewed in plan.
  • the thick portions 62 of the bumps 6 are formed in pairs so as to face each other across the center 71 when the bare IC 1 is viewed in plan.
  • FIG. 9 is a perspective plan view showing the arrangement of the bumps 6 when the bare IC 1 has two external terminals 2 in the electronic component module according to the embodiment of the present invention.
  • the external terminals 2 are often rectangular in plan view from the viewpoint of stably mounting the bare IC 1.
  • the step-like bump 6 is formed so that the thick portion 62 is located on the center side and the thin portion 61 is located on the opposite side when the bare IC 1 is viewed in plan from the center line in the longitudinal direction of the external terminal 2. Therefore, the same effect can be expected.
  • the plurality of joints 7 obtained by deforming the formed plurality of bumps 6 and joining the plurality of external terminals 2 are higher than the height on the center side when the bare IC 1 is viewed in plan view. Since the height on the opposite side to the center side when the bare IC 1 is viewed in plan view is formed to be lower, the joint portion 7 does not come into contact with the side surface of the bare IC 1, and the side surface of the bare IC 1 is obtained by dicer cutting. Even if the internal wiring is exposed, the characteristics of the bare IC 1 are not deteriorated.
  • the bump 6 is formed in a two-step shape including the thick portion 62 and the thin portion 61, but is not particularly limited to two steps.
  • FIG. 10 is a cross-sectional view showing the configuration before mounting the bare IC 1 when the shape of the bump 6 is different in the electronic component module according to the embodiment of the present invention.
  • FIG. 10A shows an example in which the bump 6 is formed in a three-step staircase having a thick portion, an intermediate portion, and a thin portion.
  • the bare IC 1 is formed so as to be thicker as it is closer to the center when viewed in plan.
  • the thickness becomes thicker as it is closer to the center when the bare IC 1 is viewed in plan view.
  • An inclined bump 6 may be formed.
  • the present invention is not limited to the above embodiment, and various changes and improvements can be made within the scope of the gist of the present invention.
  • an electronic component module in which an electronic component such as a bare IC is mounted on a substrate but also an electronic component module in which a medium-sized electronic component incorporating a small-sized electronic component is mounted on a substrate.
  • an electronic component module in which a small-sized electronic component is resin-sealed together with a substrate and then an electromagnetic wave shield portion is formed on the top surface or side surface can be manufactured by applying the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

 電子部品の複数の外部端子と基板の表面電極との接合部が、電子部品の側面に接触することがない、電子部品モジュールの製造方法及び該製造方法で製造された電子部品モジュールを提供する。 複数のバンプ6を厚さの厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成し、電子部品を平面視した場合に、厚肉部は、対応するそれぞれの外部端子2の、電子部品の中央側に位置するように、薄肉部は、対応するそれぞれの外部端子2の、電子部品の中央側と反対側に位置するように、基板の一方の面にそれぞれ形成する。形成した複数のバンプ6を変形させて複数の外部端子2を接合した複数の接合部7を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成する。

Description

電子部品モジュールの製造方法及び電子部品モジュール
 本発明は、基板の一方の面に設けてある複数のバンプに、電子部品の複数の外部端子をそれぞれ接合する電子部品モジュールの製造方法及び該製造方法で製造された電子部品モジュールに関する。
 特許文献1には、基板にバンプを介して半導体装置を接合するバンプの形成方法が開示してある。図1は、従来の電子部品モジュールの製造方法を示す模式断面図である。図1(a)に示すように、特許文献1では、基板9の表面電極10上に、インクヘッド3から金属ペースト4を吐出して乾燥させて、バンプ6を形成する。
 次に、図1(b)に示すように、ベアIC(外部端子付き電子部品)1の外部端子2が基板9のバンプ6にそれぞれ対向するように位置合わせする。そして、図1(c)に示すように、ベアIC1を基板9上に搭載して加圧・加熱することにより、バンプ6を変形させて外部端子2を接合し、ベアIC1を基板9に実装する。
特開2004-228375号公報
 上述した従来の製造方法では、例えばバンプ6の厚さが厚く形成された場合、変形したバンプ6がベアIC1の側面にまで回り込み、基板9の表面電極10とベアIC1の内部配線とが導通するおそれがあった。したがって、上述した従来の製造方法で製造した電子部品モジュールは、ベアIC1の特性が劣化するおそれがあった。
 図2は、従来の製造方法で製造した電子部品モジュールの構成を示す断面図である。バンプ6の厚さが厚く形成された場合には、ベアIC1の外部端子2と基板9の表面電極10との接合部7がベアIC1の側面にまで回り込み、接合部7とベアIC1の側面とが接触する。ベアIC1のダイサーカット時にチッピングが生じた場合、ベアIC1の側面では内部配線がむき出しになることが多い。この場合、接合部7とベアIC1の側面とが接触したときには、基板9の表面電極10とベアIC1の内部配線とが導通することにより、ベアIC1の特性が劣化する。
 本発明は斯かる事情に鑑みてなされたものであり、電子部品の複数の外部端子と基板の表面電極との接合部が、電子部品の側面に接触することがない、電子部品モジュールの製造方法及び該製造方法で製造された電子部品モジュールを提供することを目的とする。
 上記目的を達成するために本発明に係る電子部品モジュールの製造方法は、基板の一方の面に設けてある複数のバンプに、電子部品の複数の外部端子をそれぞれ接合する電子部品モジュールの製造方法において、複数の前記バンプを厚さが厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成し、前記電子部品を平面視した場合に、前記厚肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側に位置するように、前記薄肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側と反対側に位置するように、前記基板の一方の面にそれぞれ形成する工程と、形成した複数の前記バンプを変形させて複数の前記外部端子を接合した複数の接合部を、前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成する工程とを含むことを特徴とする。
 上記構成では、複数のバンプを厚さが厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成してある。そして、電子部品を平面視した場合に、厚肉部は、対応するそれぞれの外部端子の、電子部品の中央側に位置するように、薄肉部は、対応するそれぞれの外部端子の、電子部品の中央側と反対側に位置するように、基板の一方の面に形成する。形成した複数のバンプを変形させて複数の外部端子を接合した複数の接合部を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成するので、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
 また、本発明に係る電子部品モジュールの製造方法は、複数の前記バンプを階段状に形成することが好ましい。
 上記構成では、複数のバンプを階段状に形成するので、接合部を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成することができ、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
 また、本発明に係る電子部品モジュールの製造方法は、複数の前記バンプを、インクジェット法により形成することが好ましい。
 上記構成では、複数のバンプを、インクジェット法により形成するので、金属ペーストの吐出回数を調整することにより厚さの異なる薄肉部と厚肉部とを容易に形成することができる。また、薄肉部から厚肉部までを一気に形成することができ、製造コストを低減することが可能となる。
 次に、上記目的を達成するために本発明に係る電子部品モジュールは、基板と、該基板の一方の面に設けてある複数のバンプと、複数の外部端子を有する電子部品と、複数の前記バンプを変形させて複数の前記外部端子を接合した複数の接合部の周囲を封止する樹脂とを備える電子部品モジュールにおいて、複数の前記接合部は、前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成してあることを特徴とする。
 上記構成では、複数の接合部は、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成してあることにより、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
 また、本発明に係る電子部品モジュールは、複数の前記バンプは、前記電子部品を平面視した場合の中心を挟んで対向する位置に、それぞれ一対となるように配置してあることが好ましい。
 上記構成では、複数のバンプは、電子部品を平面視した場合の中心を挟んで対向する位置に、それぞれ一対となるように配置してあるので、電子部品を実装した場合に、押圧力のバランスをとることができ、複数のバンプの変形具合を均等にすることができるので、接合強度に偏りが生じることを未然に防止することが可能となる。
 上記構成によれば、複数のバンプを厚さの厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成してある。そして、電子部品を平面視した場合に、厚肉部は、対応するそれぞれの外部端子の、電子部品の中央側に位置するように、薄肉部は、対応するそれぞれの外部端子の、電子部品の中央側と反対側に位置するように、基板の一方の面に形成する。形成した複数のバンプを変形させて複数の外部端子を接合した複数の接合部を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成するので、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
従来の電子部品モジュールの製造方法を示す模式断面図である。 従来の製造方法で製造した電子部品モジュールの構成を示す断面図である。 本発明の実施の形態に係る電子部品モジュールの、ベアIC実装前の構成を示す断面図である。 本発明の実施の形態に係る電子部品モジュールの構成を示す断面図である。 基板の一部を示す拡大断面図である。 本発明の実施の形態に係る電子部品モジュールの製造方法を示す模式断面図である。 本発明の実施の形態に係る電子部品モジュールにおけるバンプの配置を示す平面透視図である。 本発明の実施の形態に係る電子部品モジュールにおけるバンプの形状が異なる場合の、バンプの配置を示す平面透視図である。 本発明の実施の形態に係る電子部品モジュールにおけるベアICの外部端子が2個である場合の、バンプの配置を示す平面透視図である。 本発明の実施の形態に係る電子部品モジュールの、バンプの形状が異なる場合の、ベアIC実装前の構成を示す断面図である。
 以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。
 図3は、本発明の実施の形態に係る電子部品モジュールの、ベアIC実装前の構成を示す断面図である。図3に示すように、基板9の一方の面に表面電極10を設けてあり、バンプ6は、表面電極10上に階段状に形成されている。
 すなわち、バンプ6は、厚さが薄い部分である薄肉部61と、厚さが厚い部分である厚肉部62とで構成されている。厚肉部62は、電子部品を実装する場合に、対応するそれぞれの外部端子2の、電子部品を平面視した場合の中央側に位置するように、薄肉部61は、対応するそれぞれの外部端子2の、電子部品を平面視した場合の中央側と反対側に位置するように、基板9の一方の面にそれぞれ形成してある。以下、外部端子付きの電子部品であるベアICを実装する場合を例に説明する。
 図4は、本発明の実施の形態に係る電子部品モジュールの構成を示す断面図である。ベアIC1の外部端子2が基板9のバンプ6にそれぞれ対向するように位置合わせした後、ベアIC1を基板9上に搭載して加圧・加熱することにより、図4に示すようにバンプ6を変形させて外部端子2を接合し、ベアIC1を基板9に実装する。
 本実施の形態では、バンプ6を変形させて、外部端子2を接合した部分を接合部7としている。接合部7は、ベアIC1を平面視した場合の中央側の高さよりベアIC1を平面視した場合の中央側と反対側の高さの方が低くなるよう形成してある。したがって、変形したバンプ6がベアIC1の側面にまで回り込むことがない。これにより、ベアIC1のダイサーカット時にチッピングが生じ、ベアIC1の側面で内部配線がむき出しになっている場合であっても、基板9の表面電極10とベアIC1の内部配線とが導通することがなく、ベアIC1の特性が劣化することがない。
 以下、本実施の形態に係る電子部品モジュールの製造方法について具体的に説明する。図5は、基板9の一部を示す拡大断面図である。基板9はフレキシブルな樹脂で形成されており、図5に示すように、基板9の一方の面に表面電極10が設けられている。表面電極10は、下地であるニッケル層102、銅層103の上に、Auメッキ101を施して構成されている。
 Auメッキ101の上に、インクヘッドから金属ペーストを吐出することによりバンプ6を所望の形状に形成する。金属ペーストとしては、例えばAgペーストを用いる。吐出回数を調整することにより厚さの異なる薄肉部61と厚肉部62とを容易に形成することができる。
 もちろん、バンプ6の形成方法は、インクジェット法に限定されるものではない。例えば、スクリーン印刷法でバンプ6を形成しても良い。スクリーン印刷法でバンプ6を形成する場合、薄肉部61を形成した後、一旦乾燥させ、スクリーン版を取り換えてから薄肉部61の一部に厚肉部62を形成する必要がある。しかし、インクジェット法でバンプ6を形成する場合には、薄肉部61から厚肉部62までを一気に形成することができ、製造コストを低減することが可能となる。
 また、ベアIC1の外部端子2は、逆円錐台形状であり、ベアIC1の外部電極であるAlパッド上にAuワイヤバンプにより形成されている。本実施の形態では、Auワイヤバンプの外径は85μm、高さは25μmである。なお、Auワイヤバンプの代わりに、Auめっきバンプ、Cuワイヤバンプ、Cuめっきバンプを用いても良い。また、外部端子2は、めっきバンプにより円盤形状に形成しても良い。
 図6は、本発明の実施の形態に係る電子部品モジュールの製造方法を示す模式断面図である。図6(a)に示すように、まず基板9の表面電極10上に、インクヘッド3から金属ペースト4を吐出し、図6(b)に示すように薄肉部61を形成する。具体的にはインクヘッド3又は基板9を載置してあるテーブルを移動させながら、金属ペースト4を吐出する。金属ペースト4としてAgペーストを用い、インクヘッド3から吐出されるAgペーストの1ドットは1pl(1×10-15 )である。本実施の形態では、インクヘッド3を載置してあるテーブルを水平方向(図6の左右方向)へ移動させながら金属ペースト4を2回吐出することにより、厚さ20μmの薄肉部61を形成している。
 次に、図6(c)に示すように、厚肉部62を形成する。厚肉部62についても、インクヘッド3を載置してあるテーブルを水平方向へ移動させながら金属ペースト4を8回吐出する。これにより、ベアIC1を平面視した場合の中央側における厚さが100μmのバンプ6を形成している。そして、形成したバンプ6を乾燥させる。吐出される金属ペースト4が微小滴であるため、特段の乾燥装置を用いずに自然乾燥させることもできる。
 本実施の形態では、厚肉部62の厚さと薄肉部61の厚さとの比率が約5:1となっているが、特にこれに限定されるものではなく、ベアIC1の実装時にベアIC1の側面に変形したバンプ6が回り込まなければ、例えば2:1であっても良い。また、水平方向(図6の左右方向)の幅は、本実施の形態では厚肉部62が50μm、薄肉部61が100μmとしているが、特にこれに限定されるものではなく、例えば厚肉部62の幅が10μmであっても良い。
 形成したバンプ6を乾燥させた後、ベアIC(外部端子付き電子部品)1の外部端子2が基板9のバンプ6にそれぞれ対向するように位置合わせする。そして、図6(d)に示すように、ベアIC1を基板9上に搭載して加圧・加熱することにより、バンプ6を変形させて外部端子2を接合し、ベアIC1を基板9に実装する。なお、ベアIC1の外部端子2の中心が、厚肉部62と重ならないよう位置合わせする。これにより、変形したバンプ6がベアIC1の側面に回り込みにくくなる。
 図7は、本発明の実施の形態に係る電子部品モジュールにおけるバンプ6の配置を示す平面透視図である。ベアIC1の外部端子2を白丸印で示しており、バンプ6にはハッチングが施してある。複数のバンプ6は、ベアIC1を平面視した場合の中心71を挟んで対向する位置に、それぞれ一対となるように配置してある。
 また、バンプ6の厚肉部62は、ベアIC1を平面視した場合の中心71を挟んで対向する位置に、それぞれ一対となるように形成されている。したがって、ベアIC1を実装した場合に、押圧力のバランスをとることができ、複数のバンプ6の変形具合を均等にすることができるので、接合強度に偏りが生じることを未然に防止することが可能となる。
 なお、バンプ6は、図7に示すように、平面視した形状が矩形であることに限定されるものではない。図8は、本発明の実施の形態に係る電子部品モジュールにおけるバンプ6の形状が異なる場合の、バンプ6の配置を示す平面透視図である。図8に示すように、平面視した形状が略楕円形である薄肉部61と、平面視した形状が略楕円形である厚肉部62とで、平面視した形状が略楕円形であるバンプ6を構成しても良い。この場合もバンプ6は、ベアIC1を平面視した場合の中心71を挟んで対向する位置に、それぞれ一対となるように配置してある。また、バンプ6の厚肉部62は、ベアIC1を平面視した場合の中心71を挟んで対向する位置に、それぞれ一対となるように形成されている。
 また、外部端子2の数も特に制約があるものではなく、最低限2個あれば足りる。図9は、本発明の実施の形態に係る電子部品モジュールにおけるベアIC1の外部端子2が2個である場合の、バンプ6の配置を示す平面透視図である。
 図9に示すように、外部端子2が2個である場合には、ベアIC1を安定して実装するという観点から外部端子2は、平面視した形状が矩形であることが多い。そして、外部端子2の長手方向の中心線よりもベアIC1を平面視した場合の中央側に厚肉部62が、反対側に薄肉部61が位置するように、階段状のバンプ6を形成することにより、同様の効果が期待できる。
 図6に戻って、最後に図6(e)に示すように、接合部7の周囲を絶縁樹脂8で封止して、電子部品モジュールとして完成する。
 以上のように本実施の形態によれば、形成した複数のバンプ6を変形させて複数の外部端子2を接合した複数の接合部7を、ベアIC1を平面視した場合の中央側の高さよりベアIC1を平面視した場合の中央側と反対側の高さの方が低くなるよう形成してあるので、接合部7がベアIC1の側面に接触することがなく、ダイサーカットによりベアIC1の側面に内部配線がむき出しになっている場合であっても、ベアIC1の特性が劣化することがない。
 なお、上述した実施の形態では、バンプ6が厚肉部62と薄肉部61との2段の階段状に形成されているが、特に2段に限定されるものではない。図10は、本発明の実施の形態に係る電子部品モジュールの、バンプ6の形状が異なる場合の、ベアIC1実装前の構成を示す断面図である。
 図10(a)では、バンプ6を厚肉部、中間部、薄肉部の3段の階段状に形成した場合の例を示している。もちろん、ベアIC1を平面視した場合の中央側に近いほど厚さが厚くなるように形成してあることは言うまでもない。また、インクヘッド3から吐出する金属ペースト4の量を精緻に制御できるのであれば、図10(b)に示すように、ベアIC1を平面視した場合の中央側に近いほど厚さが厚くなるよう傾斜したバンプ6を形成しても良い。
 また、本発明は上記実施の形態に限定されるものではなく、本発明の趣旨の範囲内であれば多種の変更、改良等が可能である。例えばベアICのような電子部品を基板に実装した電子部品モジュールだけでなく、小型サイズの電子部品を内蔵した中型サイズの電子部品を基板に実装した電子部品モジュールであっても良い。一例としては、小型サイズの電子部品を基板と共に樹脂封止した後、天面や側面に電磁波シールド部を形成した電子部品モジュールも、本発明を適用して製造することができる。
 1 ベアIC(外部端子付き電子部品)
 2 外部端子
 4 金属ペースト
 6 バンプ
 7 接合部
 8 絶縁樹脂
 9 基板
 10 表面電極
 61 薄肉部
 62 厚肉部

Claims (5)

  1.  基板の一方の面に設けてある複数のバンプに、電子部品の複数の外部端子をそれぞれ接合する電子部品モジュールの製造方法において、
     複数の前記バンプを厚さが厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成し、前記電子部品を平面視した場合に、前記厚肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側に位置するように、前記薄肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側と反対側に位置するように、前記基板の一方の面にそれぞれ形成する工程と、
     形成した複数の前記バンプを変形させて複数の前記外部端子を接合した複数の接合部を、前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成する工程と
     を含むことを特徴とする電子部品モジュールの製造方法。
  2.  複数の前記バンプを階段状に形成することを特徴とする請求項1に記載の電子部品モジュールの製造方法。
  3.  複数の前記バンプを、インクジェット法により形成することを特徴とする請求項1又は2に記載の電子部品モジュールの製造方法。
  4.  基板と、
     該基板の一方の面に設けてある複数のバンプと、
     複数の外部端子を有する電子部品と、
     複数の前記バンプを変形させて複数の前記外部端子を接合した複数の接合部の周囲を封止する樹脂と
     を備える電子部品モジュールにおいて、
     複数の前記接合部は、前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成してあることを特徴とする電子部品モジュール。
  5.  複数の前記バンプは、前記電子部品を平面視した場合の中心を挟んで対向する位置に、それぞれ一対となるように配置してあることを特徴とする請求項4に記載の電子部品モジュール。
PCT/JP2012/059305 2011-04-27 2012-04-05 電子部品モジュールの製造方法及び電子部品モジュール WO2012147480A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020137027639A KR101489146B1 (ko) 2011-04-27 2012-04-05 전자부품 모듈의 제조방법 및 전자부품 모듈
EP12775989.2A EP2704185A4 (en) 2011-04-27 2012-04-05 METHOD FOR PRODUCING AN ELECTRONIC COMPONENT MODULE AND ELECTRONIC COMPONENT MODULE
JP2013511987A JP5626460B2 (ja) 2011-04-27 2012-04-05 電子部品モジュールの製造方法及び電子部品モジュール
CN201280020504.9A CN103493191B (zh) 2011-04-27 2012-04-05 电子元器件模块的制造方法及电子元器件模块
US14/062,767 US9532495B2 (en) 2011-04-27 2013-10-24 Method of manufacturing electronic component module and electronic component module
US15/353,362 US10177108B2 (en) 2011-04-27 2016-11-16 Method of manufacturing electronic component module and electronic component module

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-099951 2011-04-27
JP2011099951 2011-04-27

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/062,767 Continuation US9532495B2 (en) 2011-04-27 2013-10-24 Method of manufacturing electronic component module and electronic component module

Publications (1)

Publication Number Publication Date
WO2012147480A1 true WO2012147480A1 (ja) 2012-11-01

Family

ID=47072004

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/059305 WO2012147480A1 (ja) 2011-04-27 2012-04-05 電子部品モジュールの製造方法及び電子部品モジュール

Country Status (6)

Country Link
US (2) US9532495B2 (ja)
EP (1) EP2704185A4 (ja)
JP (1) JP5626460B2 (ja)
KR (1) KR101489146B1 (ja)
CN (1) CN103493191B (ja)
WO (1) WO2012147480A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10600755B2 (en) * 2017-08-10 2020-03-24 Amkor Technology, Inc. Method of manufacturing an electronic device and electronic device manufactured thereby

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228375A (ja) 2003-01-23 2004-08-12 Seiko Epson Corp バンプの形成方法、デバイス、及び電子機器
JP2008060483A (ja) * 2006-09-01 2008-03-13 Sharp Corp 半導体装置の実装構造体およびその製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3824865A1 (de) * 1988-07-21 1990-01-25 Productech Gmbh Herstellen von loetflaechen
US5291375A (en) * 1991-09-30 1994-03-01 Kabushiki Kaisha Toshiba Printed circuit board and electric device configured to facilitate bonding
JPH0677632A (ja) * 1992-02-24 1994-03-18 Matsushita Electric Ind Co Ltd 回路基板
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
US5663529A (en) * 1995-09-14 1997-09-02 Ford Motor Company Anti-skew mounting pads and processing method for electronic surface mount components
JP3783754B2 (ja) * 1998-02-27 2006-06-07 富士ゼロックス株式会社 絶縁性基板および半導体装置および半導体実装装置
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
JP2001284783A (ja) * 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd 表面実装用基板及び表面実装構造
JP4175197B2 (ja) * 2003-06-27 2008-11-05 株式会社デンソー フリップチップ実装構造
US7860495B2 (en) * 2004-08-09 2010-12-28 Siemens Industry Inc. Wireless building control architecture
EP1720389B1 (en) 2005-04-25 2019-07-03 Brother Kogyo Kabushiki Kaisha Method for forming pattern and a wired board
JP4817892B2 (ja) * 2005-06-28 2011-11-16 富士通セミコンダクター株式会社 半導体装置
JP2008060438A (ja) * 2006-09-01 2008-03-13 Matsushita Electric Ind Co Ltd 電子部品実装装置および電子部品実装方法
JP4962217B2 (ja) * 2007-08-28 2012-06-27 富士通株式会社 プリント配線基板及び電子装置製造方法
US7851928B2 (en) * 2008-06-10 2010-12-14 Texas Instruments Incorporated Semiconductor device having substrate with differentially plated copper and selective solder
US9095066B2 (en) * 2008-06-18 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Printed board
US8018027B2 (en) * 2009-10-30 2011-09-13 Murata Manufacturing Co., Ltd. Flip-bonded dual-substrate inductor, flip-bonded dual-substrate inductor, and integrated passive device including a flip-bonded dual-substrate inductor
JP5991915B2 (ja) * 2012-12-27 2016-09-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6476871B2 (ja) * 2014-05-22 2019-03-06 株式会社村田製作所 回路基板、蓄電装置、電池パックおよび電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228375A (ja) 2003-01-23 2004-08-12 Seiko Epson Corp バンプの形成方法、デバイス、及び電子機器
JP2008060483A (ja) * 2006-09-01 2008-03-13 Sharp Corp 半導体装置の実装構造体およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2704185A4 *

Also Published As

Publication number Publication date
KR20130136545A (ko) 2013-12-12
JP5626460B2 (ja) 2014-11-19
US9532495B2 (en) 2016-12-27
US20140049922A1 (en) 2014-02-20
CN103493191B (zh) 2017-09-26
KR101489146B1 (ko) 2015-02-03
CN103493191A (zh) 2014-01-01
EP2704185A4 (en) 2014-10-29
US10177108B2 (en) 2019-01-08
US20170084566A1 (en) 2017-03-23
EP2704185A1 (en) 2014-03-05
JPWO2012147480A1 (ja) 2014-07-28

Similar Documents

Publication Publication Date Title
KR100757345B1 (ko) 플립 칩 패키지 및 그의 제조 방법
US9196581B2 (en) Flow underfill for microelectronic packages
WO2014054451A1 (ja) 半導体装置及びその製造方法
JP2008288489A (ja) チップ内蔵基板の製造方法
JP2008042064A (ja) セラミック配線基板とそれを用いた光学デバイス装置、パッケージおよびセラミック配線基板の製造方法
US7994638B2 (en) Semiconductor chip and semiconductor device
JP2006261565A (ja) 電子機能部品実装体及びその製造方法
JP5626460B2 (ja) 電子部品モジュールの製造方法及び電子部品モジュール
KR100874923B1 (ko) 멀티 스택 패키지, 이의 제조 방법 및 이를 제조하기 위한반도체 패키지 금형
JP6268791B2 (ja) 樹脂多層基板およびその製造方法
JP2009298118A (ja) 記録ヘッド及び記録ヘッドの製造方法
JP2012015446A (ja) 半導体装置の製造方法
JP3746719B2 (ja) フリップチップ実装方法
JP3777131B2 (ja) 電子部品実装方法
JP2017216312A (ja) 電子部品実装方法
JP6028908B2 (ja) 半導体装置
JP2001230370A (ja) 半導体装置の製造方法
KR20070062645A (ko) 패키지 온 패키지 기판 및 그 제조방법
JP2012174900A (ja) 半導体装置の製造方法
JP2000232181A (ja) Bga構造の半導体装置及びlga構造の半導体装置並びにその製造方法
JP2006135357A (ja) 多連配線基板
JP2003045911A (ja) 半導体素子の実装構造および実装用配線基板
JP2002313840A (ja) 半導体素子実装基板及びその製造方法
JPH09186453A (ja) 配線基板の製造方法とその配線基板構造
JP2005327947A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12775989

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2013511987

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2012775989

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20137027639

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE