JP5626460B2 - 電子部品モジュールの製造方法及び電子部品モジュール - Google Patents

電子部品モジュールの製造方法及び電子部品モジュール Download PDF

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JP5626460B2
JP5626460B2 JP2013511987A JP2013511987A JP5626460B2 JP 5626460 B2 JP5626460 B2 JP 5626460B2 JP 2013511987 A JP2013511987 A JP 2013511987A JP 2013511987 A JP2013511987 A JP 2013511987A JP 5626460 B2 JP5626460 B2 JP 5626460B2
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electronic component
bumps
bare
component module
substrate
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JPWO2012147480A1 (ja
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紳弥 清野
紳弥 清野
祥明 佐竹
祥明 佐竹
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

本発明は、基板の一方の面に設けてある複数のバンプに、電子部品の複数の外部端子をそれぞれ接合する電子部品モジュールの製造方法及び該製造方法で製造された電子部品モジュールに関する。
特許文献１には、基板にバンプを介して半導体装置を接合するバンプの形成方法が開示してある。図１は、従来の電子部品モジュールの製造方法を示す模式断面図である。図１（ａ）に示すように、特許文献１では、基板９の表面電極１０上に、インクヘッド３から金属ペースト４を吐出して乾燥させて、バンプ６を形成する。
次に、図１（ｂ）に示すように、ベアＩＣ（外部端子付き電子部品）１の外部端子２が基板９のバンプ６にそれぞれ対向するように位置合わせする。そして、図１（ｃ）に示すように、ベアＩＣ１を基板９上に搭載して加圧・加熱することにより、バンプ６を変形させて外部端子２を接合し、ベアＩＣ１を基板９に実装する。
特開２００４−２２８３７５号公報
上述した従来の製造方法では、例えばバンプ６の厚さが厚く形成された場合、変形したバンプ６がベアＩＣ１の側面にまで回り込み、基板９の表面電極１０とベアＩＣ１の内部配線とが導通するおそれがあった。したがって、上述した従来の製造方法で製造した電子部品モジュールは、ベアＩＣ１の特性が劣化するおそれがあった。
図２は、従来の製造方法で製造した電子部品モジュールの構成を示す断面図である。バンプ６の厚さが厚く形成された場合には、ベアＩＣ１の外部端子２と基板９の表面電極１０との接合部７がベアＩＣ１の側面にまで回り込み、接合部７とベアＩＣ１の側面とが接触する。ベアＩＣ１のダイサーカット時にチッピングが生じた場合、ベアＩＣ１の側面では内部配線がむき出しになることが多い。この場合、接合部７とベアＩＣ１の側面とが接触したときには、基板９の表面電極１０とベアＩＣ１の内部配線とが導通することにより、ベアＩＣ１の特性が劣化する。
本発明は斯かる事情に鑑みてなされたものであり、電子部品の複数の外部端子と基板の表面電極との接合部が、電子部品の側面に接触することがない、電子部品モジュールの製造方法及び該製造方法で製造された電子部品モジュールを提供することを目的とする。
上記目的を達成するために本発明に係る電子部品モジュールの製造方法は、基板の一方の面に設けてある複数のバンプに、電子部品の複数の外部端子をそれぞれ接合する電子部品モジュールの製造方法において、複数の前記バンプそれぞれは、厚さが厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成されており、前記電子部品を平面視した場合に、前記厚肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側に位置するように、前記薄肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側と反対側に位置するように、前記基板の一方の面にそれぞれ形成する工程と、複数の前記バンプをそれぞれ変形させて複数の前記外部端子をそれぞれ接合した複数の接合部を、前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成する工程とを含むことを特徴とする。
上記構成では、複数のバンプそれぞれは、厚さが厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成されている。そして、電子部品を平面視した場合に、厚肉部は、対応するそれぞれの外部端子の、電子部品の中央側に位置するように、薄肉部は、対応するそれぞれの外部端子の、電子部品の中央側と反対側に位置するように、基板の一方の面に形成する。複数のバンプをそれぞれ変形させて複数の外部端子をそれぞれ接合した複数の接合部を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成するので、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
また、本発明に係る電子部品モジュールの製造方法は、複数の前記バンプを、それぞれ階段状に形成することが好ましい。
上記構成では、複数のバンプを、それぞれ階段状に形成するので、接合部を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成することができ、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
また、本発明に係る電子部品モジュールの製造方法は、複数の前記バンプを、インクジェット法により形成することが好ましい。
上記構成では、複数のバンプを、インクジェット法により形成するので、金属ペーストの吐出回数を調整することにより厚さの異なる薄肉部と厚肉部とを容易に形成することができる。また、薄肉部から厚肉部までを一気に形成することができ、製造コストを低減することが可能となる。
次に、上記目的を達成するために本発明に係る電子部品モジュールは、基板と、該基板の一方の面に設けてある複数のバンプと、複数の外部端子を有する電子部品と、複数の前記バンプをそれぞれ変形させて複数の前記外部端子をそれぞれ接合した複数の接合部の周囲を封止する樹脂とを備える電子部品モジュールにおいて、複数の前記接合部は、それぞれ前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成してあることを特徴とする。
上記構成では、複数のバンプをそれぞれ変形させて複数の外部端子をそれぞれ接合した複数の接合部の周囲を封止する樹脂を備えており、それぞれ電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成してあるので、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
また、本発明に係る電子部品モジュールは、複数の前記バンプは、前記電子部品を平面視した場合の中心を挟んで対向する位置に、それぞれ一対となるように配置してあることが好ましい。
上記構成では、複数のバンプは、電子部品を平面視した場合の中心を挟んで対向する位置に、それぞれ一対となるように配置してあるので、電子部品を実装した場合に、押圧力のバランスをとることができ、複数のバンプの変形具合を均等にすることができるので、接合強度に偏りが生じることを未然に防止することが可能となる。
上記構成によれば、複数のバンプそれぞれは、厚さが厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成されている。そして、電子部品を平面視した場合に、厚肉部は、対応するそれぞれの外部端子の、電子部品の中央側に位置するように、薄肉部は、対応するそれぞれの外部端子の、電子部品の中央側と反対側に位置するように、基板の一方の面に形成する。複数のバンプをそれぞれ変形させて複数の外部端子をそれぞれ接合した複数の接合部を、電子部品を平面視した場合の電子部品の中央側の高さより電子部品の中央側と反対側の高さの方が低くなるよう形成するので、接合部が電子部品の側面に接触することがなく、ダイサーカットにより電子部品の側面に内部配線がむき出しになっている場合であっても、電子部品の特性が劣化することがない。
従来の電子部品モジュールの製造方法を示す模式断面図である。 従来の製造方法で製造した電子部品モジュールの構成を示す断面図である。 本発明の実施の形態に係る電子部品モジュールの、ベアＩＣ実装前の構成を示す断面図である。 本発明の実施の形態に係る電子部品モジュールの構成を示す断面図である。 基板の一部を示す拡大断面図である。 本発明の実施の形態に係る電子部品モジュールの製造方法を示す模式断面図である。 本発明の実施の形態に係る電子部品モジュールにおけるバンプの配置を示す平面透視図である。 本発明の実施の形態に係る電子部品モジュールにおけるバンプの形状が異なる場合の、バンプの配置を示す平面透視図である。 本発明の実施の形態に係る電子部品モジュールにおけるベアＩＣの外部端子が２個である場合の、バンプの配置を示す平面透視図である。 本発明の実施の形態に係る電子部品モジュールの、バンプの形状が異なる場合の、ベアＩＣ実装前の構成を示す断面図である。
以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。
図３は、本発明の実施の形態に係る電子部品モジュールの、ベアＩＣ実装前の構成を示す断面図である。図３に示すように、基板９の一方の面に表面電極１０を設けてあり、バンプ６は、表面電極１０上に階段状に形成されている。
すなわち、バンプ６は、厚さが薄い部分である薄肉部６１と、厚さが厚い部分である厚肉部６２とで構成されている。厚肉部６２は、電子部品を実装する場合に、対応するそれぞれの外部端子２の、電子部品を平面視した場合の中央側に位置するように、薄肉部６１は、対応するそれぞれの外部端子２の、電子部品を平面視した場合の中央側と反対側に位置するように、基板９の一方の面にそれぞれ形成してある。以下、外部端子付きの電子部品であるベアＩＣを実装する場合を例に説明する。
図４は、本発明の実施の形態に係る電子部品モジュールの構成を示す断面図である。ベアＩＣ１の外部端子２が基板９のバンプ６にそれぞれ対向するように位置合わせした後、ベアＩＣ１を基板９上に搭載して加圧・加熱することにより、図４に示すようにバンプ６を変形させて外部端子２を接合し、ベアＩＣ１を基板９に実装する。
本実施の形態では、バンプ６を変形させて、外部端子２を接合した部分を接合部７としている。接合部７は、ベアＩＣ１を平面視した場合の中央側の高さよりベアＩＣ１を平面視した場合の中央側と反対側の高さの方が低くなるよう形成してある。したがって、変形したバンプ６がベアＩＣ１の側面にまで回り込むことがない。これにより、ベアＩＣ１のダイサーカット時にチッピングが生じ、ベアＩＣ１の側面で内部配線がむき出しになっている場合であっても、基板９の表面電極１０とベアＩＣ１の内部配線とが導通することがなく、ベアＩＣ１の特性が劣化することがない。
以下、本実施の形態に係る電子部品モジュールの製造方法について具体的に説明する。図５は、基板９の一部を示す拡大断面図である。基板９はフレキシブルな樹脂で形成されており、図５に示すように、基板９の一方の面に表面電極１０が設けられている。表面電極１０は、下地であるニッケル層１０２、銅層１０３の上に、Ａｕメッキ１０１を施して構成されている。
Ａｕメッキ１０１の上に、インクヘッドから金属ペーストを吐出することによりバンプ６を所望の形状に形成する。金属ペーストとしては、例えばＡｇペーストを用いる。吐出回数を調整することにより厚さの異なる薄肉部６１と厚肉部６２とを容易に形成することができる。
もちろん、バンプ６の形成方法は、インクジェット法に限定されるものではない。例えば、スクリーン印刷法でバンプ６を形成しても良い。スクリーン印刷法でバンプ６を形成する場合、薄肉部６１を形成した後、一旦乾燥させ、スクリーン版を取り換えてから薄肉部６１の一部に厚肉部６２を形成する必要がある。しかし、インクジェット法でバンプ６を形成する場合には、薄肉部６１から厚肉部６２までを一気に形成することができ、製造コストを低減することが可能となる。
また、ベアＩＣ１の外部端子２は、逆円錐台形状であり、ベアＩＣ１の外部電極であるＡｌパッド上にＡｕワイヤバンプにより形成されている。本実施の形態では、Ａｕワイヤバンプの外径は８５μｍ、高さは２５μｍである。なお、Ａｕワイヤバンプの代わりに、Ａｕめっきバンプ、Ｃｕワイヤバンプ、Ｃｕめっきバンプを用いても良い。また、外部端子２は、めっきバンプにより円盤形状に形成しても良い。
図６は、本発明の実施の形態に係る電子部品モジュールの製造方法を示す模式断面図である。図６（ａ）に示すように、まず基板９の表面電極１０上に、インクヘッド３から金属ペースト４を吐出し、図６（ｂ）に示すように薄肉部６１を形成する。具体的にはインクヘッド３又は基板９を載置してあるテーブルを移動させながら、金属ペースト４を吐出する。金属ペースト４としてＡｇペーストを用い、インクヘッド３から吐出されるＡｇペーストの１ドットは１ｐｌ（１×１０-15 ｍ3 ）である。本実施の形態では、インクヘッド３を載置してあるテーブルを水平方向（図６の左右方向）へ移動させながら金属ペースト４を２回吐出することにより、厚さ２０μｍの薄肉部６１を形成している。
次に、図６（ｃ）に示すように、厚肉部６２を形成する。厚肉部６２についても、インクヘッド３を載置してあるテーブルを水平方向へ移動させながら金属ペースト４を８回吐出する。これにより、ベアＩＣ１を平面視した場合の中央側における厚さが１００μｍのバンプ６を形成している。そして、形成したバンプ６を乾燥させる。吐出される金属ペースト４が微小滴であるため、特段の乾燥装置を用いずに自然乾燥させることもできる。
本実施の形態では、厚肉部６２の厚さと薄肉部６１の厚さとの比率が約５：１となっているが、特にこれに限定されるものではなく、ベアＩＣ１の実装時にベアＩＣ１の側面に変形したバンプ６が回り込まなければ、例えば２：１であっても良い。また、水平方向（図６の左右方向）の幅は、本実施の形態では厚肉部６２が５０μｍ、薄肉部６１が１００μｍとしているが、特にこれに限定されるものではなく、例えば厚肉部６２の幅が１０μｍであっても良い。
形成したバンプ６を乾燥させた後、ベアＩＣ（外部端子付き電子部品）１の外部端子２が基板９のバンプ６にそれぞれ対向するように位置合わせする。そして、図６（ｄ）に示すように、ベアＩＣ１を基板９上に搭載して加圧・加熱することにより、バンプ６を変形させて外部端子２を接合し、ベアＩＣ１を基板９に実装する。なお、ベアＩＣ１の外部端子２の中心が、厚肉部６２と重ならないよう位置合わせする。これにより、変形したバンプ６がベアＩＣ１の側面に回り込みにくくなる。
図７は、本発明の実施の形態に係る電子部品モジュールにおけるバンプ６の配置を示す平面透視図である。ベアＩＣ１の外部端子２を白丸印で示しており、バンプ６にはハッチングが施してある。複数のバンプ６は、ベアＩＣ１を平面視した場合の中心７１を挟んで対向する位置に、それぞれ一対となるように配置してある。
また、バンプ６の厚肉部６２は、ベアＩＣ１を平面視した場合の中心７１を挟んで対向する位置に、それぞれ一対となるように形成されている。したがって、ベアＩＣ１を実装した場合に、押圧力のバランスをとることができ、複数のバンプ６の変形具合を均等にすることができるので、接合強度に偏りが生じることを未然に防止することが可能となる。
なお、バンプ６は、図７に示すように、平面視した形状が矩形であることに限定されるものではない。図８は、本発明の実施の形態に係る電子部品モジュールにおけるバンプ６の形状が異なる場合の、バンプ６の配置を示す平面透視図である。図８に示すように、平面視した形状が略楕円形である薄肉部６１と、平面視した形状が略楕円形である厚肉部６２とで、平面視した形状が略楕円形であるバンプ６を構成しても良い。この場合もバンプ６は、ベアＩＣ１を平面視した場合の中心７１を挟んで対向する位置に、それぞれ一対となるように配置してある。また、バンプ６の厚肉部６２は、ベアＩＣ１を平面視した場合の中心７１を挟んで対向する位置に、それぞれ一対となるように形成されている。
また、外部端子２の数も特に制約があるものではなく、最低限２個あれば足りる。図９は、本発明の実施の形態に係る電子部品モジュールにおけるベアＩＣ１の外部端子２が２個である場合の、バンプ６の配置を示す平面透視図である。
図９に示すように、外部端子２が２個である場合には、ベアＩＣ１を安定して実装するという観点から外部端子２は、平面視した形状が矩形であることが多い。そして、外部端子２の長手方向の中心線よりもベアＩＣ１を平面視した場合の中央側に厚肉部６２が、反対側に薄肉部６１が位置するように、階段状のバンプ６を形成することにより、同様の効果が期待できる。
図６に戻って、最後に図６（ｅ）に示すように、接合部７の周囲を絶縁樹脂８で封止して、電子部品モジュールとして完成する。
以上のように本実施の形態によれば、形成した複数のバンプ６を変形させて複数の外部端子２を接合した複数の接合部７を、ベアＩＣ１を平面視した場合の中央側の高さよりベアＩＣ１を平面視した場合の中央側と反対側の高さの方が低くなるよう形成してあるので、接合部７がベアＩＣ１の側面に接触することがなく、ダイサーカットによりベアＩＣ１の側面に内部配線がむき出しになっている場合であっても、ベアＩＣ１の特性が劣化することがない。
なお、上述した実施の形態では、バンプ６が厚肉部６２と薄肉部６１との２段の階段状に形成されているが、特に２段に限定されるものではない。図１０は、本発明の実施の形態に係る電子部品モジュールの、バンプ６の形状が異なる場合の、ベアＩＣ１実装前の構成を示す断面図である。
図１０（ａ）では、バンプ６を厚肉部、中間部、薄肉部の３段の階段状に形成した場合の例を示している。もちろん、ベアＩＣ１を平面視した場合の中央側に近いほど厚さが厚くなるように形成してあることは言うまでもない。また、インクヘッド３から吐出する金属ペースト４の量を精緻に制御できるのであれば、図１０（ｂ）に示すように、ベアＩＣ１を平面視した場合の中央側に近いほど厚さが厚くなるよう傾斜したバンプ６を形成しても良い。
また、本発明は上記実施の形態に限定されるものではなく、本発明の趣旨の範囲内であれば多種の変更、改良等が可能である。例えばベアＩＣのような電子部品を基板に実装した電子部品モジュールだけでなく、小型サイズの電子部品を内蔵した中型サイズの電子部品を基板に実装した電子部品モジュールであっても良い。一例としては、小型サイズの電子部品を基板と共に樹脂封止した後、天面や側面に電磁波シールド部を形成した電子部品モジュールも、本発明を適用して製造することができる。
１ ベアＩＣ（外部端子付き電子部品）
２ 外部端子
４ 金属ペースト
６ バンプ
７ 接合部
８ 絶縁樹脂
９ 基板
１０ 表面電極
６１ 薄肉部
６２ 厚肉部

Claims (5)

  1. 基板の一方の面に設けてある複数のバンプに、電子部品の複数の外部端子をそれぞれ接合する電子部品モジュールの製造方法において、
    複数の前記バンプそれぞれは、厚さが厚い部分である厚肉部と厚さが薄い部分である薄肉部とで構成されており、前記電子部品を平面視した場合に、前記厚肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側に位置するように、前記薄肉部は、対応するそれぞれの前記外部端子の、前記電子部品の中央側と反対側に位置するように、前記基板の一方の面にそれぞれ形成する工程と、
    複数の前記バンプをそれぞれ変形させて複数の前記外部端子をそれぞれ接合した複数の接合部を、前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成する工程と
    を含むことを特徴とする電子部品モジュールの製造方法。
  2. 複数の前記バンプを、それぞれ階段状に形成することを特徴とする請求項１に記載の電子部品モジュールの製造方法。
  3. 複数の前記バンプを、インクジェット法により形成することを特徴とする請求項１又は２に記載の電子部品モジュールの製造方法。
  4. 基板と、
    該基板の一方の面に設けてある複数のバンプと、
    複数の外部端子を有する電子部品と、
    複数の前記バンプをそれぞれ変形させて複数の前記外部端子をそれぞれ接合した複数の接合部の周囲を封止する樹脂と
    を備える電子部品モジュールにおいて、
    複数の前記接合部は、それぞれ前記電子部品を平面視した場合の前記電子部品の中央側の高さより前記電子部品の中央側と反対側の高さの方が低くなるよう形成してあることを特徴とする電子部品モジュール。
  5. 複数の前記バンプは、前記電子部品を平面視した場合の中心を挟んで対向する位置に、それぞれ一対となるように配置してあることを特徴とする請求項４に記載の電子部品モジュール。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008026504A1 (fr) * 2006-09-01 2008-03-06 Panasonic Corporation Dispositif et procédé de montage de composant électronique
JP2008060483A (ja) * 2006-09-01 2008-03-13 Sharp Corp 半導体装置の実装構造体およびその製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3824865A1 (de) * 1988-07-21 1990-01-25 Productech Gmbh Herstellen von loetflaechen
US5291375A (en) * 1991-09-30 1994-03-01 Kabushiki Kaisha Toshiba Printed circuit board and electric device configured to facilitate bonding
JPH0677632A (ja) * 1992-02-24 1994-03-18 Matsushita Electric Ind Co Ltd 回路基板
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
US5663529A (en) * 1995-09-14 1997-09-02 Ford Motor Company Anti-skew mounting pads and processing method for electronic surface mount components
JP3783754B2 (ja) * 1998-02-27 2006-06-07 富士ゼロックス株式会社 絶縁性基板および半導体装置および半導体実装装置
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
JP2001284783A (ja) * 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd 表面実装用基板及び表面実装構造
JP2004228375A (ja) 2003-01-23 2004-08-12 Seiko Epson Corp バンプの形成方法、デバイス、及び電子機器
JP4175197B2 (ja) * 2003-06-27 2008-11-05 株式会社デンソー フリップチップ実装構造
US7860495B2 (en) * 2004-08-09 2010-12-28 Siemens Industry Inc. Wireless building control architecture
EP1720389B1 (en) 2005-04-25 2019-07-03 Brother Kogyo Kabushiki Kaisha Method for forming pattern and a wired board
JP4817892B2 (ja) * 2005-06-28 2011-11-16 富士通セミコンダクター株式会社 半導体装置
JP4962217B2 (ja) * 2007-08-28 2012-06-27 富士通株式会社 プリント配線基板及び電子装置製造方法
US7851928B2 (en) * 2008-06-10 2010-12-14 Texas Instruments Incorporated Semiconductor device having substrate with differentially plated copper and selective solder
US9095066B2 (en) * 2008-06-18 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Printed board
US8018027B2 (en) * 2009-10-30 2011-09-13 Murata Manufacturing Co., Ltd. Flip-bonded dual-substrate inductor, flip-bonded dual-substrate inductor, and integrated passive device including a flip-bonded dual-substrate inductor
JP5991915B2 (ja) * 2012-12-27 2016-09-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6476871B2 (ja) * 2014-05-22 2019-03-06 株式会社村田製作所 回路基板、蓄電装置、電池パックおよび電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008026504A1 (fr) * 2006-09-01 2008-03-06 Panasonic Corporation Dispositif et procédé de montage de composant électronique
JP2008060483A (ja) * 2006-09-01 2008-03-13 Sharp Corp 半導体装置の実装構造体およびその製造方法

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