CN103493191B - 电子元器件模块的制造方法及电子元器件模块 - Google Patents
电子元器件模块的制造方法及电子元器件模块 Download PDFInfo
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- CN103493191B CN103493191B CN201280020504.9A CN201280020504A CN103493191B CN 103493191 B CN103493191 B CN 103493191B CN 201280020504 A CN201280020504 A CN 201280020504A CN 103493191 B CN103493191 B CN 103493191B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 3
- 239000002562 thickening agent Substances 0.000 description 15
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000009738 saturating Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
本发明提供一种电子元器件的多个外部端子与基板的表面电极的接合部不会与电子元器件的侧面发生接触的电子元器件模块的制造方法以及由该制造方法所制造出的电子元器件模块。多个凸点(6)由厚度较厚的部分即厚壁部和厚度较薄的部分即薄壁部所构成,在俯视电子元器件时,厚壁部位于相应的各个外部端子(2)的电子元器件的中央侧,薄壁部位于相应的各个外部端子(2)的与电子元器件的中央侧相反的一侧,以此方式在基板的一个面上分别形成厚壁部和薄壁部。使所形成的多个凸点(6)发生变形后与多个外部端子(2)接合而成的多个接合部(7)形成为,与俯视电子元器件时的电子元器件的中央侧的高度相比,与电子元器件的中央侧相反的一侧的高度较低。
Description
技术领域
本发明涉及将电子元器件的多个外部端子分别与设置在基板的一个面上的多个凸点接合的电子元器件模块的制造方法以及由该制造方法所制造出的电子元器件模块。
背景技术
专利文献1中公开了一种将半导体装置经由凸点与基板接合的凸点的形成方法。图1是表示现有的电子元器件模块的制造方法的示意剖视图。如图1(a)所示,专利文献1中,由喷墨头3在基板9的表面电极10上排出金属糊料4,并使其干燥,从而形成凸点6。
接下来,如图1(b)所示,将裸片IC(带外部端子的电子元器件)1的外部端子2进行对位以与基板9的凸点6分别相对。然后,如图1(c)所示,将裸片IC1装载在基板9上并进行加压、加热,使凸点6变形来与外部端子2接合,从而将裸片IC1安装在基板9上。
现有技术文献
专利文献
专利文献1:日本专利特开2004―228375号公报
发明内容
发明所要解决的技术问题
在上述的现有的制造方法中,例如,在将凸点6的厚度形成得较厚的情况下,存在发生了变形的凸点6绕到裸片IC1的侧面、导致基板9的表面电极10与裸片IC1的内部布线发生导通的可能性。因此,由上述现有的制造方法所制造出的电子元器件模块存在裸片IC1的特性变差的可能性。
图2是表示由现有的制造方法所制造出的电子元器件模块的结构的剖视图。在凸点6的厚度形成得较厚的情况下,裸片IC1的外部端子2与基板9的表面电极10的接合部7绕到裸片IC1的侧面,接合部7与裸片IC1的侧面相接触。在利用切割机切割裸片IC1时会产生碎屑,在此情况下,内部布线常常会在裸片IC1的侧面露出。在此情况下,在接合部7与裸片IC1的侧面发生接触时,基板9的表面电极10与裸片IC1的内部布线导通,导致裸片IC的特性变差。
本发明是鉴于上述的技术问题而完成的,其目的在于提供一种电子元器件的多个外部端子与基板的表面电极的接合部不会与电子元器件的侧面发生接触的电子元器件模块的制造方法以及由该制造方法所制造出的电子元器件模块。
解决技术问题所采用的技术方案
为了达到上述目的,本发明所涉及的电子元器件模块的制造方法是将电子元器件的多个外部端子分别与设置在基板的一个面上的多个凸点相接合的电子元器件模块的制造方法,该电子元器件模块的制造方法的特征在于,包含:多个所述凸点由厚度较厚的部分即厚壁部和厚度较薄的部分即薄壁部所构成,在俯视所述电子元器件时,所述厚壁部位于相应的各个所述外部端子的所述电子元器件的中央侧,所述薄壁部位于相应的各个所述外部端子的与所述电子元器件的中央侧相反的一侧,以此方式在所述基板的一个面上分别形成所述厚壁部和所述薄壁部的工序;以及对于使所形成的多个所述凸点发生变形后与多个所述外部端子接合而成的多个接合部,相比俯视所述电子元器件时的所述电子元器件的中央侧的高度,使与所述电子元器件的中央侧相反的一侧的高度形成得较低的工序。
在上述结构中,多个凸点由厚度较厚的部分即厚壁部和厚度较薄的部分即薄壁部所构成。而且,在俯视电子元器件时,厚壁部位于相应的各个外部端子的电子元器件的中央侧,薄壁部位于相应的各个外部端子的与电子元器件的中央侧相反的一侧,以此方式在基板的一个面上分别形成厚壁部和薄壁部。使所形成的多个凸点发生变形后与多个外部端子接合而成的多个接合部形成为,与俯视电子元器件时的电子元器件的中央侧的高度相比,与电子元器件的中央侧相反的一侧的高度较低,因此,接合部不会与电子元器件的侧面发生接触,即使内部布线因切割机的切割而在电子元器件的侧面露出的情况下,电子元器件的特性也不会变差。
此外,本发明所涉及的电子元器件模块的制造方法优选为多个所述凸点形成为台阶状。
在上述结构中,由于多个凸点形成为台阶状,因此,接合部可以形成为,与俯视电子元器件时的电子元器件的中央侧的高度相比,与电子元器件的中央侧相反的一侧的高度较低,接合部不会与电子元器件的侧面相接触,即使内部布线因切割机的切割而在电子元器件的侧面露出的情况下,电子元器件的特性也不会变差。
此外,本发明所涉及的电子元器件模块的制造方法优选为多个所述凸点是通过喷墨法形成的。
在上述结构中,多个凸点由喷墨法形成,因此,通过调节金属糊料的排出次数,能容易地形成不同厚度的薄壁部和厚壁部。而且,从薄壁部到厚壁部能一下子形成,能降低制造成本。
接下来,为了达到上述目的,本发明所涉及的电子元器件模块包括:基板;设置在该基板的一个面上的多个凸点;具有多个外部端子的电子元器件;以及对使多个所述凸点变形后与多个所述外部端子接合而成的多个接合部的周围进行封固的树脂,该电子元器件模块的特征在于,多个所述接合部形成为,与俯视所述电子元器件时的所述电子元器件的中央侧的高度相比,与所述电子元器件的中央侧相反的一侧的高度较低。
在上述结构中,多个接合部可以形成为,与俯视电子元器件时的电子元器件的中央侧的高度相比,与电子元器件的中央侧相反的一侧的高度较低,因此,接合部不会与电子元器件的侧面相接触,即使内部布线因切割机的切割而在电子元器件的侧面露出的情况下,电子元器件的特性也不会变差。
此外,本发明所涉及的电子元器件模块优选为多个所述凸点配置成在隔着俯视所述电子元器件时的中心的相对位置上分别成为一对。
在上述结构中,多个凸点配置成在隔着俯视电子元器件时的中心的相对位置上分别成为一对,因此,在安装电子元器件时,能使推压力平衡,能使多个凸点的变形程度均等,因此,能预防接合强度产生偏差。
发明的技术效果
根据上述结构,多个凸点由厚度较厚的部分即厚壁部和厚度较薄的部分即薄壁部所构成。而且,在俯视电子元器件时,厚壁部位于相应的各个外部端子的电子元器件的中央侧,薄壁部位于相应的各个外部端子的与电子元器件的中央侧相反一侧,以此方式在基板的一个面上分别形成厚壁部和薄壁部。使所形成的多个凸点发生变形后与多个外部端子接合而成的多个接合部形成为,与俯视电子元器件时的电子元器件的中央侧的高度相比,与电子元器件的中央侧相反的一侧的高度较低,因此,接合部不会与电子元器件的侧面发生接触,即使内部布线因切割机的切割而在电子元器件的侧面露出的情况下,电子元器件的特性也不会变差。
附图说明
图1是表示现有的电子元器件模块的制造方法的示意剖视图。
图2是表示由现有的制造方法所制造出的电子元器件模块的结构的剖视图。
图3是表示本发明的实施方式所涉及的电子元器件模块的安装裸片IC之前的结构的剖视图。
图4是表示本发明的实施方式所涉及的电子元器件模块的结构的剖视图。
图5是表示基板的一部分的放大剖视图。
图6是表示本发明的实施方式所涉及的电子元器件模块的制造方法的示意剖视图。
图7是表示本发明的实施方式所涉及的电子元器件模块中的凸点的配置的俯视透视图。
图8是表示本发明的实施方式所涉及的电子元器件模块中的凸点的形状不同时的、凸点的配置的俯视透视图。
图9是表示本发明的实施方式所涉及的电子元器件模块中的裸片IC的外部端子为两个时的、凸点的配置的俯视透视图。
图10是表示本发明的实施方式所涉及的电子元器件模块在凸点的形状不同时的、安装裸片IC之前的结构的剖视图。
具体实施方式
以下,参照附图对本发明的实施方式进行详细说明。
图3是表示本发明的实施方式所涉及的电子元器件模块的、安装裸片IC之前的结构的剖视图。如图3所示,在基板9的一个面上设有表面电极10,凸点6在表面电极10上形成为台阶状。
即,凸点6由厚度较薄的部分即薄壁部61、以及厚度较厚的部分即厚壁部62所构成。在安装电子元器件时,使厚壁部62位于相应的各个外部端子2的、俯视电子元器件时的中央侧,并使薄壁部61位于相应的各个外部端子2的、与俯视电子元器件时的中央侧相反一侧,以此方式在基板9的一个面上分别形成厚壁部62和薄壁部61。以下,以安装带外部端子的电子元器件即裸片IC的情况为例进行说明。
图4是表示本发明的实施方式所涉及的电子元器件模块的结构的剖视图。将裸片IC1的外部端子2进行对位以使其与基板9的凸点6分别相对,然后,将裸片IC1装载在基板9上并进行加压、加热,如图4所示使凸点6变形来与外部端子2接合,从而将裸片IC1安装在基板9上。
本实施方式中,将使凸点6发生变形后与外部端子2接合的部分作为接合部7。接合部7形成为与俯视裸片IC1时的中央侧相反的一侧的高度低于俯视裸片IC1时的中央侧的高度。因此,发生了变形的凸点6不会绕到裸片IC1的侧面。由此,即使在利用切割机切割裸片IC1时产生破碎、内部布线在裸片IC1的侧面露出的情况下,基板9的表面电极10与裸片IC1的内部布线也不会发生导通,裸片IC的特性不会变差。
以下,对本实施方式所涉及的电子元器件模块的制造方法进行具体的说明。图5是表示基板9的一部分的放大剖视图。基板9由柔性树脂所形成,如图5所示,在基板9的一个面上设有表面电极10。表面电极10通过在作为衬底的镍层102、铜层103上施加Au镀膜101而构成。
由喷墨头在Au镀膜101上排出金属糊料,使凸点6形成为所希望的形状。例如,使用Ag糊料作为金属糊料。通过调节排出次数,能容易地形成不同厚度的薄壁部61和厚壁部62。
当然,凸点6的形成方法并不限定于喷墨法。例如,也可以利用丝网印刷法来形成凸点6。在利用丝网印刷法来形成凸点6时,需要在形成薄壁部61之后,暂且使其干燥,更换丝网版,然后在薄壁部61的一部分上形成厚壁部62。然而,在利用喷墨法形成凸点6时,从薄壁部61到厚壁部62能一下子形成,能降低制造成本。
此外,裸片IC1的外部端子2为倒圆锥台形状,其在裸片IC1的外部电极即Al焊盘上通过Au引线凸点(wire bump)来形成。在本实施方式中,Au引线凸点的外径为85μm、高度为25μm。另外,也可以使用Au镀敷凸点、Cu引线凸点、Cu镀敷凸点来取代Au引线凸点。此外,外部端子2也可以通过镀敷凸点形成为圆盘形状。
图6是表示本发明的实施方式所涉及的电子元器件模块的制造方法的示意剖视图。如图6(a)所示,首先,由喷墨头3在基板9的表面电极10上排出金属糊料4,如图6(b)所示形成薄壁部61。具体而言,一边移动载放有喷墨头3或基板9的平台一边排出金属糊料4。使用Ag糊料作为金属糊料4,从喷墨头3排出的Ag糊料的一个点为1pl(1×10-15m3)。在本实施方式中,一边使载放有喷墨头3的平台在水平方向(图6的左右方向)上移动,一边分两次排出金属糊料4,从而形成厚度为20μm的薄壁部61。
接下来,如图6(c)所示形成厚壁部62。对于厚壁部62,也是一边使载放有喷墨头3的平台在水平方向上移动,一边分八次排出金属糊料4。由此,形成俯视裸片IC1时的中央侧的厚度为100μm的凸点6。然后,使所形成的凸点6干燥。由于排出的金属糊料4为微小滴,因此,无需使用特别的干燥装置也能使其自然干燥。
在本实施方式中,厚壁部62的厚度与薄壁部61的厚度的比率约为5:1,但并不特别限定于此,只要在安装裸片IC1时发生了变形的凸点6不绕到裸片IC1的侧面,例如也可以是2:1。此外,对于水平方向(图6的左右方向)的宽度,在本实施方式中将厚壁部62设为50μm,将薄壁部61设为100μm,但并不特别限定于此,例如,厚壁部62的宽度也可以为10μm。
所形成的凸点6干燥后,将裸片IC(带有外部端子的电子元器件)1的外部端子2进行对位以使其与基板9的凸点6分别相对。然后,如图6(d)所示,通过将裸片IC1装载在基板9上并进行加压、加热,使凸点6变形来与外部端子2接合,从而将裸片IC1安装在基板9上。另外,将裸片IC1的外部端子2的中心定位成不与厚壁部62重合。由此,发生变形的凸点6不易绕到裸片IC1的侧面。
图7是表示本发明的实施方式所涉及的电子元器件模块中的凸点6的配置的俯视透视图。用白色圆形标记表示裸片IC1的外部端子2,对凸点6施加了阴影。将多个凸点6配置成在隔着俯视裸片IC1时的中心71的相对位置上分别成为一对。
此外,凸点6的厚壁部62形成为在隔着俯视裸片IC1时的中心71的相对位置上分别成为一对。因此,在安装裸片IC1时,能使推压力平衡,能使多个凸点6的变形程度均等,因此,能预防接合强度产生偏差。
另外,如图7所示,凸点6的俯视时的形状为矩形,但并不限定于此。图8是表示本发明的实施方式所涉及的电子元器件模块中的凸点6的形状不同时的、凸点6的配置的俯视透视图。如图8所示,也可以由俯视时的形状为近似椭圆形的薄壁部61、以及俯视时的形状为近似椭圆形的厚壁部62来构成俯视时的形状为近似椭圆形的凸点6。在此情况下,凸点6也配置成在隔着俯视裸片IC1时的中心71的相对位置上分别成为一对。此外,凸点6的厚壁部62形成为在隔着俯视裸片IC1时的中心71的相对位置上分别成为一对。
此外,外部端子2的数量也没有特别的限制,最低限度两个就够了。图9是表示本发明的实施方式所涉及的电子元器件模块中的裸片IC1的外部端子2为两个时的、凸点6的配置的俯视透视图。
如图9所示,当外部端子2为两个时,出于稳定地安装裸片IC1这一观点,大多情况下外部端子2的俯视时的形状为矩形。而且,通过形成台阶状的凸点6,并使厚壁部62位于比外部端子2的长度方向的中心线更靠俯视裸片IC1时的中央侧,使薄壁部61位于相反侧,能期待同样的效果。
返回图6,最后,如图6(e)所示,利用绝缘树脂8对接合部7的周围进行封固,从而完成电子元器件模块。
如上所述,根据本实施方式,使所形成的多个凸点6发生变形后与多个外部端子2接合而成的多个接合部7形成为,与俯视裸片IC1时的中央侧的高度相比,与俯视裸片IC1时的中央侧相反的一侧的高度较低,因此,接合部7不会与裸片IC1的侧面接触,即使内部布线因切割机的切割而在裸片IC1的侧面露出的情况下,裸片IC1的特性也不会变差。
另外,在上述的实施方式中,凸点6形成为厚壁部62和薄壁部61这样两个台阶的台阶状,但并不特别限定于两个台阶。图10是表示本发明的实施方式所涉及的电子元器件模块在凸点6的形状不同时的、安装裸片IC1之前的结构的剖视图。
在图10(a)中,例示了使凸点6形成为厚壁部、中间部、薄壁部这样三个台阶的台阶状的情况。当然,毫无疑问,越靠近俯视裸片IC1时的中央侧厚度形成得越厚。此外,如果能精密地控制从喷墨头3排出的金属糊料4的量,则如图10(b)所示,也可以形成倾斜的凸点6,并使越靠近俯视裸片IC1时的中央侧厚度越厚。
此外,本发明并不限定于上述实施方式,只要在本发明的技术思想的范围内,能进行多种变更、改良等。例如,不仅是将裸片IC这样的电子元器件安装在基板上而成的电子元器件模块,也可以是将内置有小型尺寸的电子元器件的中型尺寸的电子元器件安装在基板上而成的电子元器件模块。作为一个示例,也可以应用本发明制造出以下的电子元器件模块:即,将小型尺寸的电子元器件与基板一起进行树脂封固之后,在顶面或侧面形成电磁波屏蔽部的电子元器件模块。
标号说明
1 裸片IC(带有外部端子的电子元器件)
2 外部端子
4 金属糊料
6 凸点
7 接合部
8 绝缘树脂
9 基板
10 表面电极
61 薄壁部
62 厚壁部
Claims (4)
1.一种电子元器件模块的制造方法,该方法用于制造将裸片IC的多个外部端子分别与设置在基板的一个面上的多个凸点接合的电子元器件模块,该电子元器件模块的制造方法的特征在于,包含:
多个所述凸点由厚度较厚的部分即厚壁部和厚度较薄的部分即薄壁部构成为台阶状,在俯视所述裸片IC时,所述厚壁部位于相应的各个所述外部端子的所述裸片IC的中央侧,所述薄壁部位于相应的各个所述外部端子的与所述裸片IC的中央侧相反的一侧,以此方式在所述基板的一个面上的平坦的表面电极分别形成所述厚壁部和所述薄壁部的工序;以及
使所形成的台阶状的多个所述凸点发生变形后与多个所述外部端子接合而成的多个接合部形成为,与俯视所述裸片IC时的所述裸片IC的中央侧的高度相比,与所述裸片IC的中央侧相反的一侧的高度较低的工序,
凸点状的多个所述外部端子形成在所述裸片IC的正下方,
多个所述接合部的至少一部分位于凸点状的多个所述外部端子的正下方,
凸点状的多个所述外部端子与形成于所述平坦的表面电极上的多个所述接合部接合,
多个所述接合部与所述平坦的表面电极的上表面、以及所述裸片IC的底面相接触。
2.如权利要求1所述的电子元器件模块的制造方法,其特征在于,多个所述凸点是通过喷墨法形成的。
3.一种电子元器件模块,包括:
基板;
设置在该基板的一个面上的多个凸点;
具有多个外部端子的裸片IC;以及
对使多个所述凸点发生变形后与多个所述外部端子接合而成的多个接合部的周围进行封固的树脂,
该电子元器件模块的特征在于,
多个所述凸点由厚度较厚的部分即厚壁部和厚度较薄的部分即薄壁部构成为台阶状,以下述方式在所述基板的一个面上的平坦的表面电极分别形成所述厚壁部和所述薄壁部,即:在俯视所述裸片IC时,所述厚壁部位于相应的各个所述外部端子的所述裸片IC的中央侧,所述薄壁部位于相应的各个所述外部端子的与所述裸片IC的中央侧相反的一侧,
多个所述接合部形成为,与俯视所述裸片IC时的所述裸片IC的中央侧的高度相比,与所述裸片IC的中央侧相反的一侧的高度较低,
凸点状的多个所述外部端子形成在所述裸片IC的正下方,
多个所述接合部的至少一部分位于凸点状的多个所述外部端子的正下方,
凸点状的多个所述外部端子与形成于所述平坦的表面电极上的多个所述接合部接合,
多个所述接合部与所述平坦的表面电极的上表面、以及所述裸片IC的底面相接触。
4.如权利要求3所述的电子元器件模块,其特征在于,多个所述凸点配置成在隔着俯视所述裸片IC时的中心的相对位置上分别成为一对。
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PCT/JP2012/059305 WO2012147480A1 (ja) | 2011-04-27 | 2012-04-05 | 電子部品モジュールの製造方法及び電子部品モジュール |
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US (2) | US9532495B2 (zh) |
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- 2012-04-05 EP EP12775989.2A patent/EP2704185A4/en not_active Withdrawn
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JP5626460B2 (ja) | 2014-11-19 |
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KR20130136545A (ko) | 2013-12-12 |
US10177108B2 (en) | 2019-01-08 |
EP2704185A4 (en) | 2014-10-29 |
US20140049922A1 (en) | 2014-02-20 |
WO2012147480A1 (ja) | 2012-11-01 |
US20170084566A1 (en) | 2017-03-23 |
EP2704185A1 (en) | 2014-03-05 |
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