WO2012133098A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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WO2012133098A1
WO2012133098A1 PCT/JP2012/057313 JP2012057313W WO2012133098A1 WO 2012133098 A1 WO2012133098 A1 WO 2012133098A1 JP 2012057313 W JP2012057313 W JP 2012057313W WO 2012133098 A1 WO2012133098 A1 WO 2012133098A1
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insulating resin
resin layer
electrode
substrate
semiconductor
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PCT/JP2012/057313
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English (en)
Japanese (ja)
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田中　明
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日本ゼオン株式会社
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Priority to JP2013507452A priority Critical patent/JPWO2012133098A1/ja
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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    • H01L2924/30—Technical effects
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    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device that is small, thin, and excellent in heat resistance and heat dissipation, and a method for manufacturing the same.
  • a plurality of semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductors), and FWDs (Free Wheel Diodes) are housed in the same package. It is a semiconductor device used for controlling power in various products such as industrial equipment, automobile equipment, and railway equipment. Conventionally, in a power semiconductor module, a package structure using a resin case has been mainly employed (see Patent Document 1).
  • FIG. 8 A schematic diagram showing an example of a conventional power semiconductor module is shown in FIG.
  • a semiconductor element 61 is bonded to one surface of a DBC (Direct Bonded Copper) insulating substrate 60 formed by bonding a copper pattern to the surface of a ceramic substrate by solder (not shown).
  • the semiconductor element 61 and the external lead-out terminal 62 are connected by a bonding wire 63 or a copper pattern (not shown).
  • the other surface of the DBC insulating substrate 60 is joined to the heat dissipation base 64 with a copper pattern (not shown).
  • the DBC insulating substrate 60, the power semiconductor element 61, and the like are housed in a resin case 65, filled with resin or the like (not shown) as needed, and covered with a resin lid 66.
  • Such power semiconductor modules are required to have characteristics such as large current conduction, high heat dissipation characteristics, and heat resistance.
  • the required performance for power semiconductor modules has further increased.
  • high power is required for power semiconductor modules used in hybrid vehicles, solar power generation systems, industrial motor circuit systems, and the like.
  • power semiconductor modules used in products such as automobiles that have limited installation space for components are required to be smaller and thinner.
  • semiconductor chips Measures against heat generated from semiconductor elements (hereinafter sometimes referred to as “semiconductor chips”) are more important than ever to increase the power output, size, and thickness of power semiconductor modules. It is required to further improve the heat resistance and heat dissipation characteristics of the module.
  • the semiconductor substrate that is the material of the semiconductor chip is replaced with a SiC (silicon carbide) substrate or GaN (gallium) that has higher heat resistance and can be operated at a high temperature.
  • a method using a nitride substrate has been attracting attention.
  • the resin material used for the power semiconductor module is preferably excellent in heat resistance.
  • a silicon gel encapsulant that has been widely used in power semiconductor modules in the past has low heat resistance and may be decomposed near 200 ° C. in the presence of oxygen.
  • the high heat-resistant epoxy resin to which the inorganic filler is added is known as a resin having excellent heat resistance
  • the resin melt viscosity becomes high, so that the resin fluidity decreases, voids, There was a risk of disconnection of wiring.
  • Patent Document 2 includes an insulating substrate having a back metal layer above and below a semiconductor chip, and further has a heat dissipation structure such as a heat sink, a heat sink, and a heat pipe on the back surface of each insulating substrate.
  • a power semiconductor module is disclosed.
  • the semiconductor chip can be cooled from above and below.
  • a hard epoxy resin is used as a resin that seals between the two heat sinks, the resin fluidity is lowered, and there is a risk of generating voids or disconnection of wiring. was there.
  • a passivation film may be formed on the surface of these parts with a flexible resin such as a polyimide resin or a polyamideimide resin in order to relieve stress applied to the wiring or the chip.
  • a flexible resin such as a polyimide resin or a polyamideimide resin
  • the thermal expansion coefficient of the resin is large, resulting in a difference in thermal stress between the resin and the surface of the semiconductor chip, peeling of the interface, cracking or deterioration inside the sealed body There was a risk of causing. Further, from the viewpoint of miniaturization of the power semiconductor module, the power semiconductor module described in Patent Document 2 has not been sufficient.
  • thermosetting polyimide resin or polyamideimide resin since the curing temperature of these resins is high, the object is required to have heat resistance in order to form a passivation film on the surface of the component. It was. In addition, there is a problem that residual stress is generated when the resin is cured.
  • JP-A-8-213547 JP 2008-124430 A (US2008 / 0224303A1)
  • a power semiconductor module using a semiconductor chip using a semiconductor substrate having excellent heat resistance and having a double-sided heat dissipation structure has been attracting attention.
  • further studies were necessary.
  • the present invention has been made in view of the above-described circumstances, and is small, thin, excellent in heat resistance and heat dissipation, and a semiconductor device manufacturing method capable of efficiently manufacturing the semiconductor device.
  • the purpose is to provide.
  • the present inventor has one or more of the following: a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate.
  • the semiconductor chip is a semiconductor device in which the back surface electrode is metal-bonded to the heat dissipation substrate, the first insulating resin layer sealing the surface portion of the semiconductor chip, the side surface portion of the semiconductor chip, and the surface of the heat dissipation substrate
  • a semiconductor device having one or two or more first through vias connecting two electrodes has been found to be small and thin and excellent in heat resistance and heat dissipation, and has completed the present invention.
  • the following semiconductor devices (1) to (11) are provided.
  • One or two or more semiconductor chips each including a first surface electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate are a heat dissipation substrate and a metal in the back electrode.
  • a bonded semiconductor device comprising: A first insulating resin layer for sealing the surface portion of the semiconductor chip; A second insulating resin layer for sealing the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate; At least one surface second electrode formed on the first insulating resin layer, and one or two or more that penetrate through the first insulating resin layer and connect the surface first electrode and the surface second electrode A first through via;
  • a semiconductor device comprising: (2) The surface area of the heat dissipation substrate is equal to or greater than the surface area of the semiconductor substrate, and the heat dissipation substrate is metal-bonded to the back electrode so as to cover the entire back surface of the semiconductor substrate.
  • the semiconductor device according to any one of (1) to (3), further including one or more second through vias that penetrate through the second insulating resin layer.
  • a heat dissipation substrate upper electrode connected to the back electrode is provided on the surface of the heat dissipation substrate, and the heat dissipation substrate upper electrode and the surface second electrode are connected by the second through via.
  • the semiconductor device according to (4).
  • the first insulating resin layer is made of an insulating resin forming a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C.
  • the second insulating resin layer is a resin having a thermal expansion coefficient of 2 to 50 ppm / ° C.
  • the semiconductor device according to any one of (1) to (5), which is made of an insulating resin that forms a layer.
  • the first insulating resin layer is made of an insulating resin having a glass transition temperature of 300 ° C. or higher
  • the second insulating resin layer is made of an insulating resin having a glass transition temperature of 240 ° C. or higher.
  • the first insulating resin layer and the second insulating resin layer are made of one or two or more insulating resins selected from the group consisting of a polyimide resin, a polybenzimidazole resin, and a polybenzoxazole resin.
  • the semiconductor device according to any one of (1) to (7), wherein (9) The semiconductor according to any one of (1) to (8), wherein the first through via and / or the second through via are formed by a plating method or a metal bonding method using a metal post material. apparatus.
  • Step 1) a semiconductor chip comprising a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate; One or more first through via forming metal posts formed on the first surface electrode, and a first insulating resin layer for sealing the surface portion of the semiconductor chip and the first through via forming metal post.
  • step 2 A step of metal bonding to the heat dissipation substrate with the back electrode (step 2)
  • a second insulating resin layer forming resin is applied to the surface of the heat dissipation substrate so as to cover the entire semiconductor chip sealing body metal-bonded to the heat dissipation substrate.
  • Step 3 Thinning treatment is performed on the surfaces of the first insulating resin layer and the second insulating resin layer.
  • Step 4 Step of flattening the insulating resin layer and exposing the upper surface of the through via forming metal post (Step 4) Step of forming a surface second electrode on at least the surface of the first insulating resin layer (13)
  • the thickness of the semiconductor substrate is The method for manufacturing a semiconductor device according to (12), which is 400 ⁇ m or less.
  • step 4 a heat dissipating component selected from an insulating heat dissipating sheet having wiring, an insulating heat dissipating substrate having wiring, and a lead electrode having a heat dissipating function is applied to the surface second electrode.
  • Step a) Forming a plating resist film on the surface of the heat dissipation substrate and providing an opening in the plating resist film so that a predetermined portion of the heat dissipation substrate is exposed
  • Step b) Filling the opening with a metal, Step of forming second through via forming metal post
  • step c) Step of removing plating resist film
  • the second through via forming metal post is placed at a predetermined position on the surface of the heat dissipation substrate.
  • the semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.1 to 1.5, 1.7 and 1.8 in this order: (12) to (16 ) A method for manufacturing a semiconductor device according to any one of the above.
  • Step 1.1 Step of depositing a plating resist film on the surface of the semiconductor substrate on which the first surface electrode is formed
  • Step 1.2 A plating resist film so that a predetermined portion of the first surface electrode is exposed.
  • Step 1.3 Step of filling the opening with metal and forming a metal post for forming a first through via
  • Step 1.4 Step of removing the plating resist film (Step 1.
  • a first insulating resin layer forming resin is applied to the surface of the semiconductor substrate so as to cover the first through via forming metal post, and heated at 300 to 450 ° C. to form a first insulating resin layer.
  • Simultaneously annealing the metal posts step 1.7) forming a back electrode on the back surface of the semiconductor substrate (step 1.8) separating the semiconductor substrate by dicing (18)
  • step 1.5 Prior to 1.7), (step 1.6) by the rear surface of the semiconductor substrate of the thinning process, a method of manufacturing a semiconductor device according to a step of the thickness of the semiconductor substrate to 400 ⁇ m or less (17).
  • the semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.9, 1.10, 1.12 and 1.13 in this order (12) to (15 ) A method for manufacturing a semiconductor device according to any one of the above.
  • Step 1.9 Forming a first through via forming metal post by a metal bonding method on the surface first electrode of the semiconductor substrate on which the surface first electrode is formed
  • Step 1.10 A step of applying a first insulating resin layer forming resin to the surface of the semiconductor substrate so as to cover the through via forming metal post and heating at 300 to 450 ° C.
  • Step 1.12) Step of forming a back electrode on the back surface of the semiconductor substrate (Step 1.13) Step of dicing the semiconductor substrate by dicing (20) After (Step 1.10), (Step 1.12) Before (Step 1.11), the method of manufacturing a semiconductor device according to (19), including a step of reducing the thickness of the semiconductor substrate to 400 ⁇ m or less by thinning processing of the back surface of the semiconductor substrate.
  • the semiconductor device of the present invention is small and thin, and has excellent heat resistance and heat dissipation. According to the manufacturing method of the present invention, a semiconductor device that is small, thin, and excellent in heat resistance and heat dissipation can be efficiently manufactured.
  • the manufacturing method of the present invention is useful as a method for manufacturing a semiconductor device of the present invention.
  • a semiconductor device includes one or more semiconductor chips each including a first front electrode formed on a front surface side of a semiconductor substrate and a back electrode formed on a back surface side of the semiconductor substrate.
  • 2 insulating resin layers, at least a surface second electrode formed on the first insulating resin layer, and the first insulating resin layer penetrating and connecting the surface first electrode and the surface second electrode And having one or more first through vias.
  • metal bonding refers to heat-resistant metal bonding in which melt fracture does not occur at high temperatures (usually 300 ° C. or higher, preferably 400 ° C. or higher).
  • Metal bonding methods include direct bonding using nano metal particles such as nano gold particles, nano silver particles, and nano copper particles, bonding using high heat-resistant solder having a heat resistant temperature of 300 ° C. or higher, and bonding metals by high frequency bonding. And the like.
  • a power semiconductor module 100A shown in FIG. 1 includes a semiconductor substrate 200, a front surface first electrode 35 formed on the front surface side of the semiconductor substrate 200, and a back surface electrode 32 on the back surface side of the semiconductor substrate 200.
  • the chip has a structure in which the chip is metal-bonded to the heat dissipation substrate 14 with the back electrode 32.
  • the surface portion of the semiconductor chip is sealed with a first insulating resin layer 20, and the side surface portion of the semiconductor chip and the heat dissipation substrate 14 are sealed with a second insulating resin layer 21.
  • semiconductor chips include power semiconductor chips such as IGBTs, MOSFETs, and FWDs.
  • power semiconductor chips such as IGBTs, MOSFETs, and FWDs.
  • the back surface electrode 32 of the semiconductor chip for example, when the semiconductor chip is an IGBT, an IGBT collector electrode or the like can be cited.
  • the front surface first electrode 35 an IGBT emitter electrode or the like can be cited.
  • Examples of the semiconductor substrate 200 include a Si (silicon) substrate, a SiC (silicon carbide) substrate, and a GaN (gallium nitride) substrate. From the viewpoint of heat resistance, a SiC (silicon carbide) substrate and a GaN (gallium nitride) substrate. ) A substrate is preferred.
  • the thickness of the semiconductor substrate 200 is usually 600 ⁇ m or less, preferably 400 ⁇ m or less, and more preferably 30 ⁇ m to 400 ⁇ m. When the thickness is 400 ⁇ m or less, a thin semiconductor device having excellent conversion efficiency can be obtained.
  • the surface second electrode 36 is formed on the surface of the first insulating resin layer 20 and is connected to the surface first electrode 35 through the first through via 34.
  • the surface second electrode 36 also has a heat dissipation function, and its area can be expanded to a size equivalent to the area of the heat dissipation substrate 14 at the maximum. Therefore, the semiconductor device of the present invention has a high degree of design freedom. As described above, by adopting a structure using the surface second electrode 36 and the first through via 34, a reduction in thickness is achieved, and a double-sided heat dissipation structure including the heat dissipation substrate 14 and the surface second electrode 36 is provided. Thus, high heat dissipation is achieved.
  • heat dissipation substrate 14 examples include copper-clad substrates such as a DBC (Direct Bonded Copper) substrate and an AMC (Active Metal Brazed Copper) substrate.
  • a power semiconductor module 100A shown in FIG. 1 is an example in which a DBC substrate 14 having a structure in which copper patterns 14a are bonded to both surfaces of a ceramic substrate 14b is used as a heat dissipation substrate.
  • the surface area of the heat dissipation substrate 14 is preferably equal to or greater than the surface area of the half-layer substrate 200 constituting the semiconductor chip from the viewpoint of heat dissipation.
  • the heat dissipation substrate 14 is preferably metal-bonded by the back electrode 32 of the semiconductor chip so as to cover the entire back surface of the semiconductor substrate 200.
  • the total installation sectional area of the first through vias 34 is preferably 20% or more, more preferably 20 to 50%, and more preferably 25 to 35% with respect to the sectional area of the surface first electrode 35. Further preferred. Sufficient conductivity can be obtained when the total cross-sectional area of the first through vias 34 is 20% or more with respect to the cross-sectional area of the surface first electrode 35. In addition, heat generated on the surface of the first surface electrode can be efficiently transferred to the surface of the second surface of the surface, thereby suppressing deterioration in conversion efficiency due to temperature rise on the device surface and deterioration of the semiconductor chip due to generation of thermal stress. Can do.
  • the total installation cross-sectional area of the first through via 34 is 50% or less, so that the cost for forming the through via can be suppressed.
  • the first through via 34 can be formed by, for example, a plating method or a metal bonding method using a metal post material.
  • the surface portion of the semiconductor chip is sealed with the first insulating resin layer 20, and the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate 14 are sealed with the second insulating resin layer 21.
  • the elastic modulus of the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is preferably 2 to 8 GPa. As will be described later, a thinning process is performed on these insulating resin layers. At this time, if the elastic modulus exceeds 8 GPa, the resin becomes hard and brittle, and there is a possibility of causing surface roughness during cutting. On the other hand, if the elastic modulus is less than 2 GPa, the resin tends to be stretched during cutting, and the processing speed may be reduced, and it may be difficult to perform beautiful processing.
  • the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is an insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C. in the former, and in the latter.
  • An insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 50 ppm / ° C. is preferable.
  • the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is an insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C.
  • the thermal expansion coefficient of the first insulating resin layer 20 is a value close to the thermal expansion coefficient of the semiconductor substrate 200 constituting the semiconductor chip. It is preferable that For example, when a SiC substrate is used as the semiconductor substrate, the coefficient of thermal expansion of the first insulating resin layer 20 is preferably 2 to 8 ppm / ° C, and more preferably 4 to 6 ppm / ° C.
  • the coefficient of thermal expansion of the first insulating resin layer 20 is preferably 2 to 8 ppm / ° C, and more preferably 4 to 6 ppm / ° C.
  • the thermal expansion coefficient of the second insulating resin layer 21 is preferably a value close to the thermal expansion coefficient of the heat dissipation substrate 14.
  • the thermal expansion coefficient of the main skeleton ceramic portion of the heat dissipation substrate 14 is usually about 8 ppm / ° C.
  • the second insulating resin layer 21 has a thermal expansion rate of 8 to 17 ppm / ° C.
  • the resin layer is made of an insulating resin.
  • the thermal expansion coefficient of the 2nd insulating resin layer 21 when joining an upper thermal radiation sheet and the lead electrode which has a thermal radiation function to the 2nd insulating resin layer 21, it is preferable to adjust the thermal expansion coefficient of the 2nd insulating resin layer 21 according to the thermal expansion coefficient of these materials. . More specifically, when the material of the heat dissipation mechanism is copper or aluminum, it is preferable to match the thermal expansion coefficient of the second insulating resin layer 21 to around 16.3 ppm / ° C. and around 21 ppm / ° C., respectively.
  • the first insulating resin layer 20 and the second insulating resin layer 21 may be formed of the same resin. By doing in this way, resin interface peeling can be suppressed significantly.
  • Examples of the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 include polyimide resin, polybenzimidazole resin, and polybenzoxazole resin. These resins can be used alone or in combination of two or more. Among these, a polyimide resin is preferable.
  • a polyamic acid is synthesized by polycondensation of a rigid structure aromatic tetracarboxylic acid or acid anhydride thereof and a rigid structure aromatic diamine, and then a thermal imide
  • the method include conversion to a polyimide resin by a method such as chemical conversion or chemical imidization.
  • Control of the coefficient of thermal expansion can be achieved by copolymerizing an aromatic tetracarboxylic acid having a flexible structure or an acid anhydride thereof and an aromatic diamine having a flexible structure as necessary.
  • the “rigid structure” means that a rod-like rigid straight chain that has low mobility and cannot be bent by itself is formed, and the flexible structure means that it is not the rigid structure.
  • rigid structure aromatic tetracarboxylic acid examples include pyromellitic dianhydride, 3,3 ′, 4,4′-benzophenone tetracarboxylic dianhydride, benzene-1,2,3,4-tetra Carboxylic dianhydride, 2,2 ′, 3,3′-benzophenone tetracarboxylic dianhydride, 2,3,3 ′, 4′-benzophenone tetracarboxylic dianhydride, naphthalene-2,3,6 7-tetracarboxylic dianhydride, naphthalene-1,2,5,6-tetracarboxylic dianhydride, naphthalene-1,2,4,5-tetracarboxylic dianhydride, naphthalene-1,2,5 , 8-tetracarboxylic dianhydride, naphthalene-1,2,6,7-tetracarboxylic dianhydride, 4,8-dimethyl-1
  • An alicyclic acid dianhydride pyrazine-2,3,5,6-tetracarboxylic dianhydride, pyrrolidine-2,3,4,5-tetracarboxylic dianhydride, thiophene-2,3,4 , 5-tetracarboxylic dianhydrides and the like, and heterocyclic derivative dianhydrides such as tetracarboxylic acids corresponding thereto.
  • aromatic tetracarboxylic acid etc. It is preferable to use at least one selected from the group consisting of acid, pyromellitic dianhydride (PMDA), biphenyltetracarboxylic acid, and biphenyltetracarboxylic dianhydride (s-BPDA).
  • PMDA pyromellitic dianhydride
  • s-BPDA biphenyltetracarboxylic dianhydride
  • rigid aromatic diamines examples include 4,4′-diaminobenzanilide, 4,4′-diamino-2,2′-ditrifluoromethylbiphenyl, and 2,2′-di (p-aminophenyl)- 5,5'-bisbenzoxazole, 2,2'-di (p-aminophenyl) -6,6'-bisbenzoxazole, 2,2'-di (p-aminophenyl) -5,5'-bis Benzimidazole, 3,6- (4-aminophenyl) pyridazine, 4,4'-diaminobenzanilide, p-phenylenediamine (PPDA), 4,4'-diaminobiphenyl, m-phenylenediamine, 1-isopropyl-2 , 4-phenylenediamine, p-phenylenediamine, 4,4′-diaminodiphenyl sulfide, 3,3
  • Examples of the flexible structure aromatic tetracarboxylic acid or acid anhydride used for controlling the thermal expansion coefficient include 3,3 ′, 4,4′-benzophenone tetracarboxylic dianhydride (BTDA).
  • BTDA 4,4′-benzophenone tetracarboxylic dianhydride
  • An aromatic tetracarboxylic acid having a structure in which two or more aromatic rings are bonded by a carbonyl group (> C ⁇ O) or an oxygen atom (—O—) can be used.
  • Examples of the flexible structure diamine include a diamine having a structure in which the bonding position of the substituent bonded to the main chain heterocycle such as 2,5-bis (p-aminobenzoyl) thiophene) is an ortho position or a meta position; Examples thereof include diamines having an ether structure in the main chain such as oxydianiline; diamines having a siloxane structure in the main chain such as 1,3-diaminopropyl-1,1,3,3-tetramethyldisiloxane.
  • flexible structure diamines include 4,4′-diaminodiphenylpropane, 3,3′-diaminodiphenylpropane, 4,4′-diaminodiphenylethane, 3,3′-diaminodiphenylethane, 4,4 Examples include '-diaminodiphenylmethane and 3,3'-diaminodiphenylmethane.
  • the insulating resin constituting the first insulating resin layer 20 has a glass transition temperature of 300 ° C. or higher
  • the insulating resin constituting the second insulating resin layer 21 has a glass transition temperature of 240 ° C. or higher. It is preferable. By using such an insulating resin, a semiconductor device having excellent heat resistance can be obtained.
  • the semiconductor chip, the semiconductor substrate, the first insulating resin layer, the second insulating resin layer, and the like described in the power semiconductor 100A are the same for the power semiconductor modules 100B, 100C, 100D, and 100E described later.
  • FIG. 2 shows an example of a power semiconductor module in which two or more semiconductor chips are mounted in the semiconductor device of the present invention.
  • 2A is a schematic view of the power semiconductor module 100B viewed from above
  • FIG. 2B is a schematic view of the XY cross section of FIG. 2A viewed from the side.
  • a power semiconductor module 100B shown in FIG. 2 has a structure in which three power semiconductor chips are metal-bonded to a wiring metal portion (not shown) of the heat dissipation board 14 at each back electrode 32 on the heat dissipation board 14. Yes. Further, the power semiconductor chip has a semiconductor substrate 200, a front surface first electrode 35, and a back surface electrode 32, which are sealed with a first insulating resin layer, and the front surface first electrode 35 has a first insulating resin layer. It is connected to the surface second electrode 36 through a first through via 34 formed therein.
  • the thickness up to the upper part of the second insulating resin layer 21 in which the three elements are sealed with respect to the surface of the heat dissipation substrate 14 is uniform.
  • the surface first electrode and the surface second electrode become parallel.
  • a cutting method is excellent as will be described later.
  • FIG. 3 A schematic diagram showing an example of a power semiconductor module having a heat dissipation mechanism such as a lower thermal diffusion conductive substrate is shown in FIG.
  • the power semiconductor module 100 ⁇ / b> C shown in FIG. 3 has a structure in which the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15. Therefore, the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat dissipation substrate 14.
  • FIG. 4 shows a schematic diagram of an example of a power semiconductor module having a heat dissipation mechanism such as a lower heat diffusion conductive substrate and an upper heat dissipation sheet.
  • the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15, and is bonded to the surface second electrode lead-out wiring 38.
  • the surface second electrode lead-out wiring 38 and the surface second electrode are connected to each other. It has a metal bonded structure.
  • the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat dissipation substrate 14.
  • the heat generated in the semiconductor chip is efficiently radiated from the upper part of the power semiconductor module 100D.
  • FIG. 5 shows a schematic diagram of another example of a power semiconductor module having a heat dissipation mechanism such as a lower heat diffusion conductive substrate and an upper heat dissipation sheet.
  • the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15, and the upper heat dissipation sheet 16 is bonded to the surface second electrode lead-out wiring 38;
  • the second electrode lead-out wiring 38 is metal-bonded to the front surface second electrode, and
  • the heat dissipation substrate upper electrode 17 connected to the back electrode 32 is provided on the surface of the heat dissipation substrate 14.
  • the surface second electrode 37 is connected by a second through via 39 and has a structure in which the lead electrode 18 having a heat dissipation function is metal-bonded to the surface second electrode 37.
  • the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat radiating substrate 14, is also efficiently radiated from the upper part, and is radiated using the second through via 39. Since the mechanism is provided, the heat generated from the semiconductor chip can be radiated more efficiently. Further, the wiring can be integrated, the semiconductor device can be made thinner and smaller, and the attachment of the upper heat dissipation sheet 16 is also advantageous.
  • an upper heat dissipation board may be used instead of the heat dissipation sheet 16, and a heat dissipation member having a heat dissipation fin can be directly connected.
  • the method is not limited to the method of consolidating the wirings on the upper heat dissipation substrate 16.
  • the wirings can be consolidated on the lower thermal diffusion conductive substrate 15 side.
  • the semiconductor device of the present invention is not limited to the semiconductor device shown in FIGS. 1 to 5, and the type of the semiconductor substrate, the first surface electrode, the back surface electrode, the insulating resin layer, the second surface surface are within the scope not departing from the gist of the present invention.
  • the shape and arrangement of electrodes and through vias can be freely changed.
  • the entire semiconductor chip is sealed with a first insulating resin and a second insulating resin that are excellent in insulation and heat resistance. Therefore, in the semiconductor device of the present invention, the semiconductor chip is protected from moisture and the like, and element deterioration is unlikely to occur. Further, the semiconductor device of the present invention can control the thermal expansion rate of the semiconductor substrate, the heat dissipation substrate, and the sealing resin. Therefore, the interface stress due to the thermal stress difference at the sealing interface can be reduced during the manufacture and use of the semiconductor device, and the semiconductor device manufacturing yield and product reliability are greatly improved.
  • Step 1 a semiconductor chip comprising a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate, and 1 or formed on the front surface first electrode
  • One or more semiconductor chip seals having two or more first through via forming metal posts and a first insulating resin layer for sealing the surface portion of the semiconductor chip and the first through via forming metal posts.
  • Step 2 For forming the second insulating resin layer on the surface of the heat dissipation substrate so as to cover the entire semiconductor chip sealing body metal-bonded to the heat dissipation substrate A step of applying a resin and heating at 300 to 450 ° C. to form a second insulating resin layer (Step 3)
  • the first insulating resin layer and the surface of the second insulating resin layer are subjected to a thinning process to thereby form a first insulating resin layer.
  • a specific example of the manufacturing method of the semiconductor chip sealing body used in step 1 will be described later.
  • the resin for forming the second insulating resin layer used in step 2 the same resins as those described above in the description of the semiconductor device can be used.
  • the thinning process in step 3 include a cutting method and a polishing method, and these may be combined.
  • a method of forming the surface second electrode in the step 4 for example, a metal film is formed on the entire surface by a sputtering vapor deposition method and then patterned, or a metal film is formed in advance so as to have a predetermined pattern. A method is mentioned.
  • the semiconductor device manufacturing method of the present invention is particularly suitable for manufacturing the above-described semiconductor device of the present invention.
  • FIGS. 6 (a) to 6 (d) are steps 1 (step 1a to step 1d), FIG. 6 (e) is step 2 (step 2a), and FIG. 6 (f) is step 3 (step).
  • 3a) and FIG. 6 (g) are diagrams illustrating each of step 4 (step 4a).
  • FIG. 6H is a diagram for explaining a process of joining the lower thermal diffusion conductive substrate 15 and the upper heat dissipation sheet 16 to the state shown in FIG. 6G.
  • the manufacturing method of the semiconductor device of the present invention is not limited to the one described in this step. Further, the semiconductor device shown in FIGS. 1 to 4 can be manufactured by performing only necessary steps from the steps shown in FIG. 6 in accordance with the structure of the target semiconductor device.
  • Step 1a As shown in FIG. 6A, a plating resist 23 is formed on the heat dissipation substrate 14 and patterned to open a through via hole 39a. At this time, it is preferable to provide an opening on the heat dissipation substrate upper electrode 17 connected to the back electrode.
  • Step 1b As shown in FIG. 6B, the through via hole 39a is filled with metal by plating to form a second through via metal post 39b.
  • the plating method is not particularly limited, but it is preferable to use an electrolytic plating method.
  • Step 1c As shown in FIG. 6C, after the end of plating, the plating resist is removed by a conventional method. Instead of the steps 1a to 1c, the same metal post for the second through via may be formed by metal bonding the metal post material to the heat dissipation substrate 14.
  • Step 1d As shown in FIG. 6D, the semiconductor chip sealing body is metal-bonded to the heat dissipation substrate 14 with the back electrode.
  • the order in which the process 1d is implemented is not particularly limited.
  • the semiconductor chip sealing body may be metal-bonded to the heat dissipation substrate before step 1a.
  • Step 2a As shown in FIG. 6E, a second insulating resin layer forming resin is applied so that the semiconductor chip sealing body and the second through via metal post 39b are embedded, and heated at 300 to 450 ° C. Thus, the second insulating resin layer 21 is formed.
  • coating film A1 Before the coating film obtained by applying and drying the second insulating resin layer forming resin (hereinafter sometimes referred to as “coating film A1”) is heated to 300 to 450 ° C., the above coating is applied.
  • the film A1 is compatible with an organic solvent (hereinafter, also referred to as “solvent A1”) used in the second insulating resin layer forming resin (an organic solvent solution of the second insulating resin layer forming resin). It is also preferable to further provide a step of immersing in a certain solvent (hereinafter sometimes referred to as “solvent B1”) at 10 to 40 ° C. for 1 to 60 minutes.
  • the resin for forming the second insulating resin layer is applied, and the resulting coating film has a residual solvent amount of usually 1 to 45% by weight, preferably 3 to 40% by weight, based on the entire coating film. %, More preferably 5 to 35% by weight, after drying at a drying temperature of 50 to 130 ° C. for 1 to 60 minutes to obtain a coating film A1, the obtained coating film A1 is added to 10% in the solvent B1. A step of immersing at ⁇ 40 ° C. for 1 to 60 minutes is further provided. Thereby, the solvent A1 can be efficiently removed from the coating film A1, and as a result, the second insulating resin layer 21 having excellent adhesion with the heat dissipation substrate 14 can be formed.
  • the solvent A1 when the resin for forming the second insulating resin layer is a polyimide precursor, usually N-methylpyrrolidone, N, N-dimethylformamide, N, N-dimethylacetamide, tetramethylurea, hexamethylphosphoric acid Amide solvents such as triamide; or sulfur-containing solvents such as dimethyl sulfoxide and sulfolane are used. Accordingly, the solvent B1 used is preferably a polar solvent other than the amide solvent and the sulfur-containing solvent.
  • water For example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • alcohol solvents such as methanol, ethanol, and propanol
  • ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone
  • a mixed solvent composed of two or more of these solvents for example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • the coating film A1 is heated to 130 to 250 ° C.
  • the second insulating resin layer 21 can be formed by cooling to one end, 0 to 120 ° C., preferably 10 to 100 ° C., more preferably 20 to 100 ° C., and again heating to 250 to 450 ° C. 14 is preferable for forming a second insulating resin layer having excellent adhesion to the resin.
  • the cooling method may be any method that can lower the temperature to a predetermined temperature, and the cooling time can be appropriately determined. For example, it can cool by standing_to_cool.
  • the plating filler is also annealed simultaneously at this curing temperature. Accordingly, the adhesion between the second through via metal post 39b and the surface first electrode, the strength of the second through via, the electrical conductivity of the second through via, the second through via and the first insulating resin layer are improved. The improvement of the adhesion is achieved.
  • Step 3a As shown in FIG. 6 (f), the heat dissipation substrate 14 is fixed to a pedestal (not shown), the resin sealing portion on the surface is cut, and the first through via metal post 39b and the second penetration The upper surface of the via metal post 39b is exposed.
  • the cutting can be performed using a known cutting machine (for example, a surface brainer DFS8920 manufactured by DiSCO).
  • Step 4a As shown in FIG. 6G, a metal film is formed on the cut surface and patterned to form the surface second electrodes 36 and 37.
  • the method for forming the metal film is not particularly limited.
  • a metal film can be formed by sputtering deposition.
  • seat 16 can be joined to the upper and lower surfaces, respectively.
  • the upper heat radiation sheet 16 is bonded to the surface second electrode lead wiring, and the surface second electrode lead wiring is metal-bonded to the surface second electrode.
  • FIG. 7A A semiconductor element 11 having a first surface electrode (not shown) is fabricated on a semiconductor substrate 200.
  • a silicon carbide substrate or a gallium nitride substrate can be used in addition to the silicon substrate.
  • FIG. 7B A plating resist 23 is formed on the semiconductor element 11.
  • the coating film thickness can be determined in consideration of the plating thickness. Usually, the plating thickness is preferably 30 to 60 ⁇ m. Further, instead of forming the plating resist 23, a photosensitive sheet for plating may be used.
  • the plating method is not particularly limited, but it is preferable to use an electrolytic plating method.
  • FIG. 7F First insulating resin layer forming resin is applied so that the first through via metal post 34b is embedded on the entire semiconductor substrate 200, and heated at 300 to 450 ° C. to form the first insulating resin layer. 20 is formed, and the semiconductor element 11 and the metal post 34b are sealed.
  • coating film A2 Before the coating film obtained by applying and drying the first insulating resin layer forming resin (hereinafter sometimes referred to as “coating film A2”) is heated to 300 to 450 ° C., the above coating is applied.
  • the film A2 has an affinity with an organic solvent (hereinafter sometimes referred to as “solvent A2”) used in the first insulating resin layer forming resin (the organic solvent solution of the first insulating resin layer forming resin). It is also preferable to further provide a step of immersing in a solvent (hereinafter sometimes referred to as “solvent B2”) at 10 to 40 ° C. for 1 to 60 minutes.
  • the first insulating resin layer forming resin is applied, and the resulting coating film has a residual solvent amount of usually 1 to 45% by weight, preferably 3 to 40% by weight, based on the entire coating film. %, More preferably 5 to 35% by weight, after drying at a drying temperature of 50 to 130 ° C. for 1 to 60 minutes to obtain a coating film A2, the resulting coating film A2 is added to 10% in solvent B2. Soak for 1 to 60 minutes at ⁇ 40 ° C. This step is provided. Thereby, the organic solvent can be efficiently removed from the coating film A2, and as a result, the first insulating resin layer 21 having excellent adhesion to the semiconductor substrate 200 can be formed.
  • the solvent A2 when the first insulating resin layer forming resin is a polyimide precursor, usually N-methylpyrrolidone, N, N-dimethylformamide, N, N-dimethylacetamide, tetramethylurea, hexamethylphosphoric acid Amide solvents such as triamide; or sulfur-containing solvents such as dimethyl sulfoxide and sulfolane are used. Accordingly, the solvent B2 to be used is preferably a polar solvent other than the amide solvent and the sulfur-containing solvent.
  • water For example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • alcohol solvents such as methanol, ethanol, and propanol
  • ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone
  • a mixed solvent composed of two or more of these solvents for example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • the coating film A2 is heated to 130 to 250 ° C.
  • the first insulating resin layer 20 may be formed by cooling to one end, 0 to 120 ° C., preferably 10 to 100 ° C., more preferably 20 to 100 ° C., and again heating to 250 to 450 ° C. It is preferable when forming the 1st insulating resin layer excellent in adhesiveness.
  • the cooling method may be any method that can lower the temperature to a predetermined temperature, and the cooling time can be appropriately determined. For example, it can cool by standing_to_cool.
  • the plating filler is also annealed simultaneously at this curing temperature. Therefore, the adhesion between the first through via metal post 34b and the surface first electrode, the strength of the first through via, the electrical conductivity of the first through via, the first through via and the first insulating resin layer are improved. The improvement of the adhesion is achieved.
  • the semiconductor substrate 200 side is fixed to a pedestal (not shown) and the surface of the first insulating resin layer 20 is thinned to make the thickness uniform (not shown).
  • This step is for accurately performing the next back surface processing, and is not an essential step. Even when this step is performed, if the semiconductor device of the present invention is manufactured, the upper surface of the first through via metal post 34b is exposed in this step. It is not necessary to expose the upper surface of the via metal post 34b.
  • the thinning method There are no particular restrictions on the thinning method. Examples thereof include a cutting method and a polishing method, and these may be combined. Of these, the cutting method is preferable because of its excellent processing speed.
  • a known cutting machine for example, a surface brainer DFS8920 manufactured by DiSCO
  • DiSCO DiSCO
  • FIG. 7G After the surface treatment of the first insulating resin layer 20 as described above, a metal film is formed on the entire surface as necessary. Next, the metal film surface is fixed, and the back surface of the semiconductor substrate 200 is cut and polished to form a thin plate. Although this step is not an essential step, a thin semiconductor device with excellent conversion efficiency can be obtained by reducing the thickness of the semiconductor substrate to preferably 400 ⁇ m or less, more preferably 30 ⁇ m to 200 ⁇ m.
  • the metal film of the second electrode on the front surface and the back electrode is formed by adjusting the film composition and film thickness so that the residual stress is uniform. By adjusting the residual stress of the double-sided metal foil, the semiconductor substrate 200 does not warp even after the semiconductor substrate 200 is thinned.
  • FIG. 7I Individual semiconductor chips are obtained by dicing. Even if individualized, since the upper limit residual stress is equalized with respect to the semiconductor substrate 200, the flatness of the semiconductor chip is maintained.
  • the semiconductor chip obtained by the above steps is preferably used as a semiconductor chip sealing body for manufacturing the power semiconductor module shown in FIGS.
  • the manufacturing process of the semiconductor chip used in the present invention is not limited to the above.
  • the same first metal post for through via may be formed by metal bonding a metal post material to a silicon substrate.
  • the first insulating resin surface flattened in the step shown in FIG. 7 (f) is not formed with a metal film, but is fixed to a temporarily fixed substrate or the like, thereby suppressing the warpage of the substrate, polishing the back substrate, and back electrode A manufacturing process can also be performed.
  • Photosensitive polyimide can also be used as the first insulating resin used in step 7 (e).
  • the photosensitive polyimide for example, a low thermal expansion photosensitive polyimide described in JP-A No. 2004-285129 can be used.
  • step 7 (e) by using photosensitive polyimide, instead of forming through via metal posts by the method of FIGS. 7 (a) to 7 (c), through via holes are formed and plated and filled. Via metal posts can be formed.
  • photosensitive polyimide is preferable because it can be used for the purpose of opening a dicing line in the sealing step of FIG.
  • a step of metal-joining a heat radiating component selected from an insulating heat radiating sheet having wiring on the electrode, an insulating heat radiating substrate having wiring, and a lead electrode having a heat radiating function May be.
  • Power semiconductor element 62 External lead-out terminal 63 ... Bonding wire 64 ... Radiation base 65 Resin case 66 ... lid 62 ... emitter electrode 63 ... gate electrode 64 ... collector electrodes 100A, 100B, 100C, 100D, 100E ⁇ power semiconductor module 200 ... semiconductor substrate

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Abstract

La présente invention concerne un dispositif à semi-conducteur, où une ou plusieurs puces semi-conductrices, dotées d'une première électrode de surface avant formée sur le côté surface avant d'un substrat semi-conducteur et d'une électrode de surface arrière formée sur le côté surface arrière du substrat semi-conducteur, sont reliées métalliquement à l'aide d'une plaque de dissipation de chaleur au niveau de l'électrode de surface arrière, le dispositif étant caractérisé en ce qu'il comporte une première couche de résine isolante qui scelle la section de surface de la puce semi-conductrice, une seconde couche de résine isolante scellant les sections latérales de la puce semi-conductrice et la surface de la plaque de dissipation de chaleur, et au moins une seconde électrode de surface avant formée sur la première couche de résine isolante et un ou plusieurs trous pénétrants qui pénètrent dans la première couche de résine isolante et connectent la première électrode de surface avant à la seconde électrode de surface avant. L'invention concerne également un procédé de fabrication associé. Cette invention fournit un dispositif à semi-conducteur petit et fin ayant une résistance à la chaleur et une dissipation de la chaleur supérieures, et un procédé de fabrication de dispositif à semi-conducteur permettant de fabriquer efficacement le dispositif à semi-conducteur.
PCT/JP2012/057313 2011-03-31 2012-03-22 Dispositif à semi-conducteur et son procédé de fabrication WO2012133098A1 (fr)

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JP2015005681A (ja) * 2013-06-24 2015-01-08 三菱電機株式会社 半導体装置及びその製造方法
JP2018531516A (ja) * 2015-10-07 2018-10-25 セラムテック ゲゼルシャフト ミット ベシュレンクテル ハフツングＣｅｒａｍＴｅｃ ＧｍｂＨ 二面冷却式回路
US11581234B2 (en) 2019-06-07 2023-02-14 Samsung Electronics Co., Ltd. Semiconductor package with improved heat dissipation
WO2023080090A1 (fr) * 2021-11-05 2023-05-11 ローム株式会社 Boîtier de semi-conducteur

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