WO2012133098A1 - Semiconductor device and manufacturing method for same - Google Patents

Semiconductor device and manufacturing method for same Download PDF

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Publication number
WO2012133098A1
WO2012133098A1 PCT/JP2012/057313 JP2012057313W WO2012133098A1 WO 2012133098 A1 WO2012133098 A1 WO 2012133098A1 JP 2012057313 W JP2012057313 W JP 2012057313W WO 2012133098 A1 WO2012133098 A1 WO 2012133098A1
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Prior art keywords
insulating resin
resin layer
electrode
substrate
semiconductor
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PCT/JP2012/057313
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French (fr)
Japanese (ja)
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田中　明
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日本ゼオン株式会社
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Priority to JP2013507452A priority Critical patent/JPWO2012133098A1/en
Publication of WO2012133098A1 publication Critical patent/WO2012133098A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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    • H01L2924/30—Technical effects
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    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device that is small, thin, and excellent in heat resistance and heat dissipation, and a method for manufacturing the same.
  • a plurality of semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductors), and FWDs (Free Wheel Diodes) are housed in the same package. It is a semiconductor device used for controlling power in various products such as industrial equipment, automobile equipment, and railway equipment. Conventionally, in a power semiconductor module, a package structure using a resin case has been mainly employed (see Patent Document 1).
  • FIG. 8 A schematic diagram showing an example of a conventional power semiconductor module is shown in FIG.
  • a semiconductor element 61 is bonded to one surface of a DBC (Direct Bonded Copper) insulating substrate 60 formed by bonding a copper pattern to the surface of a ceramic substrate by solder (not shown).
  • the semiconductor element 61 and the external lead-out terminal 62 are connected by a bonding wire 63 or a copper pattern (not shown).
  • the other surface of the DBC insulating substrate 60 is joined to the heat dissipation base 64 with a copper pattern (not shown).
  • the DBC insulating substrate 60, the power semiconductor element 61, and the like are housed in a resin case 65, filled with resin or the like (not shown) as needed, and covered with a resin lid 66.
  • Such power semiconductor modules are required to have characteristics such as large current conduction, high heat dissipation characteristics, and heat resistance.
  • the required performance for power semiconductor modules has further increased.
  • high power is required for power semiconductor modules used in hybrid vehicles, solar power generation systems, industrial motor circuit systems, and the like.
  • power semiconductor modules used in products such as automobiles that have limited installation space for components are required to be smaller and thinner.
  • semiconductor chips Measures against heat generated from semiconductor elements (hereinafter sometimes referred to as “semiconductor chips”) are more important than ever to increase the power output, size, and thickness of power semiconductor modules. It is required to further improve the heat resistance and heat dissipation characteristics of the module.
  • the semiconductor substrate that is the material of the semiconductor chip is replaced with a SiC (silicon carbide) substrate or GaN (gallium) that has higher heat resistance and can be operated at a high temperature.
  • a method using a nitride substrate has been attracting attention.
  • the resin material used for the power semiconductor module is preferably excellent in heat resistance.
  • a silicon gel encapsulant that has been widely used in power semiconductor modules in the past has low heat resistance and may be decomposed near 200 ° C. in the presence of oxygen.
  • the high heat-resistant epoxy resin to which the inorganic filler is added is known as a resin having excellent heat resistance
  • the resin melt viscosity becomes high, so that the resin fluidity decreases, voids, There was a risk of disconnection of wiring.
  • Patent Document 2 includes an insulating substrate having a back metal layer above and below a semiconductor chip, and further has a heat dissipation structure such as a heat sink, a heat sink, and a heat pipe on the back surface of each insulating substrate.
  • a power semiconductor module is disclosed.
  • the semiconductor chip can be cooled from above and below.
  • a hard epoxy resin is used as a resin that seals between the two heat sinks, the resin fluidity is lowered, and there is a risk of generating voids or disconnection of wiring. was there.
  • a passivation film may be formed on the surface of these parts with a flexible resin such as a polyimide resin or a polyamideimide resin in order to relieve stress applied to the wiring or the chip.
  • a flexible resin such as a polyimide resin or a polyamideimide resin
  • the thermal expansion coefficient of the resin is large, resulting in a difference in thermal stress between the resin and the surface of the semiconductor chip, peeling of the interface, cracking or deterioration inside the sealed body There was a risk of causing. Further, from the viewpoint of miniaturization of the power semiconductor module, the power semiconductor module described in Patent Document 2 has not been sufficient.
  • thermosetting polyimide resin or polyamideimide resin since the curing temperature of these resins is high, the object is required to have heat resistance in order to form a passivation film on the surface of the component. It was. In addition, there is a problem that residual stress is generated when the resin is cured.
  • JP-A-8-213547 JP 2008-124430 A (US2008 / 0224303A1)
  • a power semiconductor module using a semiconductor chip using a semiconductor substrate having excellent heat resistance and having a double-sided heat dissipation structure has been attracting attention.
  • further studies were necessary.
  • the present invention has been made in view of the above-described circumstances, and is small, thin, excellent in heat resistance and heat dissipation, and a semiconductor device manufacturing method capable of efficiently manufacturing the semiconductor device.
  • the purpose is to provide.
  • the present inventor has one or more of the following: a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate.
  • the semiconductor chip is a semiconductor device in which the back surface electrode is metal-bonded to the heat dissipation substrate, the first insulating resin layer sealing the surface portion of the semiconductor chip, the side surface portion of the semiconductor chip, and the surface of the heat dissipation substrate
  • a semiconductor device having one or two or more first through vias connecting two electrodes has been found to be small and thin and excellent in heat resistance and heat dissipation, and has completed the present invention.
  • the following semiconductor devices (1) to (11) are provided.
  • One or two or more semiconductor chips each including a first surface electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate are a heat dissipation substrate and a metal in the back electrode.
  • a bonded semiconductor device comprising: A first insulating resin layer for sealing the surface portion of the semiconductor chip; A second insulating resin layer for sealing the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate; At least one surface second electrode formed on the first insulating resin layer, and one or two or more that penetrate through the first insulating resin layer and connect the surface first electrode and the surface second electrode A first through via;
  • a semiconductor device comprising: (2) The surface area of the heat dissipation substrate is equal to or greater than the surface area of the semiconductor substrate, and the heat dissipation substrate is metal-bonded to the back electrode so as to cover the entire back surface of the semiconductor substrate.
  • the semiconductor device according to any one of (1) to (3), further including one or more second through vias that penetrate through the second insulating resin layer.
  • a heat dissipation substrate upper electrode connected to the back electrode is provided on the surface of the heat dissipation substrate, and the heat dissipation substrate upper electrode and the surface second electrode are connected by the second through via.
  • the semiconductor device according to (4).
  • the first insulating resin layer is made of an insulating resin forming a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C.
  • the second insulating resin layer is a resin having a thermal expansion coefficient of 2 to 50 ppm / ° C.
  • the semiconductor device according to any one of (1) to (5), which is made of an insulating resin that forms a layer.
  • the first insulating resin layer is made of an insulating resin having a glass transition temperature of 300 ° C. or higher
  • the second insulating resin layer is made of an insulating resin having a glass transition temperature of 240 ° C. or higher.
  • the first insulating resin layer and the second insulating resin layer are made of one or two or more insulating resins selected from the group consisting of a polyimide resin, a polybenzimidazole resin, and a polybenzoxazole resin.
  • the semiconductor device according to any one of (1) to (7), wherein (9) The semiconductor according to any one of (1) to (8), wherein the first through via and / or the second through via are formed by a plating method or a metal bonding method using a metal post material. apparatus.
  • Step 1) a semiconductor chip comprising a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate; One or more first through via forming metal posts formed on the first surface electrode, and a first insulating resin layer for sealing the surface portion of the semiconductor chip and the first through via forming metal post.
  • step 2 A step of metal bonding to the heat dissipation substrate with the back electrode (step 2)
  • a second insulating resin layer forming resin is applied to the surface of the heat dissipation substrate so as to cover the entire semiconductor chip sealing body metal-bonded to the heat dissipation substrate.
  • Step 3 Thinning treatment is performed on the surfaces of the first insulating resin layer and the second insulating resin layer.
  • Step 4 Step of flattening the insulating resin layer and exposing the upper surface of the through via forming metal post (Step 4) Step of forming a surface second electrode on at least the surface of the first insulating resin layer (13)
  • the thickness of the semiconductor substrate is The method for manufacturing a semiconductor device according to (12), which is 400 ⁇ m or less.
  • step 4 a heat dissipating component selected from an insulating heat dissipating sheet having wiring, an insulating heat dissipating substrate having wiring, and a lead electrode having a heat dissipating function is applied to the surface second electrode.
  • Step a) Forming a plating resist film on the surface of the heat dissipation substrate and providing an opening in the plating resist film so that a predetermined portion of the heat dissipation substrate is exposed
  • Step b) Filling the opening with a metal, Step of forming second through via forming metal post
  • step c) Step of removing plating resist film
  • the second through via forming metal post is placed at a predetermined position on the surface of the heat dissipation substrate.
  • the semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.1 to 1.5, 1.7 and 1.8 in this order: (12) to (16 ) A method for manufacturing a semiconductor device according to any one of the above.
  • Step 1.1 Step of depositing a plating resist film on the surface of the semiconductor substrate on which the first surface electrode is formed
  • Step 1.2 A plating resist film so that a predetermined portion of the first surface electrode is exposed.
  • Step 1.3 Step of filling the opening with metal and forming a metal post for forming a first through via
  • Step 1.4 Step of removing the plating resist film (Step 1.
  • a first insulating resin layer forming resin is applied to the surface of the semiconductor substrate so as to cover the first through via forming metal post, and heated at 300 to 450 ° C. to form a first insulating resin layer.
  • Simultaneously annealing the metal posts step 1.7) forming a back electrode on the back surface of the semiconductor substrate (step 1.8) separating the semiconductor substrate by dicing (18)
  • step 1.5 Prior to 1.7), (step 1.6) by the rear surface of the semiconductor substrate of the thinning process, a method of manufacturing a semiconductor device according to a step of the thickness of the semiconductor substrate to 400 ⁇ m or less (17).
  • the semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.9, 1.10, 1.12 and 1.13 in this order (12) to (15 ) A method for manufacturing a semiconductor device according to any one of the above.
  • Step 1.9 Forming a first through via forming metal post by a metal bonding method on the surface first electrode of the semiconductor substrate on which the surface first electrode is formed
  • Step 1.10 A step of applying a first insulating resin layer forming resin to the surface of the semiconductor substrate so as to cover the through via forming metal post and heating at 300 to 450 ° C.
  • Step 1.12) Step of forming a back electrode on the back surface of the semiconductor substrate (Step 1.13) Step of dicing the semiconductor substrate by dicing (20) After (Step 1.10), (Step 1.12) Before (Step 1.11), the method of manufacturing a semiconductor device according to (19), including a step of reducing the thickness of the semiconductor substrate to 400 ⁇ m or less by thinning processing of the back surface of the semiconductor substrate.
  • the semiconductor device of the present invention is small and thin, and has excellent heat resistance and heat dissipation. According to the manufacturing method of the present invention, a semiconductor device that is small, thin, and excellent in heat resistance and heat dissipation can be efficiently manufactured.
  • the manufacturing method of the present invention is useful as a method for manufacturing a semiconductor device of the present invention.
  • a semiconductor device includes one or more semiconductor chips each including a first front electrode formed on a front surface side of a semiconductor substrate and a back electrode formed on a back surface side of the semiconductor substrate.
  • 2 insulating resin layers, at least a surface second electrode formed on the first insulating resin layer, and the first insulating resin layer penetrating and connecting the surface first electrode and the surface second electrode And having one or more first through vias.
  • metal bonding refers to heat-resistant metal bonding in which melt fracture does not occur at high temperatures (usually 300 ° C. or higher, preferably 400 ° C. or higher).
  • Metal bonding methods include direct bonding using nano metal particles such as nano gold particles, nano silver particles, and nano copper particles, bonding using high heat-resistant solder having a heat resistant temperature of 300 ° C. or higher, and bonding metals by high frequency bonding. And the like.
  • a power semiconductor module 100A shown in FIG. 1 includes a semiconductor substrate 200, a front surface first electrode 35 formed on the front surface side of the semiconductor substrate 200, and a back surface electrode 32 on the back surface side of the semiconductor substrate 200.
  • the chip has a structure in which the chip is metal-bonded to the heat dissipation substrate 14 with the back electrode 32.
  • the surface portion of the semiconductor chip is sealed with a first insulating resin layer 20, and the side surface portion of the semiconductor chip and the heat dissipation substrate 14 are sealed with a second insulating resin layer 21.
  • semiconductor chips include power semiconductor chips such as IGBTs, MOSFETs, and FWDs.
  • power semiconductor chips such as IGBTs, MOSFETs, and FWDs.
  • the back surface electrode 32 of the semiconductor chip for example, when the semiconductor chip is an IGBT, an IGBT collector electrode or the like can be cited.
  • the front surface first electrode 35 an IGBT emitter electrode or the like can be cited.
  • Examples of the semiconductor substrate 200 include a Si (silicon) substrate, a SiC (silicon carbide) substrate, and a GaN (gallium nitride) substrate. From the viewpoint of heat resistance, a SiC (silicon carbide) substrate and a GaN (gallium nitride) substrate. ) A substrate is preferred.
  • the thickness of the semiconductor substrate 200 is usually 600 ⁇ m or less, preferably 400 ⁇ m or less, and more preferably 30 ⁇ m to 400 ⁇ m. When the thickness is 400 ⁇ m or less, a thin semiconductor device having excellent conversion efficiency can be obtained.
  • the surface second electrode 36 is formed on the surface of the first insulating resin layer 20 and is connected to the surface first electrode 35 through the first through via 34.
  • the surface second electrode 36 also has a heat dissipation function, and its area can be expanded to a size equivalent to the area of the heat dissipation substrate 14 at the maximum. Therefore, the semiconductor device of the present invention has a high degree of design freedom. As described above, by adopting a structure using the surface second electrode 36 and the first through via 34, a reduction in thickness is achieved, and a double-sided heat dissipation structure including the heat dissipation substrate 14 and the surface second electrode 36 is provided. Thus, high heat dissipation is achieved.
  • heat dissipation substrate 14 examples include copper-clad substrates such as a DBC (Direct Bonded Copper) substrate and an AMC (Active Metal Brazed Copper) substrate.
  • a power semiconductor module 100A shown in FIG. 1 is an example in which a DBC substrate 14 having a structure in which copper patterns 14a are bonded to both surfaces of a ceramic substrate 14b is used as a heat dissipation substrate.
  • the surface area of the heat dissipation substrate 14 is preferably equal to or greater than the surface area of the half-layer substrate 200 constituting the semiconductor chip from the viewpoint of heat dissipation.
  • the heat dissipation substrate 14 is preferably metal-bonded by the back electrode 32 of the semiconductor chip so as to cover the entire back surface of the semiconductor substrate 200.
  • the total installation sectional area of the first through vias 34 is preferably 20% or more, more preferably 20 to 50%, and more preferably 25 to 35% with respect to the sectional area of the surface first electrode 35. Further preferred. Sufficient conductivity can be obtained when the total cross-sectional area of the first through vias 34 is 20% or more with respect to the cross-sectional area of the surface first electrode 35. In addition, heat generated on the surface of the first surface electrode can be efficiently transferred to the surface of the second surface of the surface, thereby suppressing deterioration in conversion efficiency due to temperature rise on the device surface and deterioration of the semiconductor chip due to generation of thermal stress. Can do.
  • the total installation cross-sectional area of the first through via 34 is 50% or less, so that the cost for forming the through via can be suppressed.
  • the first through via 34 can be formed by, for example, a plating method or a metal bonding method using a metal post material.
  • the surface portion of the semiconductor chip is sealed with the first insulating resin layer 20, and the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate 14 are sealed with the second insulating resin layer 21.
  • the elastic modulus of the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is preferably 2 to 8 GPa. As will be described later, a thinning process is performed on these insulating resin layers. At this time, if the elastic modulus exceeds 8 GPa, the resin becomes hard and brittle, and there is a possibility of causing surface roughness during cutting. On the other hand, if the elastic modulus is less than 2 GPa, the resin tends to be stretched during cutting, and the processing speed may be reduced, and it may be difficult to perform beautiful processing.
  • the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is an insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C. in the former, and in the latter.
  • An insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 50 ppm / ° C. is preferable.
  • the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is an insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C.
  • the thermal expansion coefficient of the first insulating resin layer 20 is a value close to the thermal expansion coefficient of the semiconductor substrate 200 constituting the semiconductor chip. It is preferable that For example, when a SiC substrate is used as the semiconductor substrate, the coefficient of thermal expansion of the first insulating resin layer 20 is preferably 2 to 8 ppm / ° C, and more preferably 4 to 6 ppm / ° C.
  • the coefficient of thermal expansion of the first insulating resin layer 20 is preferably 2 to 8 ppm / ° C, and more preferably 4 to 6 ppm / ° C.
  • the thermal expansion coefficient of the second insulating resin layer 21 is preferably a value close to the thermal expansion coefficient of the heat dissipation substrate 14.
  • the thermal expansion coefficient of the main skeleton ceramic portion of the heat dissipation substrate 14 is usually about 8 ppm / ° C.
  • the second insulating resin layer 21 has a thermal expansion rate of 8 to 17 ppm / ° C.
  • the resin layer is made of an insulating resin.
  • the thermal expansion coefficient of the 2nd insulating resin layer 21 when joining an upper thermal radiation sheet and the lead electrode which has a thermal radiation function to the 2nd insulating resin layer 21, it is preferable to adjust the thermal expansion coefficient of the 2nd insulating resin layer 21 according to the thermal expansion coefficient of these materials. . More specifically, when the material of the heat dissipation mechanism is copper or aluminum, it is preferable to match the thermal expansion coefficient of the second insulating resin layer 21 to around 16.3 ppm / ° C. and around 21 ppm / ° C., respectively.
  • the first insulating resin layer 20 and the second insulating resin layer 21 may be formed of the same resin. By doing in this way, resin interface peeling can be suppressed significantly.
  • Examples of the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 include polyimide resin, polybenzimidazole resin, and polybenzoxazole resin. These resins can be used alone or in combination of two or more. Among these, a polyimide resin is preferable.
  • a polyamic acid is synthesized by polycondensation of a rigid structure aromatic tetracarboxylic acid or acid anhydride thereof and a rigid structure aromatic diamine, and then a thermal imide
  • the method include conversion to a polyimide resin by a method such as chemical conversion or chemical imidization.
  • Control of the coefficient of thermal expansion can be achieved by copolymerizing an aromatic tetracarboxylic acid having a flexible structure or an acid anhydride thereof and an aromatic diamine having a flexible structure as necessary.
  • the “rigid structure” means that a rod-like rigid straight chain that has low mobility and cannot be bent by itself is formed, and the flexible structure means that it is not the rigid structure.
  • rigid structure aromatic tetracarboxylic acid examples include pyromellitic dianhydride, 3,3 ′, 4,4′-benzophenone tetracarboxylic dianhydride, benzene-1,2,3,4-tetra Carboxylic dianhydride, 2,2 ′, 3,3′-benzophenone tetracarboxylic dianhydride, 2,3,3 ′, 4′-benzophenone tetracarboxylic dianhydride, naphthalene-2,3,6 7-tetracarboxylic dianhydride, naphthalene-1,2,5,6-tetracarboxylic dianhydride, naphthalene-1,2,4,5-tetracarboxylic dianhydride, naphthalene-1,2,5 , 8-tetracarboxylic dianhydride, naphthalene-1,2,6,7-tetracarboxylic dianhydride, 4,8-dimethyl-1
  • An alicyclic acid dianhydride pyrazine-2,3,5,6-tetracarboxylic dianhydride, pyrrolidine-2,3,4,5-tetracarboxylic dianhydride, thiophene-2,3,4 , 5-tetracarboxylic dianhydrides and the like, and heterocyclic derivative dianhydrides such as tetracarboxylic acids corresponding thereto.
  • aromatic tetracarboxylic acid etc. It is preferable to use at least one selected from the group consisting of acid, pyromellitic dianhydride (PMDA), biphenyltetracarboxylic acid, and biphenyltetracarboxylic dianhydride (s-BPDA).
  • PMDA pyromellitic dianhydride
  • s-BPDA biphenyltetracarboxylic dianhydride
  • rigid aromatic diamines examples include 4,4′-diaminobenzanilide, 4,4′-diamino-2,2′-ditrifluoromethylbiphenyl, and 2,2′-di (p-aminophenyl)- 5,5'-bisbenzoxazole, 2,2'-di (p-aminophenyl) -6,6'-bisbenzoxazole, 2,2'-di (p-aminophenyl) -5,5'-bis Benzimidazole, 3,6- (4-aminophenyl) pyridazine, 4,4'-diaminobenzanilide, p-phenylenediamine (PPDA), 4,4'-diaminobiphenyl, m-phenylenediamine, 1-isopropyl-2 , 4-phenylenediamine, p-phenylenediamine, 4,4′-diaminodiphenyl sulfide, 3,3
  • Examples of the flexible structure aromatic tetracarboxylic acid or acid anhydride used for controlling the thermal expansion coefficient include 3,3 ′, 4,4′-benzophenone tetracarboxylic dianhydride (BTDA).
  • BTDA 4,4′-benzophenone tetracarboxylic dianhydride
  • An aromatic tetracarboxylic acid having a structure in which two or more aromatic rings are bonded by a carbonyl group (> C ⁇ O) or an oxygen atom (—O—) can be used.
  • Examples of the flexible structure diamine include a diamine having a structure in which the bonding position of the substituent bonded to the main chain heterocycle such as 2,5-bis (p-aminobenzoyl) thiophene) is an ortho position or a meta position; Examples thereof include diamines having an ether structure in the main chain such as oxydianiline; diamines having a siloxane structure in the main chain such as 1,3-diaminopropyl-1,1,3,3-tetramethyldisiloxane.
  • flexible structure diamines include 4,4′-diaminodiphenylpropane, 3,3′-diaminodiphenylpropane, 4,4′-diaminodiphenylethane, 3,3′-diaminodiphenylethane, 4,4 Examples include '-diaminodiphenylmethane and 3,3'-diaminodiphenylmethane.
  • the insulating resin constituting the first insulating resin layer 20 has a glass transition temperature of 300 ° C. or higher
  • the insulating resin constituting the second insulating resin layer 21 has a glass transition temperature of 240 ° C. or higher. It is preferable. By using such an insulating resin, a semiconductor device having excellent heat resistance can be obtained.
  • the semiconductor chip, the semiconductor substrate, the first insulating resin layer, the second insulating resin layer, and the like described in the power semiconductor 100A are the same for the power semiconductor modules 100B, 100C, 100D, and 100E described later.
  • FIG. 2 shows an example of a power semiconductor module in which two or more semiconductor chips are mounted in the semiconductor device of the present invention.
  • 2A is a schematic view of the power semiconductor module 100B viewed from above
  • FIG. 2B is a schematic view of the XY cross section of FIG. 2A viewed from the side.
  • a power semiconductor module 100B shown in FIG. 2 has a structure in which three power semiconductor chips are metal-bonded to a wiring metal portion (not shown) of the heat dissipation board 14 at each back electrode 32 on the heat dissipation board 14. Yes. Further, the power semiconductor chip has a semiconductor substrate 200, a front surface first electrode 35, and a back surface electrode 32, which are sealed with a first insulating resin layer, and the front surface first electrode 35 has a first insulating resin layer. It is connected to the surface second electrode 36 through a first through via 34 formed therein.
  • the thickness up to the upper part of the second insulating resin layer 21 in which the three elements are sealed with respect to the surface of the heat dissipation substrate 14 is uniform.
  • the surface first electrode and the surface second electrode become parallel.
  • a cutting method is excellent as will be described later.
  • FIG. 3 A schematic diagram showing an example of a power semiconductor module having a heat dissipation mechanism such as a lower thermal diffusion conductive substrate is shown in FIG.
  • the power semiconductor module 100 ⁇ / b> C shown in FIG. 3 has a structure in which the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15. Therefore, the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat dissipation substrate 14.
  • FIG. 4 shows a schematic diagram of an example of a power semiconductor module having a heat dissipation mechanism such as a lower heat diffusion conductive substrate and an upper heat dissipation sheet.
  • the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15, and is bonded to the surface second electrode lead-out wiring 38.
  • the surface second electrode lead-out wiring 38 and the surface second electrode are connected to each other. It has a metal bonded structure.
  • the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat dissipation substrate 14.
  • the heat generated in the semiconductor chip is efficiently radiated from the upper part of the power semiconductor module 100D.
  • FIG. 5 shows a schematic diagram of another example of a power semiconductor module having a heat dissipation mechanism such as a lower heat diffusion conductive substrate and an upper heat dissipation sheet.
  • the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15, and the upper heat dissipation sheet 16 is bonded to the surface second electrode lead-out wiring 38;
  • the second electrode lead-out wiring 38 is metal-bonded to the front surface second electrode, and
  • the heat dissipation substrate upper electrode 17 connected to the back electrode 32 is provided on the surface of the heat dissipation substrate 14.
  • the surface second electrode 37 is connected by a second through via 39 and has a structure in which the lead electrode 18 having a heat dissipation function is metal-bonded to the surface second electrode 37.
  • the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat radiating substrate 14, is also efficiently radiated from the upper part, and is radiated using the second through via 39. Since the mechanism is provided, the heat generated from the semiconductor chip can be radiated more efficiently. Further, the wiring can be integrated, the semiconductor device can be made thinner and smaller, and the attachment of the upper heat dissipation sheet 16 is also advantageous.
  • an upper heat dissipation board may be used instead of the heat dissipation sheet 16, and a heat dissipation member having a heat dissipation fin can be directly connected.
  • the method is not limited to the method of consolidating the wirings on the upper heat dissipation substrate 16.
  • the wirings can be consolidated on the lower thermal diffusion conductive substrate 15 side.
  • the semiconductor device of the present invention is not limited to the semiconductor device shown in FIGS. 1 to 5, and the type of the semiconductor substrate, the first surface electrode, the back surface electrode, the insulating resin layer, the second surface surface are within the scope not departing from the gist of the present invention.
  • the shape and arrangement of electrodes and through vias can be freely changed.
  • the entire semiconductor chip is sealed with a first insulating resin and a second insulating resin that are excellent in insulation and heat resistance. Therefore, in the semiconductor device of the present invention, the semiconductor chip is protected from moisture and the like, and element deterioration is unlikely to occur. Further, the semiconductor device of the present invention can control the thermal expansion rate of the semiconductor substrate, the heat dissipation substrate, and the sealing resin. Therefore, the interface stress due to the thermal stress difference at the sealing interface can be reduced during the manufacture and use of the semiconductor device, and the semiconductor device manufacturing yield and product reliability are greatly improved.
  • Step 1 a semiconductor chip comprising a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate, and 1 or formed on the front surface first electrode
  • One or more semiconductor chip seals having two or more first through via forming metal posts and a first insulating resin layer for sealing the surface portion of the semiconductor chip and the first through via forming metal posts.
  • Step 2 For forming the second insulating resin layer on the surface of the heat dissipation substrate so as to cover the entire semiconductor chip sealing body metal-bonded to the heat dissipation substrate A step of applying a resin and heating at 300 to 450 ° C. to form a second insulating resin layer (Step 3)
  • the first insulating resin layer and the surface of the second insulating resin layer are subjected to a thinning process to thereby form a first insulating resin layer.
  • a specific example of the manufacturing method of the semiconductor chip sealing body used in step 1 will be described later.
  • the resin for forming the second insulating resin layer used in step 2 the same resins as those described above in the description of the semiconductor device can be used.
  • the thinning process in step 3 include a cutting method and a polishing method, and these may be combined.
  • a method of forming the surface second electrode in the step 4 for example, a metal film is formed on the entire surface by a sputtering vapor deposition method and then patterned, or a metal film is formed in advance so as to have a predetermined pattern. A method is mentioned.
  • the semiconductor device manufacturing method of the present invention is particularly suitable for manufacturing the above-described semiconductor device of the present invention.
  • FIGS. 6 (a) to 6 (d) are steps 1 (step 1a to step 1d), FIG. 6 (e) is step 2 (step 2a), and FIG. 6 (f) is step 3 (step).
  • 3a) and FIG. 6 (g) are diagrams illustrating each of step 4 (step 4a).
  • FIG. 6H is a diagram for explaining a process of joining the lower thermal diffusion conductive substrate 15 and the upper heat dissipation sheet 16 to the state shown in FIG. 6G.
  • the manufacturing method of the semiconductor device of the present invention is not limited to the one described in this step. Further, the semiconductor device shown in FIGS. 1 to 4 can be manufactured by performing only necessary steps from the steps shown in FIG. 6 in accordance with the structure of the target semiconductor device.
  • Step 1a As shown in FIG. 6A, a plating resist 23 is formed on the heat dissipation substrate 14 and patterned to open a through via hole 39a. At this time, it is preferable to provide an opening on the heat dissipation substrate upper electrode 17 connected to the back electrode.
  • Step 1b As shown in FIG. 6B, the through via hole 39a is filled with metal by plating to form a second through via metal post 39b.
  • the plating method is not particularly limited, but it is preferable to use an electrolytic plating method.
  • Step 1c As shown in FIG. 6C, after the end of plating, the plating resist is removed by a conventional method. Instead of the steps 1a to 1c, the same metal post for the second through via may be formed by metal bonding the metal post material to the heat dissipation substrate 14.
  • Step 1d As shown in FIG. 6D, the semiconductor chip sealing body is metal-bonded to the heat dissipation substrate 14 with the back electrode.
  • the order in which the process 1d is implemented is not particularly limited.
  • the semiconductor chip sealing body may be metal-bonded to the heat dissipation substrate before step 1a.
  • Step 2a As shown in FIG. 6E, a second insulating resin layer forming resin is applied so that the semiconductor chip sealing body and the second through via metal post 39b are embedded, and heated at 300 to 450 ° C. Thus, the second insulating resin layer 21 is formed.
  • coating film A1 Before the coating film obtained by applying and drying the second insulating resin layer forming resin (hereinafter sometimes referred to as “coating film A1”) is heated to 300 to 450 ° C., the above coating is applied.
  • the film A1 is compatible with an organic solvent (hereinafter, also referred to as “solvent A1”) used in the second insulating resin layer forming resin (an organic solvent solution of the second insulating resin layer forming resin). It is also preferable to further provide a step of immersing in a certain solvent (hereinafter sometimes referred to as “solvent B1”) at 10 to 40 ° C. for 1 to 60 minutes.
  • the resin for forming the second insulating resin layer is applied, and the resulting coating film has a residual solvent amount of usually 1 to 45% by weight, preferably 3 to 40% by weight, based on the entire coating film. %, More preferably 5 to 35% by weight, after drying at a drying temperature of 50 to 130 ° C. for 1 to 60 minutes to obtain a coating film A1, the obtained coating film A1 is added to 10% in the solvent B1. A step of immersing at ⁇ 40 ° C. for 1 to 60 minutes is further provided. Thereby, the solvent A1 can be efficiently removed from the coating film A1, and as a result, the second insulating resin layer 21 having excellent adhesion with the heat dissipation substrate 14 can be formed.
  • the solvent A1 when the resin for forming the second insulating resin layer is a polyimide precursor, usually N-methylpyrrolidone, N, N-dimethylformamide, N, N-dimethylacetamide, tetramethylurea, hexamethylphosphoric acid Amide solvents such as triamide; or sulfur-containing solvents such as dimethyl sulfoxide and sulfolane are used. Accordingly, the solvent B1 used is preferably a polar solvent other than the amide solvent and the sulfur-containing solvent.
  • water For example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • alcohol solvents such as methanol, ethanol, and propanol
  • ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone
  • a mixed solvent composed of two or more of these solvents for example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • the coating film A1 is heated to 130 to 250 ° C.
  • the second insulating resin layer 21 can be formed by cooling to one end, 0 to 120 ° C., preferably 10 to 100 ° C., more preferably 20 to 100 ° C., and again heating to 250 to 450 ° C. 14 is preferable for forming a second insulating resin layer having excellent adhesion to the resin.
  • the cooling method may be any method that can lower the temperature to a predetermined temperature, and the cooling time can be appropriately determined. For example, it can cool by standing_to_cool.
  • the plating filler is also annealed simultaneously at this curing temperature. Accordingly, the adhesion between the second through via metal post 39b and the surface first electrode, the strength of the second through via, the electrical conductivity of the second through via, the second through via and the first insulating resin layer are improved. The improvement of the adhesion is achieved.
  • Step 3a As shown in FIG. 6 (f), the heat dissipation substrate 14 is fixed to a pedestal (not shown), the resin sealing portion on the surface is cut, and the first through via metal post 39b and the second penetration The upper surface of the via metal post 39b is exposed.
  • the cutting can be performed using a known cutting machine (for example, a surface brainer DFS8920 manufactured by DiSCO).
  • Step 4a As shown in FIG. 6G, a metal film is formed on the cut surface and patterned to form the surface second electrodes 36 and 37.
  • the method for forming the metal film is not particularly limited.
  • a metal film can be formed by sputtering deposition.
  • seat 16 can be joined to the upper and lower surfaces, respectively.
  • the upper heat radiation sheet 16 is bonded to the surface second electrode lead wiring, and the surface second electrode lead wiring is metal-bonded to the surface second electrode.
  • FIG. 7A A semiconductor element 11 having a first surface electrode (not shown) is fabricated on a semiconductor substrate 200.
  • a silicon carbide substrate or a gallium nitride substrate can be used in addition to the silicon substrate.
  • FIG. 7B A plating resist 23 is formed on the semiconductor element 11.
  • the coating film thickness can be determined in consideration of the plating thickness. Usually, the plating thickness is preferably 30 to 60 ⁇ m. Further, instead of forming the plating resist 23, a photosensitive sheet for plating may be used.
  • the plating method is not particularly limited, but it is preferable to use an electrolytic plating method.
  • FIG. 7F First insulating resin layer forming resin is applied so that the first through via metal post 34b is embedded on the entire semiconductor substrate 200, and heated at 300 to 450 ° C. to form the first insulating resin layer. 20 is formed, and the semiconductor element 11 and the metal post 34b are sealed.
  • coating film A2 Before the coating film obtained by applying and drying the first insulating resin layer forming resin (hereinafter sometimes referred to as “coating film A2”) is heated to 300 to 450 ° C., the above coating is applied.
  • the film A2 has an affinity with an organic solvent (hereinafter sometimes referred to as “solvent A2”) used in the first insulating resin layer forming resin (the organic solvent solution of the first insulating resin layer forming resin). It is also preferable to further provide a step of immersing in a solvent (hereinafter sometimes referred to as “solvent B2”) at 10 to 40 ° C. for 1 to 60 minutes.
  • the first insulating resin layer forming resin is applied, and the resulting coating film has a residual solvent amount of usually 1 to 45% by weight, preferably 3 to 40% by weight, based on the entire coating film. %, More preferably 5 to 35% by weight, after drying at a drying temperature of 50 to 130 ° C. for 1 to 60 minutes to obtain a coating film A2, the resulting coating film A2 is added to 10% in solvent B2. Soak for 1 to 60 minutes at ⁇ 40 ° C. This step is provided. Thereby, the organic solvent can be efficiently removed from the coating film A2, and as a result, the first insulating resin layer 21 having excellent adhesion to the semiconductor substrate 200 can be formed.
  • the solvent A2 when the first insulating resin layer forming resin is a polyimide precursor, usually N-methylpyrrolidone, N, N-dimethylformamide, N, N-dimethylacetamide, tetramethylurea, hexamethylphosphoric acid Amide solvents such as triamide; or sulfur-containing solvents such as dimethyl sulfoxide and sulfolane are used. Accordingly, the solvent B2 to be used is preferably a polar solvent other than the amide solvent and the sulfur-containing solvent.
  • water For example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • alcohol solvents such as methanol, ethanol, and propanol
  • ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone
  • a mixed solvent composed of two or more of these solvents for example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
  • the coating film A2 is heated to 130 to 250 ° C.
  • the first insulating resin layer 20 may be formed by cooling to one end, 0 to 120 ° C., preferably 10 to 100 ° C., more preferably 20 to 100 ° C., and again heating to 250 to 450 ° C. It is preferable when forming the 1st insulating resin layer excellent in adhesiveness.
  • the cooling method may be any method that can lower the temperature to a predetermined temperature, and the cooling time can be appropriately determined. For example, it can cool by standing_to_cool.
  • the plating filler is also annealed simultaneously at this curing temperature. Therefore, the adhesion between the first through via metal post 34b and the surface first electrode, the strength of the first through via, the electrical conductivity of the first through via, the first through via and the first insulating resin layer are improved. The improvement of the adhesion is achieved.
  • the semiconductor substrate 200 side is fixed to a pedestal (not shown) and the surface of the first insulating resin layer 20 is thinned to make the thickness uniform (not shown).
  • This step is for accurately performing the next back surface processing, and is not an essential step. Even when this step is performed, if the semiconductor device of the present invention is manufactured, the upper surface of the first through via metal post 34b is exposed in this step. It is not necessary to expose the upper surface of the via metal post 34b.
  • the thinning method There are no particular restrictions on the thinning method. Examples thereof include a cutting method and a polishing method, and these may be combined. Of these, the cutting method is preferable because of its excellent processing speed.
  • a known cutting machine for example, a surface brainer DFS8920 manufactured by DiSCO
  • DiSCO DiSCO
  • FIG. 7G After the surface treatment of the first insulating resin layer 20 as described above, a metal film is formed on the entire surface as necessary. Next, the metal film surface is fixed, and the back surface of the semiconductor substrate 200 is cut and polished to form a thin plate. Although this step is not an essential step, a thin semiconductor device with excellent conversion efficiency can be obtained by reducing the thickness of the semiconductor substrate to preferably 400 ⁇ m or less, more preferably 30 ⁇ m to 200 ⁇ m.
  • the metal film of the second electrode on the front surface and the back electrode is formed by adjusting the film composition and film thickness so that the residual stress is uniform. By adjusting the residual stress of the double-sided metal foil, the semiconductor substrate 200 does not warp even after the semiconductor substrate 200 is thinned.
  • FIG. 7I Individual semiconductor chips are obtained by dicing. Even if individualized, since the upper limit residual stress is equalized with respect to the semiconductor substrate 200, the flatness of the semiconductor chip is maintained.
  • the semiconductor chip obtained by the above steps is preferably used as a semiconductor chip sealing body for manufacturing the power semiconductor module shown in FIGS.
  • the manufacturing process of the semiconductor chip used in the present invention is not limited to the above.
  • the same first metal post for through via may be formed by metal bonding a metal post material to a silicon substrate.
  • the first insulating resin surface flattened in the step shown in FIG. 7 (f) is not formed with a metal film, but is fixed to a temporarily fixed substrate or the like, thereby suppressing the warpage of the substrate, polishing the back substrate, and back electrode A manufacturing process can also be performed.
  • Photosensitive polyimide can also be used as the first insulating resin used in step 7 (e).
  • the photosensitive polyimide for example, a low thermal expansion photosensitive polyimide described in JP-A No. 2004-285129 can be used.
  • step 7 (e) by using photosensitive polyimide, instead of forming through via metal posts by the method of FIGS. 7 (a) to 7 (c), through via holes are formed and plated and filled. Via metal posts can be formed.
  • photosensitive polyimide is preferable because it can be used for the purpose of opening a dicing line in the sealing step of FIG.
  • a step of metal-joining a heat radiating component selected from an insulating heat radiating sheet having wiring on the electrode, an insulating heat radiating substrate having wiring, and a lead electrode having a heat radiating function May be.
  • Power semiconductor element 62 External lead-out terminal 63 ... Bonding wire 64 ... Radiation base 65 Resin case 66 ... lid 62 ... emitter electrode 63 ... gate electrode 64 ... collector electrodes 100A, 100B, 100C, 100D, 100E ⁇ power semiconductor module 200 ... semiconductor substrate

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Abstract

The present invention provides a semiconductor device, wherein one or more semiconductor chips, provided with a first front surface electrode formed on the front surface side of a semiconductor substrate and a rear surface electrode formed on the rear surface side of the semiconductor substrate, are metallically joined with a heat dissipating board at the rear surface electrode, characterized by having a first insulating resin layer which seals the surface section of the semiconductor chip, a second insulating resin layer sealing the side sections of the semiconductor chip and the surface of the heat dissipating board, and at least a second front surface electrode formed on the first insulating resin layer and one or more first penetration vias which penetrate in the first insulating resin layer and connect the first front surface electrode with the second front surface electrode, and a manufacturing method therefor. With this invention, provided are a small and thin semiconductor device superior in heat resistance and heat dissipation, and a semiconductor device manufacturing method capable of efficiently manufacturing the semiconductor device.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、小型、薄型で、耐熱性及び放熱性に優れる半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device that is small, thin, and excellent in heat resistance and heat dissipation, and a method for manufacturing the same.
　ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、ＦＷＤ（Ｆｒｅｅ　Ｗｈｅｅｌ　Ｄｉｏｄｅ）等の半導体素子の複数個を同一のパッケージに収納してなるパワー半導体モジュールは、家電製品、産業用機器、自動車用機器、電鉄用機器等の種々の製品において電力を制御するために用いられる半導体装置である。
　従来、パワー半導体モジュールにおいては、樹脂ケースを用いるパッケージ構造が主に採用されていた（特許文献１参照）。 A plurality of semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductors), and FWDs (Free Wheel Diodes) are housed in the same package. It is a semiconductor device used for controlling power in various products such as industrial equipment, automobile equipment, and railway equipment.
Conventionally, in a power semiconductor module, a package structure using a resin case has been mainly employed (see Patent Document 1).
　従来のパワー半導体モジュールの一例を示す模式図を図８に示す。
　図８において、セラミックス基板の表面に銅パターンを接合してなるＤＢＣ（Ｄｉｒｅｃｔ　Ｂｏｎｄｅｄ　Ｃｏｐｐｅｒ）絶縁基板６０の一方の面上に、半導体素子６１がハンダ（図示を省略）で接合されている。半導体素子６１と外部導出端子６２は、ボンディングワイヤ６３又は銅パターン（図示を省略）で接続されている。ＤＢＣ絶縁基板６０のもう一方の面は、銅パターン（図示を省略）で放熱ベース６４に接合されている。ＤＢＣ絶縁基板６０やパワー半導体素子６１などは、樹脂ケース６５に収納され、必要に応じて内部に樹脂等（図示を省略）が充填され、樹脂製の蓋６６で覆われる。 A schematic diagram showing an example of a conventional power semiconductor module is shown in FIG.
In FIG. 8, a semiconductor element 61 is bonded to one surface of a DBC (Direct Bonded Copper) insulating substrate 60 formed by bonding a copper pattern to the surface of a ceramic substrate by solder (not shown). The semiconductor element 61 and the external lead-out terminal 62 are connected by a bonding wire 63 or a copper pattern (not shown). The other surface of the DBC insulating substrate 60 is joined to the heat dissipation base 64 with a copper pattern (not shown). The DBC insulating substrate 60, the power semiconductor element 61, and the like are housed in a resin case 65, filled with resin or the like (not shown) as needed, and covered with a resin lid 66.
　このようなパワー半導体モジュールには、大電流通電性、高放熱特性、耐熱性等の特性が要求される。また、近年においては、パワー半導体モジュールに対する要求性能は更に高まってきている。例えば、ハイブリッド自動車、太陽光発電システム、産業用モーター回路システム等に使用されるパワー半導体モジュールに関しては、高出力化が求められている。また、自動車のように部品の設置スペースに制約がある製品に使用されるパワー半導体モジュールに関しては、小型化、薄型化が求められている。 Such power semiconductor modules are required to have characteristics such as large current conduction, high heat dissipation characteristics, and heat resistance. In recent years, the required performance for power semiconductor modules has further increased. For example, high power is required for power semiconductor modules used in hybrid vehicles, solar power generation systems, industrial motor circuit systems, and the like. Further, power semiconductor modules used in products such as automobiles that have limited installation space for components are required to be smaller and thinner.
　パワー半導体モジュールの高出力化や小型化、薄型化を図るには、半導体素子（以下、「半導体チップ」ということがある。）から発生する熱の対策がこれまで以上に重要であり、パワー半導体モジュールの耐熱性や放熱特性をさらに高めることが求められている。　 Measures against heat generated from semiconductor elements (hereinafter sometimes referred to as “semiconductor chips”) are more important than ever to increase the power output, size, and thickness of power semiconductor modules. It is required to further improve the heat resistance and heat dissipation characteristics of the module. *
　パワー半導体モジュールの耐熱性を高める方法としては、半導体チップの材料である半導体基板として、Ｓｉ基板に代えて、より耐熱性に優れ、高温作動が可能であるＳｉＣ（シリコンカーバイド）基板やＧａＮ（ガリウムナイトライド）基板を用いる方法が注目されてきている。また、これらの半導体基板の特性を生かすためには、パワー半導体モジュールに用いる樹脂材料は耐熱性に優れることが好ましい。
　しかしながら、樹脂材料として、従来パワー半導体モジュールに広く使用されているシリコンゲル封止材は耐熱性が低く、酸素存在下、２００℃付近で分解するおそれがあった。また、無機フィラーを添加した高耐熱性エポキシ樹脂が耐熱性に優れる樹脂として知られているが、無機フィラーを添加して用いると、樹脂溶融粘度が高くなるため樹脂流動性が低下し、ボイド、配線断絶等を発生させるおそれがあった。 As a method for improving the heat resistance of the power semiconductor module, instead of the Si substrate, the semiconductor substrate that is the material of the semiconductor chip is replaced with a SiC (silicon carbide) substrate or GaN (gallium) that has higher heat resistance and can be operated at a high temperature. A method using a nitride substrate has been attracting attention. In order to take advantage of the characteristics of these semiconductor substrates, the resin material used for the power semiconductor module is preferably excellent in heat resistance.
However, as a resin material, a silicon gel encapsulant that has been widely used in power semiconductor modules in the past has low heat resistance and may be decomposed near 200 ° C. in the presence of oxygen. Moreover, although the high heat-resistant epoxy resin to which the inorganic filler is added is known as a resin having excellent heat resistance, if the inorganic filler is added and used, the resin melt viscosity becomes high, so that the resin fluidity decreases, voids, There was a risk of disconnection of wiring.
　一方、パワー半導体モジュールの放熱特性の向上や小型化・薄型化を図る方策として、近年、新たな構造の半導体モジュールが提案されている。
　例えば、特許文献２には、半導体チップの上下に、裏面金属層を有する絶縁基板をそれぞれ有し、さらに、それぞれの絶縁基板の裏面には放熱板、ヒートシンク及びヒートパイプ等の放熱構造体を有するパワー半導体モジュールが開示されている。この構造を有するパワー半導体モジュールにおいては、上下から半導体チップを冷却することができる。
　しかしながら、この文献に記載のパワー半導体モジュールにおいては、２枚の放熱板の間を封止する樹脂として硬いエポキシ系樹脂が用いられるため、樹脂流動性が低下して、ボイドや配線断絶等を発生させるおそれがあった。 On the other hand, in recent years, semiconductor modules having a new structure have been proposed as measures for improving the heat dissipation characteristics of power semiconductor modules and reducing the size and thickness.
For example, Patent Document 2 includes an insulating substrate having a back metal layer above and below a semiconductor chip, and further has a heat dissipation structure such as a heat sink, a heat sink, and a heat pipe on the back surface of each insulating substrate. A power semiconductor module is disclosed. In the power semiconductor module having this structure, the semiconductor chip can be cooled from above and below.
However, in the power semiconductor module described in this document, since a hard epoxy resin is used as a resin that seals between the two heat sinks, the resin fluidity is lowered, and there is a risk of generating voids or disconnection of wiring. was there.
　また、特許文献２には、配線やチップにかかる応力を緩和するために、ポリイミド系樹脂、ポリアミドイミド系樹脂等の柔軟な樹脂でこれらの部品の表面にパッシベーション膜を形成してもよいことも記載されているが、この場合には次のような問題があった。
　すなわち、溶剤可溶性のポリイミド樹脂やポリアミドイミド樹脂を使用する場合、樹脂の熱膨脹率が大きく、樹脂と半導体チップ表面との間に熱応力差が生じ、界面の剥離、封止体内部のクラックや劣化を生じさせるおそれがあった。
　また、パワー半導体モジュールの小型化という観点からは、特許文献２に記載のパワー半導体モジュールは十分とはいえなかった。 Further, in Patent Document 2, a passivation film may be formed on the surface of these parts with a flexible resin such as a polyimide resin or a polyamideimide resin in order to relieve stress applied to the wiring or the chip. Although described, there were the following problems in this case.
That is, when using a solvent-soluble polyimide resin or polyamide-imide resin, the thermal expansion coefficient of the resin is large, resulting in a difference in thermal stress between the resin and the surface of the semiconductor chip, peeling of the interface, cracking or deterioration inside the sealed body There was a risk of causing.
Further, from the viewpoint of miniaturization of the power semiconductor module, the power semiconductor module described in Patent Document 2 has not been sufficient.
　一方、熱硬化型のポリイミド樹脂やポリアミドイミド樹脂を使用する場合、これらの樹脂の硬化温度が高いため、部品の表面にパッシベーション膜を形成するためには、対象物には耐熱性が求められていた。また、樹脂硬化時に残留応力が発生するという問題があった。 On the other hand, when thermosetting polyimide resin or polyamideimide resin is used, since the curing temperature of these resins is high, the object is required to have heat resistance in order to form a passivation film on the surface of the component. It was. In addition, there is a problem that residual stress is generated when the resin is cured.
特開平８－２１３５４７号公報JP-A-8-213547 特開２００８－１２４４３０号公報（ＵＳ２００８／０２２４３０３Ａ１）JP 2008-124430 A (US2008 / 0224303A1)
　上述のように、次世代パワー半導体モジュールとして、耐熱性に優れる半導体基板を用いる半導体チップを使用し、両面放熱構造を有するパワー半導体モジュールが注目されているが、小型、薄型で、耐熱性及び放熱性に優れるパワー半導体モジュールを得るためにはさらなる検討が必要な状況にあった。 As described above, as a next-generation power semiconductor module, a power semiconductor module using a semiconductor chip using a semiconductor substrate having excellent heat resistance and having a double-sided heat dissipation structure has been attracting attention. In order to obtain a power semiconductor module with excellent performance, further studies were necessary.
　本発明は、上述した実情に鑑みてなされたものであって、小型、薄型で、耐熱性及び放熱性に優れる半導体装置、並びに、この半導体装置を効率よく製造することができる半導体装置の製造方法を提供することを目的とする。 The present invention has been made in view of the above-described circumstances, and is small, thin, excellent in heat resistance and heat dissipation, and a semiconductor device manufacturing method capable of efficiently manufacturing the semiconductor device. The purpose is to provide.
　本発明者は、上記課題を解決すべく鋭意研究した結果、半導体基板の表面側に形成された表面第１電極と、前記半導体基板の裏面側に形成された裏面電極とを備える１又は２以上の半導体チップが、前記裏面電極で放熱基板と金属接合されている半導体装置であって、前記半導体チップの表面部を封止する第１絶縁樹脂層と、前記半導体チップの側面部及び放熱基板表面を封止する第２絶縁樹脂層と、少なくとも前記第１絶縁樹脂層上に形成された表面第２電極と、及び前記第１絶縁樹脂層内を貫通し、前記表面第１電極と前記表面第２電極とを接続する１又は２以上の第１貫通ビアとを有する半導体装置は、小型、薄型で、耐熱性及び放熱性に優れることを見出し、本発明を完成するに至った。 As a result of earnest research to solve the above problems, the present inventor has one or more of the following: a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate. The semiconductor chip is a semiconductor device in which the back surface electrode is metal-bonded to the heat dissipation substrate, the first insulating resin layer sealing the surface portion of the semiconductor chip, the side surface portion of the semiconductor chip, and the surface of the heat dissipation substrate A second insulating resin layer for sealing, at least a surface second electrode formed on the first insulating resin layer, and penetrating through the first insulating resin layer, the surface first electrode and the surface first electrode A semiconductor device having one or two or more first through vias connecting two electrodes has been found to be small and thin and excellent in heat resistance and heat dissipation, and has completed the present invention.
　かくして本発明の第１によれば、下記（１）～（１１）の半導体装置が提供される。
（１）半導体基板の表面側に形成された表面第１電極と、前記半導体基板の裏面側に形成された裏面電極とを備える１又は２以上の半導体チップが、前記裏面電極で放熱基板と金属接合されている半導体装置であって、
前記半導体チップの表面部を封止する第１絶縁樹脂層と、
前記半導体チップの側面部及び放熱基板表面を封止する第２絶縁樹脂層と、
少なくとも前記第１絶縁樹脂層上に形成された表面第２電極と、及び
前記第１絶縁樹脂層内を貫通し、前記表面第１電極と前記表面第２電極とを接続する１又は２以上の第１貫通ビアと、
を有することを特徴とする半導体装置。
（２）前記放熱基板の表面積が前記半導体基板の表面積と等しいか、又はそれより大きいものであり、前記放熱基板が、前記半導体基板の裏面全体を覆うように前記裏面電極と金属接合されてなる（１）に記載の半導体装置。
（３）前記半導体チップを構成する半導体基板の厚みが４００μｍ以下である（１）又は（２）に記載の半導体装置。 Thus, according to the first aspect of the present invention, the following semiconductor devices (1) to (11) are provided.
(1) One or two or more semiconductor chips each including a first surface electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate are a heat dissipation substrate and a metal in the back electrode. A bonded semiconductor device comprising:
A first insulating resin layer for sealing the surface portion of the semiconductor chip;
A second insulating resin layer for sealing the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate;
At least one surface second electrode formed on the first insulating resin layer, and one or two or more that penetrate through the first insulating resin layer and connect the surface first electrode and the surface second electrode A first through via;
A semiconductor device comprising:
(2) The surface area of the heat dissipation substrate is equal to or greater than the surface area of the semiconductor substrate, and the heat dissipation substrate is metal-bonded to the back electrode so as to cover the entire back surface of the semiconductor substrate. The semiconductor device according to (1).
(3) The semiconductor device according to (1) or (2), wherein the semiconductor substrate constituting the semiconductor chip has a thickness of 400 μm or less.
（４）前記第２絶縁樹脂層内を貫通する１又は２以上の第２貫通ビアをさらに有する（１）～（３）のいずれかに記載の半導体装置。
（５）前記裏面電極と接続されている放熱基板上電極を前記放熱基板表面に有し、前記放熱基板上電極と前記表面第２電極が、前記第２貫通ビアにより接続されていることを特徴とする（４）に記載の半導体装置。
（６）前記第１絶縁樹脂層が、熱膨張率が２～２１ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂から構成され、第２絶縁樹脂層が、熱膨脹率が２～５０ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂から構成されていることを特徴とする（１）～（５）のいずれかに記載の半導体装置。 (4) The semiconductor device according to any one of (1) to (3), further including one or more second through vias that penetrate through the second insulating resin layer.
(5) A heat dissipation substrate upper electrode connected to the back electrode is provided on the surface of the heat dissipation substrate, and the heat dissipation substrate upper electrode and the surface second electrode are connected by the second through via. The semiconductor device according to (4).
(6) The first insulating resin layer is made of an insulating resin forming a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C., and the second insulating resin layer is a resin having a thermal expansion coefficient of 2 to 50 ppm / ° C. The semiconductor device according to any one of (1) to (5), which is made of an insulating resin that forms a layer.
（７）前記第１絶縁樹脂層が、ガラス転移温度が３００℃以上である絶縁性樹脂から構成され、前記第２絶縁樹脂層が、ガラス転移温度が２４０℃以上である絶縁性樹脂から構成されていることを特徴とする（１）～（６）のいずれかに記載の半導体装置。
（８）前記第１絶縁樹脂層及び前記第２絶縁樹脂層が、ポリイミド樹脂、ポリベンズイミダゾール樹脂及びポリベンズオキサゾール樹脂からなる群から選ばれる一種又は二種以上の絶縁性樹脂から構成されていることを特徴とする（１）～（７）のいずれかに記載の半導体装置。
（９）前記第１貫通ビア及び／又は第２貫通ビアが、めっき法又は金属ポスト材を用いる金属接合法により形成されたものである、（１）～（８）のいずれかに記載の半導体装置。 (7) The first insulating resin layer is made of an insulating resin having a glass transition temperature of 300 ° C. or higher, and the second insulating resin layer is made of an insulating resin having a glass transition temperature of 240 ° C. or higher. The semiconductor device according to any one of (1) to (6), wherein
(8) The first insulating resin layer and the second insulating resin layer are made of one or two or more insulating resins selected from the group consisting of a polyimide resin, a polybenzimidazole resin, and a polybenzoxazole resin. The semiconductor device according to any one of (1) to (7), wherein
(9) The semiconductor according to any one of (1) to (8), wherein the first through via and / or the second through via are formed by a plating method or a metal bonding method using a metal post material. apparatus.
（１０）配線を有する絶縁性放熱シートを有し、その配線部が前記表面第２電極と金属接合されている（１）～（９）のいずれかに記載の半導体装置。
（１１）リード電極を有し、そのリード電極が前記表面第２電極と金属接合されている（１）～（１０）のいずれかに記載の半導体装置。 (10) The semiconductor device according to any one of (1) to (9), further including an insulating heat dissipation sheet having wiring, the wiring portion of which is metal-bonded to the surface second electrode.
(11) The semiconductor device according to any one of (1) to (10), including a lead electrode, the lead electrode being metal-bonded to the surface second electrode.
　本発明の第２によれば、下記（１２）～（２０）の半導体装置の製造方法が提供される。
（１２）以下の工程１～４をこの順で有することを特徴とする半導体装置の製造方法。
（工程１）半導体基板の表面側に形成された表面第１電極と、前記半導体基板の裏面側に形成された裏面電極とを備える半導体チップと、
前記表面第１電極上に形成された１又は２以上の第１貫通ビア形成用金属ポストと、前記半導体チップの表面部及び前記第１貫通ビア形成用金属ポストを封止する第１絶縁樹脂層とを有する、１又は２以上の半導体チップ封止体を、
その裏面電極で放熱基板と金属接合する工程
（工程２）放熱基板と金属接合された前記半導体チップ封止体全体を覆うように、前記放熱基板表面に第２絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第２絶縁樹脂層を形成する工程
（工程３）前記第１絶縁樹脂層及び第２絶縁樹脂層表面を薄化処理して、第１絶縁樹脂層と第２絶縁樹脂層を平坦化し、貫通ビア形成用金属ポストの上面を露出させる工程
（工程４）少なくとも第１絶縁樹脂層表面上に、表面第２電極を形成する工程
（１３）前記半導体基板の厚みが４００μｍ以下である（１２）に記載の半導体装置の製造方法。
（１４）工程４の後に、前記表面第２電極に、配線を有する絶縁性放熱シート、配線を有する絶縁性放熱基板および放熱機能を有するリード電極から選ばれる放熱用部品を、該放熱用部品の配線部又はリード電極部で金属接合する工程をさらに有する、（１２）又は（１３）に記載の半導体装置の製造方法。 According to a second aspect of the present invention, there is provided the following semiconductor device manufacturing method (12) to (20).
(12) A method of manufacturing a semiconductor device comprising the following steps 1 to 4 in this order.
(Step 1) a semiconductor chip comprising a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate;
One or more first through via forming metal posts formed on the first surface electrode, and a first insulating resin layer for sealing the surface portion of the semiconductor chip and the first through via forming metal post. 1 or 2 or more semiconductor chip sealing bodies having
A step of metal bonding to the heat dissipation substrate with the back electrode (step 2) A second insulating resin layer forming resin is applied to the surface of the heat dissipation substrate so as to cover the entire semiconductor chip sealing body metal-bonded to the heat dissipation substrate. Step of forming a second insulating resin layer by heating at 300 to 450 ° C. (Step 3) Thinning treatment is performed on the surfaces of the first insulating resin layer and the second insulating resin layer. Step of flattening the insulating resin layer and exposing the upper surface of the through via forming metal post (Step 4) Step of forming a surface second electrode on at least the surface of the first insulating resin layer (13) The thickness of the semiconductor substrate is The method for manufacturing a semiconductor device according to (12), which is 400 μm or less.
(14) After step 4, a heat dissipating component selected from an insulating heat dissipating sheet having wiring, an insulating heat dissipating substrate having wiring, and a lead electrode having a heat dissipating function is applied to the surface second electrode. The method for manufacturing a semiconductor device according to (12) or (13), further comprising a step of metal bonding at the wiring portion or the lead electrode portion.
（１５）少なくとも工程２の前に、以下の工程ａ～ｃを有する（１２）～（１４）のいずれかに記載の半導体装置の製造方法。
（工程ａ）放熱基板表面にめっきレジスト膜を成膜し、前記放熱基板の所定部が露出するように、めっきレジスト膜に開口部を設ける工程
（工程ｂ）前記開口部内に金属を充填し、第２貫通ビア形成用金属ポストを形成する工程
（工程ｃ）めっきレジスト膜を除去する工程
（１６）少なくとも工程２の前に、放熱基板表面の所定位置に、第２貫通ビア形成用金属ポストを金属接合法により形成する工程を有する、（１２）～（１４）のいずれかに記載の半導体装置の製造方法。 (15) The method for manufacturing a semiconductor device according to any one of (12) to (14), which includes the following steps a to c at least before step 2.
(Step a) Forming a plating resist film on the surface of the heat dissipation substrate and providing an opening in the plating resist film so that a predetermined portion of the heat dissipation substrate is exposed (Step b) Filling the opening with a metal, Step of forming second through via forming metal post (step c) Step of removing plating resist film (16) Prior to at least step 2, the second through via forming metal post is placed at a predetermined position on the surface of the heat dissipation substrate. The method for manufacturing a semiconductor device according to any one of (12) to (14), including a step of forming by a metal bonding method.
（１７）前記半導体チップ封止体が、以下の工程１．１～１．５、１．７及び１．８をこの順で有する製造工程により得られたものである、（１２）～（１６）のいずれかに記載の半導体装置の製造方法。
（工程１．１）表面第１電極が形成された半導体基板の表面にめっきレジスト膜を成膜する工程
（工程１．２）前記表面第１電極の所定部が露出するように、めっきレジスト膜に開口部を設ける工程
（工程１．３）前記開口部に金属を充填し、第１貫通ビア形成用金属ポストを形成する工程
（工程１．４）めっきレジスト膜を除去する工程
（工程１．５）前記第１貫通ビア形成用金属ポストを覆うように、前記半導体基板表面に第１絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第１絶縁樹脂層を形成し、同時に前記金属ポストのアニール処理を行う工程
（工程１．７）前記半導体基板の裏面に裏面電極を形成する工程
（工程１．８）前記半導体基板をダイシングにより個片化する工程
（１８）前記（工程１．５）の後、（工程１．７）の前に、（工程１．６）前記半導体基板の裏面の薄板化処理により、半導体基板の厚みを４００μｍ以下にする工程を有する（１７）に記載の半導体装置の製造方法。 (17) The semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.1 to 1.5, 1.7 and 1.8 in this order: (12) to (16 ) A method for manufacturing a semiconductor device according to any one of the above.
(Step 1.1) Step of depositing a plating resist film on the surface of the semiconductor substrate on which the first surface electrode is formed (Step 1.2) A plating resist film so that a predetermined portion of the first surface electrode is exposed. (Step 1.3) Step of filling the opening with metal and forming a metal post for forming a first through via (Step 1.4) Step of removing the plating resist film (Step 1. 5) A first insulating resin layer forming resin is applied to the surface of the semiconductor substrate so as to cover the first through via forming metal post, and heated at 300 to 450 ° C. to form a first insulating resin layer. Simultaneously annealing the metal posts (step 1.7) forming a back electrode on the back surface of the semiconductor substrate (step 1.8) separating the semiconductor substrate by dicing (18) After step 1.5), Prior to 1.7), (step 1.6) by the rear surface of the semiconductor substrate of the thinning process, a method of manufacturing a semiconductor device according to a step of the thickness of the semiconductor substrate to 400μm or less (17).
（１９）前記半導体チップ封止体が、以下の工程１．９、１．１０、１．１２及び１．１３をこの順で有する製造工程により得られたものである、（１２）～（１５）のいずれかに記載の半導体装置の製造方法。
（工程１．９）表面第１電極が形成された半導体基板の前記表面第１電極上に、第１貫通ビア形成用金属ポストを金属接合法により形成する工程
（工程１．１０）前記第１貫通ビア形成用金属ポストを覆うように、前記半導体基板表面に第１絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第１絶縁樹脂層を形成する工程
（工程１．１２）前記半導体基板の裏面に裏面電極を形成する工程
（工程１．１３）前記半導体基板をダイシングにより個片化する工程
（２０）前記（工程１．１０）の後、（工程１．１２）の前に、（工程１．１１）前記半導体基板の裏面の薄板化処理により、半導体基板の厚みを４００μｍ以下にする工程を有する（１９）に記載の半導体装置の製造方法。 (19) The semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.9, 1.10, 1.12 and 1.13 in this order (12) to (15 ) A method for manufacturing a semiconductor device according to any one of the above.
(Step 1.9) Forming a first through via forming metal post by a metal bonding method on the surface first electrode of the semiconductor substrate on which the surface first electrode is formed (Step 1.10) A step of applying a first insulating resin layer forming resin to the surface of the semiconductor substrate so as to cover the through via forming metal post and heating at 300 to 450 ° C. to form a first insulating resin layer (step 1.12) ) Step of forming a back electrode on the back surface of the semiconductor substrate (Step 1.13) Step of dicing the semiconductor substrate by dicing (20) After (Step 1.10), (Step 1.12) Before (Step 1.11), the method of manufacturing a semiconductor device according to (19), including a step of reducing the thickness of the semiconductor substrate to 400 μm or less by thinning processing of the back surface of the semiconductor substrate.
　本発明の半導体装置は、小型、薄型で、耐熱性及び放熱性に優れる。
　本発明の製造方法によれば、小型、薄型で、耐熱性及び放熱性に優れる半導体装置を効率よく製造することができる。本発明の製造方法は、本発明の半導体装置の製造方法として有用である。 The semiconductor device of the present invention is small and thin, and has excellent heat resistance and heat dissipation.
According to the manufacturing method of the present invention, a semiconductor device that is small, thin, and excellent in heat resistance and heat dissipation can be efficiently manufactured. The manufacturing method of the present invention is useful as a method for manufacturing a semiconductor device of the present invention.
本発明のパワー半導体モジュール１００Ａの模式的な断面図である。It is typical sectional drawing of power semiconductor module 100A of this invention. 本発明のパワー半導体モジュール１００Ｂの模式的な断面図である。It is typical sectional drawing of the power semiconductor module 100B of this invention. 本発明のパワー半導体モジュール１００Ｃの模式的な断面図である。It is a typical sectional view of power semiconductor module 100C of the present invention. 本発明のパワー半導体モジュール１００Ｄの模式的な断面図である。It is typical sectional drawing of power semiconductor module 100D of this invention. 本発明のパワー半導体モジュール１００Ｅの模式的な断面図である。It is typical sectional drawing of the power semiconductor module 100E of this invention. 本発明のパワー半導体モジュール１００Ｅの製造工程図である。It is a manufacturing-process figure of the power semiconductor module 100E of this invention. 半導体チップの製造工程図である。It is a manufacturing process figure of a semiconductor chip. 従来のパワー半導体モジュールの模式的な断面図である。It is typical sectional drawing of the conventional power semiconductor module.
　以下、本発明を、１）半導体装置、及び、２）半導体装置の製造方法に項分けして説明する。
１）半導体装置
　本発明の半導体装置は、半導体基板の表面側に形成された表面第１電極と、前記半導体基板の裏面側に形成された裏面電極とを備える１又は２以上の半導体チップが、前記裏面電極で放熱基板と金属接合されている半導体装置であって、前記半導体チップの表面部を封止する第１絶縁樹脂層と、前記半導体チップの側面部及び放熱基板表面を封止する第２絶縁樹脂層と、少なくとも前記第１絶縁樹脂層上に形成された表面第２電極と、及び前記第１絶縁樹脂層内を貫通し、前記表面第１電極と前記表面第２電極とを接続する１又は２以上の第１貫通ビアとを有することを特徴とする。 Hereinafter, the present invention will be described in terms of 1) a semiconductor device and 2) a method for manufacturing a semiconductor device.
1) Semiconductor device A semiconductor device according to the present invention includes one or more semiconductor chips each including a first front electrode formed on a front surface side of a semiconductor substrate and a back electrode formed on a back surface side of the semiconductor substrate. A semiconductor device that is metal-bonded to the heat dissipation substrate by the back electrode, wherein the first insulating resin layer that seals the surface portion of the semiconductor chip, and the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate are sealed. 2 insulating resin layers, at least a surface second electrode formed on the first insulating resin layer, and the first insulating resin layer penetrating and connecting the surface first electrode and the surface second electrode And having one or more first through vias.
　なお、本明細書において、「金属接合」とは、高温（通常３００℃以上、好ましくは４００℃以上）条件下においても接合部位の溶融破断が起きない耐熱金属接合をいう。金属接合の方法としては、ナノ金粒子、ナノ銀粒子、ナノ銅粒子等のナノ金属粒子により直接接合する方法、耐熱温度３００℃以上の高耐熱ハンダにより接合する方法、高周波接合により金属同士を接合する方法等が挙げられる。 In this specification, “metal bonding” refers to heat-resistant metal bonding in which melt fracture does not occur at high temperatures (usually 300 ° C. or higher, preferably 400 ° C. or higher). Metal bonding methods include direct bonding using nano metal particles such as nano gold particles, nano silver particles, and nano copper particles, bonding using high heat-resistant solder having a heat resistant temperature of 300 ° C. or higher, and bonding metals by high frequency bonding. And the like.
　以下、本発明の半導体装置について、図面を参照しながら詳細に説明する。
　本発明の半導体装置（パワー半導体モジュール）の模式的な断面図を図１～図５に示す。
　図１に示すパワー半導体モジュール１００Ａは、半導体基板２００と、該半導体基板２００の表面側に形成された表面第１電極３５と、及び、前記半導体基板２００の裏面側に裏面電極３２とを備える半導体チップが、裏面電極３２で放熱基板１４に金属接合された構造を有する。
　また、前記半導体チップの表面部は第１絶縁樹脂層２０で封止され、半導体チップの側面部及び放熱基板１４は第２絶縁樹脂層２１で封止されている。 Hereinafter, a semiconductor device of the present invention will be described in detail with reference to the drawings.
1 to 5 are schematic cross-sectional views of a semiconductor device (power semiconductor module) of the present invention.
A power semiconductor module 100A shown in FIG. 1 includes a semiconductor substrate 200, a front surface first electrode 35 formed on the front surface side of the semiconductor substrate 200, and a back surface electrode 32 on the back surface side of the semiconductor substrate 200. The chip has a structure in which the chip is metal-bonded to the heat dissipation substrate 14 with the back electrode 32.
The surface portion of the semiconductor chip is sealed with a first insulating resin layer 20, and the side surface portion of the semiconductor chip and the heat dissipation substrate 14 are sealed with a second insulating resin layer 21.
　半導体チップとしては、ＩＧＢＴ、ＭＯＳＦＥＴ、ＦＷＤ等のパワー半導体チップが挙げられる。半導体チップの裏面電極３２としては、例えば、半導体チップがＩＧＢＴである場合、ＩＧＢＴのコレクタ電極等が挙げられ、表面第１電極３５としては、ＩＧＢＴのエミッタ電極等が挙げられる。 Examples of semiconductor chips include power semiconductor chips such as IGBTs, MOSFETs, and FWDs. As the back surface electrode 32 of the semiconductor chip, for example, when the semiconductor chip is an IGBT, an IGBT collector electrode or the like can be cited. As the front surface first electrode 35, an IGBT emitter electrode or the like can be cited.
　半導体基板２００としては、Ｓｉ（シリコン）基板、ＳｉＣ（シリコンカーバイド）基板、ＧａＮ（ガリウムナイトライド）基板等が挙げられ、耐熱性の観点からは、ＳｉＣ（シリコンカーバイド）基板、ＧａＮ（ガリウムナイトライド）基板が好ましい。半導体基板２００の厚みは、通常６００μｍ以下、好ましくは４００μｍ以下、より好ましくは３０μｍ～４００μｍである。厚みが４００μｍ以下であることで、変換効率に優れた薄型の半導体装置が得られる。 Examples of the semiconductor substrate 200 include a Si (silicon) substrate, a SiC (silicon carbide) substrate, and a GaN (gallium nitride) substrate. From the viewpoint of heat resistance, a SiC (silicon carbide) substrate and a GaN (gallium nitride) substrate. ) A substrate is preferred. The thickness of the semiconductor substrate 200 is usually 600 μm or less, preferably 400 μm or less, and more preferably 30 μm to 400 μm. When the thickness is 400 μm or less, a thin semiconductor device having excellent conversion efficiency can be obtained.
　表面第２電極３６は、第１絶縁樹脂層２０の表面に形成され、第１貫通ビア３４を介して表面第１電極３５と接続されている。表面第２電極３６は放熱機能も兼ね備えており、その面積は、最大で放熱基板１４の面積と同等の大きさまで拡大することができる。したがって、本発明の半導体装置は設計の自由度が高い。このように、表面第２電極３６と第１貫通ビア３４を利用する構造を採用することで薄型化が達成され、また、放熱基板１４と表面第２電極３６とからなる両面放熱構造を有することで、高い放熱性が達成される。 The surface second electrode 36 is formed on the surface of the first insulating resin layer 20 and is connected to the surface first electrode 35 through the first through via 34. The surface second electrode 36 also has a heat dissipation function, and its area can be expanded to a size equivalent to the area of the heat dissipation substrate 14 at the maximum. Therefore, the semiconductor device of the present invention has a high degree of design freedom. As described above, by adopting a structure using the surface second electrode 36 and the first through via 34, a reduction in thickness is achieved, and a double-sided heat dissipation structure including the heat dissipation substrate 14 and the surface second electrode 36 is provided. Thus, high heat dissipation is achieved.
　放熱基板１４としては、ＤＢＣ（Ｄｉｒｅｃｔ　Ｂｏｎｄｅｄ　Ｃｏｐｐｅｒ）基板、ＡＭＣ（Ａｃｔｉｖｅ　Ｍｅｔａｌ　Ｂｒａｚｅｄ　Ｃｏｐｐｅｒ）基板等の銅貼り基板が挙げられる。図１に示すパワー半導体モジュール１００Ａは、放熱基板として、セラミックス基板１４ｂの両面に銅パターン１４ａが接合された構造のＤＢＣ基板１４を使用した例である。 Examples of the heat dissipation substrate 14 include copper-clad substrates such as a DBC (Direct Bonded Copper) substrate and an AMC (Active Metal Brazed Copper) substrate. A power semiconductor module 100A shown in FIG. 1 is an example in which a DBC substrate 14 having a structure in which copper patterns 14a are bonded to both surfaces of a ceramic substrate 14b is used as a heat dissipation substrate.
　放熱基板１４の表面積は、放熱性の観点から、半導体チップを構成する半層体基板２００の表面積と等しいか、これよりも大きいことが好ましい。
　また、同様の理由から、放熱基板１４は半導体基板２００の裏面全体を覆うように前記半導体チップの裏面電極３２で金属接合されることが好ましい。 The surface area of the heat dissipation substrate 14 is preferably equal to or greater than the surface area of the half-layer substrate 200 constituting the semiconductor chip from the viewpoint of heat dissipation.
For the same reason, the heat dissipation substrate 14 is preferably metal-bonded by the back electrode 32 of the semiconductor chip so as to cover the entire back surface of the semiconductor substrate 200.
　パワー半導体モジュール１００Ａにおいて、第１貫通ビア３４の設置断面積の合計は、表面第１電極３５の断面積に対して、２０％以上が好ましく、２０～５０％がより好ましく、２５～３５％がさらに好ましい。第１貫通ビア３４の設置断面積の合計が表面第１電極３５の断面積に対して２０％以上であることで、十分な導電性を得ることができる。また、表面第１電極表面で発生する熱を表面第２電極面に効率よく伝達することができ、デバイス表面の温度上昇による変換効率の低下や、熱応力発生による半導体チップの劣化を抑制することができる。一方、第１貫通ビア３４の設置断面積の合計が５０％以下であることで、貫通ビアの形成にかかるコストを抑えることができる。
　第１貫通ビア３４は、例えば、めっき法又は金属ポスト材を用いる金属接合法により形成することができる。 In the power semiconductor module 100A, the total installation sectional area of the first through vias 34 is preferably 20% or more, more preferably 20 to 50%, and more preferably 25 to 35% with respect to the sectional area of the surface first electrode 35. Further preferred. Sufficient conductivity can be obtained when the total cross-sectional area of the first through vias 34 is 20% or more with respect to the cross-sectional area of the surface first electrode 35. In addition, heat generated on the surface of the first surface electrode can be efficiently transferred to the surface of the second surface of the surface, thereby suppressing deterioration in conversion efficiency due to temperature rise on the device surface and deterioration of the semiconductor chip due to generation of thermal stress. Can do. On the other hand, the total installation cross-sectional area of the first through via 34 is 50% or less, so that the cost for forming the through via can be suppressed.
The first through via 34 can be formed by, for example, a plating method or a metal bonding method using a metal post material.
　パワー半導体モジュール１００Ａにおいて、半導体チップの表面部は第１絶縁樹脂層２０により封止され、半導体チップの側面部及び放熱基板１４の表面は、第２絶縁樹脂層２１により封止されている。 In the power semiconductor module 100A, the surface portion of the semiconductor chip is sealed with the first insulating resin layer 20, and the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate 14 are sealed with the second insulating resin layer 21.
　第１絶縁樹脂層２０及び第２絶縁樹脂層２１を構成する絶縁性樹脂の弾性率は２～８ＧＰａが好ましい。後述するように、これらの絶縁樹脂層に対して、薄化処理が行われるが、このとき、弾性率が８ＧＰａを越えると樹脂が硬く脆くなり、切削時に表面荒れを起こすおそれがある。一方、弾性率が２ＧＰａを下回ると切削時に樹脂が伸びやすくなり、加工速度が低下するおそれや、綺麗な加工がしにくくなるおそれがある。 The elastic modulus of the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is preferably 2 to 8 GPa. As will be described later, a thinning process is performed on these insulating resin layers. At this time, if the elastic modulus exceeds 8 GPa, the resin becomes hard and brittle, and there is a possibility of causing surface roughness during cutting. On the other hand, if the elastic modulus is less than 2 GPa, the resin tends to be stretched during cutting, and the processing speed may be reduced, and it may be difficult to perform beautiful processing.
　また、第１絶縁樹脂層２０及び第２絶縁樹脂層２１を構成する絶縁性樹脂は、前者で熱膨張率が２～２１ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂であることが、後者で熱膨脹率が２～５０ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂であることが、好ましい。第１絶縁樹脂層２０及び第２絶縁樹脂層２１を構成する絶縁性樹脂はいずれも、熱膨張率が２～２１ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂であるのが、より好ましい。
　すなわち、第１絶縁樹脂層２０は半導体チップの上部を封止するものであることから、第１絶縁樹脂層２０の熱膨張率は、半導体チップを構成する半導体基板２００の熱膨張率に近い値であることが好ましい。例えば、半導体基板としてＳｉＣ基板を用いる場合は、第１絶縁樹脂層２０の熱膨脹率は、２～８ｐｐｍ／℃が好ましく、４～６ｐｐｍ／℃がより好ましい。
　第１絶縁樹脂層２０の熱膨張率を半導体基板材料の熱膨脹率に合わせることで、第１絶縁樹脂層２０が設けられた半導体チップを放熱基板１４に金属接合する際に、前記半導体チップの反りを抑制することができる。また、半導体装置の使用時に半導体チップが発熱しても、半導体チップと第１絶縁樹脂層２０間の熱応力差が低減され、接合面、封止面での剥離等の問題が解消される。 Further, the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is an insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C. in the former, and in the latter. An insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 50 ppm / ° C. is preferable. More preferably, the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 is an insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C.
That is, since the first insulating resin layer 20 seals the upper part of the semiconductor chip, the thermal expansion coefficient of the first insulating resin layer 20 is a value close to the thermal expansion coefficient of the semiconductor substrate 200 constituting the semiconductor chip. It is preferable that For example, when a SiC substrate is used as the semiconductor substrate, the coefficient of thermal expansion of the first insulating resin layer 20 is preferably 2 to 8 ppm / ° C, and more preferably 4 to 6 ppm / ° C.
By matching the coefficient of thermal expansion of the first insulating resin layer 20 to the coefficient of thermal expansion of the semiconductor substrate material, the warp of the semiconductor chip when the semiconductor chip provided with the first insulating resin layer 20 is metal-bonded to the heat dissipation substrate 14. Can be suppressed. Further, even if the semiconductor chip generates heat during use of the semiconductor device, the difference in thermal stress between the semiconductor chip and the first insulating resin layer 20 is reduced, and problems such as peeling on the bonding surface and the sealing surface are solved.
　第２絶縁樹脂層２１は放熱基板１４の上部を封止するものであることから、第２絶縁樹脂層２１の熱膨張率は、放熱基板１４の熱膨脹率に近い値であることが好ましい。例えば、放熱基板１４の主骨格セラミックス部位の熱膨脹率は通常８ｐｐｍ／℃程度であることから、このような放熱基板を用いる場合は、第２絶縁樹脂層２１は、熱膨脹率が８～１７ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂から構成されることが好ましい。
　第２絶縁樹脂層２１の熱膨張率を放熱基板１４の熱膨張率に合わせることで、第２絶縁樹脂層２１と放熱基板１４間の熱応力差が低減される。 Since the second insulating resin layer 21 seals the upper portion of the heat dissipation substrate 14, the thermal expansion coefficient of the second insulating resin layer 21 is preferably a value close to the thermal expansion coefficient of the heat dissipation substrate 14. For example, since the thermal expansion coefficient of the main skeleton ceramic portion of the heat dissipation substrate 14 is usually about 8 ppm / ° C., when such a heat dissipation substrate is used, the second insulating resin layer 21 has a thermal expansion rate of 8 to 17 ppm / ° C. It is preferable that the resin layer is made of an insulating resin.
By matching the thermal expansion coefficient of the second insulating resin layer 21 with the thermal expansion coefficient of the heat dissipation board 14, the difference in thermal stress between the second insulating resin layer 21 and the heat dissipation board 14 is reduced.
　また、第２絶縁樹脂層２１に上部放熱シートや放熱機能を有するリード電極を接合する場合、これらの材料の熱膨張率に合わせて第２絶縁樹脂層２１の熱膨張率を調節することが好ましい。より具体的には、前記放熱機構の材料が銅やアルミニウムの場合は、第２絶縁樹脂層２１の熱膨張率を、それぞれ１６．３ｐｐｍ／℃付近、２１ｐｐｍ／℃付近に合わせることが好ましい。 Moreover, when joining an upper thermal radiation sheet and the lead electrode which has a thermal radiation function to the 2nd insulating resin layer 21, it is preferable to adjust the thermal expansion coefficient of the 2nd insulating resin layer 21 according to the thermal expansion coefficient of these materials. . More specifically, when the material of the heat dissipation mechanism is copper or aluminum, it is preferable to match the thermal expansion coefficient of the second insulating resin layer 21 to around 16.3 ppm / ° C. and around 21 ppm / ° C., respectively.
　第１絶縁樹脂層２０と第２絶縁樹脂層２１を同一の樹脂で形成してもよい。このようにすることで、樹脂界面剥離を大幅に抑制することができる。 The first insulating resin layer 20 and the second insulating resin layer 21 may be formed of the same resin. By doing in this way, resin interface peeling can be suppressed significantly.
　第１絶縁樹脂層２０や第２絶縁樹脂層２１を構成する絶縁性樹脂としては、例えば、ポリイミド樹脂、ポリベンズイミダゾール樹脂及びポリベンズオキサゾール樹脂等が挙げられる。これらの樹脂は一種単独で、あるいは二種以上を組み合わせて用いることができる。これらの中でもポリイミド樹脂が好ましい。 Examples of the insulating resin constituting the first insulating resin layer 20 and the second insulating resin layer 21 include polyimide resin, polybenzimidazole resin, and polybenzoxazole resin. These resins can be used alone or in combination of two or more. Among these, a polyimide resin is preferable.
　上記の熱膨張率を有するポリイミドを合成する方法としては、剛直構造の芳香族テトラカルボン酸又はその酸無水物と剛直構造芳香族ジアミンとを重縮合させることによってポリアミド酸を合成し、次いで熱イミド化、化学イミド化等の手法でポリイミド樹脂に変換する方法が挙げられる。また、熱膨脹率の制御は、柔軟構造の芳香族テトラカルボン酸又はその酸無水物、柔軟構造の芳香族ジアミンを必要に応じで共重合することで達成できる。
　ここで、「剛直構造」とは、運動性が低く、自身では湾曲できない、棒状の剛直鎖を形成していることを意味し、柔軟構造とは、前記剛直構造ではないことを意味する。 As a method of synthesizing a polyimide having the above-mentioned coefficient of thermal expansion, a polyamic acid is synthesized by polycondensation of a rigid structure aromatic tetracarboxylic acid or acid anhydride thereof and a rigid structure aromatic diamine, and then a thermal imide Examples of the method include conversion to a polyimide resin by a method such as chemical conversion or chemical imidization. Control of the coefficient of thermal expansion can be achieved by copolymerizing an aromatic tetracarboxylic acid having a flexible structure or an acid anhydride thereof and an aromatic diamine having a flexible structure as necessary.
Here, the “rigid structure” means that a rod-like rigid straight chain that has low mobility and cannot be bent by itself is formed, and the flexible structure means that it is not the rigid structure.
　剛直構造の芳香族テトラカルボン酸等としては、例えば、ピロメリット酸二無水物、３，３’，４，４’－ベンゾフェノンテトラカルボン酸二無水物、ベンゼン－１，２，３，４－テトラカルボン酸二無水物、２，２’，３，３’－ベンゾフェノンテトラカルボン酸二無水物、２，３，３’，４’－ベンゾフェノンテトラカルボン酸二無水物、ナフタレン－２，３，６，７－テトラカルボン酸二無水物、ナフタレン－１，２，５，６－テトラカルボン酸二無水物、ナフタレン－１，２，４，５－テトラカルボン酸二無水物、ナフタレン－１，２，５，８－テトラカルボン酸二無水物、ナフタレン－１，２，６，７－テトラカルボン酸二無水物、４，８－ジメチル－１，２，３，５，６，７－ヘキサヒドロナフタレン－１，２，５，６－テトラカルボン酸二無水物、４，８－ジメチル－１，２，３，５，６，７－ヘキサヒドロナフタレン－２，３，６，７－テトラカルボン酸二無水物、２，６－ジクロロナフタレン－１，４，５，８－テトラカルボン酸二無水物、２，７－ジクロロナフタレン－１，４，５，８－テトラカルボン酸二無水物、２，３，６，７－テトラクロロナフタレン－１，４，５，８－テトラカルボン酸二無水物、１，４，５，８－テトラクロロナフタレン－２，３，６，７－テトラカルボン酸二無水物、３，３’，４，４’－ビフェニルテトラカルボン酸二無水物、２，２’，３，３’－ビフェニルテトラカルボン酸二無水物、２，３，３’，４’－ジフェニルテトラカルボン酸二無水物、２，３”，４，４”－ｐ－テルフェニルテトラカルボン酸二無水物、２，２”，３，３”－ｐ－テルフェニルテトラカルボン酸二無水物、２，３，３”，４”－ｐ－テルフェニルテトラカルボン酸二無水物、２，２－ビス（２，３－ジカルボキシフェニル）－プロパン二無水物、２，２－ビス（３，４－ジカルボキシフェニル）－プロパン二無水物、ビス（２，３－ジカルボキシフェニル）エーテル二無水物、ビス（３，４－ジカルボキシフェニル）エーテル二無水物、ビス（２，３－ジカルボキシフェニル）メタン二無水物、ビス（３，４－ジカルボキシフェニル）メタン二無水物、ビス（２，３－ジカルボキシフェニル）スルホン二無水物、ビス（３，４－ジカルボキシフェニル）スルホン二無水物、１，１－ビス（２，３－ジカルボキシフェニル）エタン二無水物、１，１－ビス（３，４－ジカルボキシフェニル）エタン二無水物、ペリレン－２，３，８，９－テトラカルボン酸二無水物、ペリレン－３，４，９，１０－テトラカルボン酸二無水物、ペリレン－４，５，１０，１１－テトラカルボン酸二無水物、ペリレン－５，６，１１，１２－テトラカルボン酸二無水物、フェナンスレン－１，２，７，８－テトラカルボン酸二無水物、フェナンスレン－１，２，６，７－テトラカルボン酸二無水物、フェナンスレン－１，２，９，１０－テトラカルボン酸二無水物等の芳香族テトラカルボン酸二無水物及びその水添加物；シクロペンタン－１，２，３，４－テトラカルボン酸二無水物、シクロブタンテトラカルボン酸二無水物、ビシクロ［２，２，２］オクタ－７－エン－２－エキソ，３－エキソ，５－エキソ，６－エキソテトラカルボン酸２，３：５，６－二無水物、ビシクロ［２，２，１］ヘプタン－２－エキソ，３－エキソ，５－エキソ，６－エキソテトラカルボン酸２，３：５，６－二無水物等の脂環式酸二無水物；ピラジン－２，３，５，６－テトラカルボン酸二無水物、ピロリジン－２，３，４，５－テトラカルボン酸二無水物、チオフェン－２，３，４，５－テトラカルボン酸二無水物等の複素環誘導体酸二無水物；これらに対応するテトラカルボン酸等が挙げられる。 Examples of the rigid structure aromatic tetracarboxylic acid include pyromellitic dianhydride, 3,3 ′, 4,4′-benzophenone tetracarboxylic dianhydride, benzene-1,2,3,4-tetra Carboxylic dianhydride, 2,2 ′, 3,3′-benzophenone tetracarboxylic dianhydride, 2,3,3 ′, 4′-benzophenone tetracarboxylic dianhydride, naphthalene-2,3,6 7-tetracarboxylic dianhydride, naphthalene-1,2,5,6-tetracarboxylic dianhydride, naphthalene-1,2,4,5-tetracarboxylic dianhydride, naphthalene-1,2,5 , 8-tetracarboxylic dianhydride, naphthalene-1,2,6,7-tetracarboxylic dianhydride, 4,8-dimethyl-1,2,3,5,6,7-hexahydronaphthalene-1 , 2,5,6-tet Carboxylic dianhydride, 4,8-dimethyl-1,2,3,5,6,7-hexahydronaphthalene-2,3,6,7-tetracarboxylic dianhydride, 2,6-dichloronaphthalene- 1,4,5,8-tetracarboxylic dianhydride, 2,7-dichloronaphthalene-1,4,5,8-tetracarboxylic dianhydride, 2,3,6,7-tetrachloronaphthalene-1 , 4,5,8-tetracarboxylic dianhydride, 1,4,5,8-tetrachloronaphthalene-2,3,6,7-tetracarboxylic dianhydride, 3,3 ′, 4,4 ′ -Biphenyltetracarboxylic dianhydride, 2,2 ', 3,3'-biphenyltetracarboxylic dianhydride, 2,3,3', 4'-diphenyltetracarboxylic dianhydride, 2,3 ", 4,4 "-p-terphenyltetracarboxylic dianhydride, 2 2 ", 3,3" -p-terphenyltetracarboxylic dianhydride, 2,3,3 ", 4" -p-terphenyltetracarboxylic dianhydride, 2,2-bis (2,3- Dicarboxyphenyl) -propane dianhydride, 2,2-bis (3,4-dicarboxyphenyl) -propane dianhydride, bis (2,3-dicarboxyphenyl) ether dianhydride, bis (3,4 -Dicarboxyphenyl) ether dianhydride, bis (2,3-dicarboxyphenyl) methane dianhydride, bis (3,4-dicarboxyphenyl) methane dianhydride, bis (2,3-dicarboxyphenyl) Sulfone dianhydride, bis (3,4-dicarboxyphenyl) sulfone dianhydride, 1,1-bis (2,3-dicarboxyphenyl) ethane dianhydride, 1,1-bis (3,4-di Carboxyphe Nyl) ethane dianhydride, perylene-2,3,8,9-tetracarboxylic dianhydride, perylene-3,4,9,10-tetracarboxylic dianhydride, perylene-4,5,10,11 -Tetracarboxylic dianhydride, perylene-5,6,11,12-tetracarboxylic dianhydride, phenanthrene-1,2,7,8-tetracarboxylic dianhydride, phenanthrene-1,2,6, Aromatic tetracarboxylic dianhydrides such as 7-tetracarboxylic dianhydride and phenanthrene-1,2,9,10-tetracarboxylic dianhydride and their water additives; cyclopentane-1,2,3 4-tetracarboxylic dianhydride, cyclobutanetetracarboxylic dianhydride, bicyclo [2,2,2] oct-7-ene-2-exo, 3-exo, 5-exo, 6-exotetracarboxylic acid 2 3: 5,6-dianhydride, bicyclo [2,2,1] heptane-2-exo, 3-exo, 5-exo, 6-exotetracarboxylic acid 2,3: 5,6-dianhydride, etc. An alicyclic acid dianhydride; pyrazine-2,3,5,6-tetracarboxylic dianhydride, pyrrolidine-2,3,4,5-tetracarboxylic dianhydride, thiophene-2,3,4 , 5-tetracarboxylic dianhydrides and the like, and heterocyclic derivative dianhydrides such as tetracarboxylic acids corresponding thereto.
　これらの中でも、熱膨張率と残留応力が小さく、銅基板等との密着性に優れる膜をより簡便に得られることから、本発明においては、剛直構造の芳香族テトラカルボン酸等として、ピロメリット酸、ピロメリット酸二無水物（ＰＭＤＡ）、ビフェニルテトラカルボン酸、及びビフェニルテトラカルボン酸二無水物（ｓ－ＢＰＤＡ）からなる群より選ばれる少なくとも１種を使用することが好ましい。 Among these, since a coefficient of thermal expansion and residual stress is small and a film having excellent adhesion to a copper substrate or the like can be obtained more easily, in the present invention, as a rigid structure aromatic tetracarboxylic acid, etc. It is preferable to use at least one selected from the group consisting of acid, pyromellitic dianhydride (PMDA), biphenyltetracarboxylic acid, and biphenyltetracarboxylic dianhydride (s-BPDA).
　剛直構造の芳香族ジアミンとしては、例えば、４，４′－ジアミノベンズアニリド、４，４’－ジアミノ－２，２’－ジトリフルオロメチルビフェニル、２，２’－ジ（ｐ－アミノフェニル）－５，５’－ビスベンゾオキサゾール、２，２’－ジ（ｐ－アミノフェニル）－６，６’－ビスベンゾオキサゾール、２，２’－ジ（ｐ－アミノフェニル）－５，５’－ビスベンズイミダゾール、３，６－（４－アミノフェニル）ピリダジン、４，４’－ジアミノベンズアニリド、ｐ－フェニレンジアミン（ＰＰＤＡ）、４，４’－ジアミノビフェニル、ｍ－フェニレンジアミン、１－イソプロピル－２，４－フェニレンジアミン、ｐ－フェニレンジアミン、４，４’－ジアミノジフェニルスルフィド、３，３’－ジアミノジフェニルスルフィド、４，４’－ジアミノジフェニルスルホン、３，３’－ジアミノジフェニルスルホン、４，４’－ジアミノジフェニルエーテル、３，３’－ジアミノジフェニルエーテル、１，４－ビス（４－アミノフェノキシ）ベンゼン、ベンジジン、４，４”－ジアミノ－ｐ－テルフェニル、３，３”－ジアミノ－ｐ－テルフェニル、ビス（ｐ－アミノシクロヘキシル）メテン、ビス（ｐ－β－アミノ－ｔ－ブチルフェニル）エーテル、ビス（ｐ－β－メチル－δ－アミノペンチル）ベンゼン、ｐ－ビス（２－メチル－４－アミノペンチル）ベンゼン、ｐ－ビス（１，１－ジメチル－５－アミノペンチル）ベンゼン、１，５－ジアミノナフタレン、２，６－ジアミノナフタレン、２，４－ビス（β－アミノ－ｔ－ブチル）トルエン、２，４－ジアミノトルエン、ｍ－キシレン－２，５－ジアミン、ｐ－キシレン－２，５－ジアミン、ｍ－キシリレンジアミン、ｐ－キシリレンジアミン等が挙げられる。 Examples of rigid aromatic diamines include 4,4′-diaminobenzanilide, 4,4′-diamino-2,2′-ditrifluoromethylbiphenyl, and 2,2′-di (p-aminophenyl)- 5,5'-bisbenzoxazole, 2,2'-di (p-aminophenyl) -6,6'-bisbenzoxazole, 2,2'-di (p-aminophenyl) -5,5'-bis Benzimidazole, 3,6- (4-aminophenyl) pyridazine, 4,4'-diaminobenzanilide, p-phenylenediamine (PPDA), 4,4'-diaminobiphenyl, m-phenylenediamine, 1-isopropyl-2 , 4-phenylenediamine, p-phenylenediamine, 4,4′-diaminodiphenyl sulfide, 3,3′-diaminodiphenyl sulfide, , 4′-diaminodiphenyl sulfone, 3,3′-diaminodiphenyl sulfone, 4,4′-diaminodiphenyl ether, 3,3′-diaminodiphenyl ether, 1,4-bis (4-aminophenoxy) benzene, benzidine, 4, 4 ″ -diamino-p-terphenyl, 3,3 ″ -diamino-p-terphenyl, bis (p-aminocyclohexyl) methene, bis (p-β-amino-t-butylphenyl) ether, bis (p- β-methyl-δ-aminopentyl) benzene, p-bis (2-methyl-4-aminopentyl) benzene, p-bis (1,1-dimethyl-5-aminopentyl) benzene, 1,5-diaminonaphthalene, 2,6-diaminonaphthalene, 2,4-bis (β-amino-t-butyl) toluene, 2,4-diaminotoluene, Examples thereof include m-xylene-2,5-diamine, p-xylene-2,5-diamine, m-xylylenediamine, p-xylylenediamine and the like.
　これらの中でも、２，２’－ジ（ｐ－アミノフェニル）－５，５’－ビスベンゾオキサゾール（略称＝ＮＰＮ）、２，２’－ジ（ｐ－アミノフェニル）－６，６’－ビスベンゾオキサゾール（略称＝ＯＰＯ）、２，２’－ジ（ｐ－アミノフェニル）－５，５’－ビスベンズイミダゾール、３，６－（ｐ－アミノフェニル）ピリダジン（略称＝ＤＡＰＰＺ）、４，４’－ジアミノベンズアニリド（略称＝ＤＡＢＡ）が好ましい。 Among these, 2,2′-di (p-aminophenyl) -5,5′-bisbenzoxazole (abbreviation = NPN), 2,2′-di (p-aminophenyl) -6,6′-bis Benzoxazole (abbreviation = OPO), 2,2′-di (p-aminophenyl) -5,5′-bisbenzimidazole, 3,6- (p-aminophenyl) pyridazine (abbreviation = DAPPZ), 4,4 '-Diaminobenzanilide (abbreviation = DABA) is preferred.
　熱膨脹率を制御するために用いられる、柔軟構造の芳香族テトラカルボン酸又はその酸無水物としては、例えば、３，３’，４，４’－ベンゾフェノンテトラカルボン酸二無水物（ＢＴＤＡ）等の２つ以上の芳香族環が、カルボニル基（＞Ｃ＝Ｏ）や酸素原子（－Ｏ－）により結合した構造を有する芳香族テトラカルボン酸等が挙げられる。 Examples of the flexible structure aromatic tetracarboxylic acid or acid anhydride used for controlling the thermal expansion coefficient include 3,3 ′, 4,4′-benzophenone tetracarboxylic dianhydride (BTDA). An aromatic tetracarboxylic acid having a structure in which two or more aromatic rings are bonded by a carbonyl group (> C═O) or an oxygen atom (—O—) can be used.
　柔軟構造ジアミンとしては、例えば、２，５－ビス（ｐ－アミノベンゾイル）チオフェン）等の主鎖のヘテロ環に結合する置換基の結合位置がオルト位やメタ位となる構造を含有するジアミン；オキシジアニリン等の主鎖にエーテル構造を含有するジアミン；１，３－ジアミノプロピル－１，１，３，３－テトラメチルジシロキサン等の主鎖にシロキサン構造を有するジアミン等が挙げられる。
　そのほかの柔軟構造ジアミンの具体例としては、４，４’－ジアミノジフェニルプロパン、３，３’－ジアミノジフェニルプロパン、４，４’－ジアミノジフェニルエタン、３，３’－ジアミノジフェニルエタン、４，４’－ジアミノジフェニルメタン、及び３，３’－ジアミノジフェニルメタンなどが挙げられる。 Examples of the flexible structure diamine include a diamine having a structure in which the bonding position of the substituent bonded to the main chain heterocycle such as 2,5-bis (p-aminobenzoyl) thiophene) is an ortho position or a meta position; Examples thereof include diamines having an ether structure in the main chain such as oxydianiline; diamines having a siloxane structure in the main chain such as 1,3-diaminopropyl-1,1,3,3-tetramethyldisiloxane.
Specific examples of other flexible structure diamines include 4,4′-diaminodiphenylpropane, 3,3′-diaminodiphenylpropane, 4,4′-diaminodiphenylethane, 3,3′-diaminodiphenylethane, 4,4 Examples include '-diaminodiphenylmethane and 3,3'-diaminodiphenylmethane.
　また、第１絶縁樹脂層２０を構成する絶縁性樹脂のガラス転移温度が３００℃以上であり、第２絶縁樹脂層２１を構成する絶縁性樹脂のガラス転移温度が２４０℃以上である樹脂であることが好ましい。このような絶縁性樹脂を使用することで、耐熱性に優れる半導体装置を得ることができる。 Further, the insulating resin constituting the first insulating resin layer 20 has a glass transition temperature of 300 ° C. or higher, and the insulating resin constituting the second insulating resin layer 21 has a glass transition temperature of 240 ° C. or higher. It is preferable. By using such an insulating resin, a semiconductor device having excellent heat resistance can be obtained.
　第１絶縁樹脂層や第２絶縁樹脂層を形成する際に用いられるポリイミド樹脂の製造例を示す。
１．シリコン上の熱膨脹率に合わせたポリイミド樹脂の合成
　反応器に、２，２’－ジ（ｐ－アミノフェニル）－６，６’－ビスベンゾオキサゾール２７．２８ｇ（０．０６５２モル）、１，３－ジアミノプロピル－１，１，３，３－テトラメチルジシロキサン０．５ｇ（０．００２モル）、並びに溶剤として、Ｎ，Ｎ－ジメチルアセトアミド１００ｇ、及びＮ－メチル－２－ピロリドン１００ｇを投入し、混合溶液とした。この溶液に、氷冷攪拌下、３，３’－４，４’－ビフェニルテトラカルボン酸二無水物２０．６ｇ（０．０７モル）を粉体のまま加え、氷冷下で２時間攪拌した。さらに室温で２時間攪拌した後、５－アミノテトラゾール（０．００５６モル）を加え、室温で２４時間攪拌してポリアミド酸ワニスを得た。このワニスをシリコン基板上に塗工後、最終キュア温度４００℃、１時間で製膜した膜の熱膨脹率は４．５ｐｐｍ／℃、ガラス転移温度（Ｔｇ）は４００℃以上であった。
　この膜はシリコン基板と強い密着性を示すことから、シリコン半導体基板を用いる場合、この樹脂は第１絶縁樹脂層の形成用樹脂として特に有用である。 The manufacture example of the polyimide resin used when forming a 1st insulating resin layer and a 2nd insulating resin layer is shown.
1. Synthesis of polyimide resin matched to thermal expansion coefficient on silicon A reactor was charged with 27.28 g (0.0652 mol) of 2,2′-di (p-aminophenyl) -6,6′-bisbenzoxazole, 1,3 -Diaminopropyl-1,1,3,3-tetramethyldisiloxane 0.5 g (0.002 mol) and N, N-dimethylacetamide 100 g and N-methyl-2-pyrrolidone 100 g as the solvent A mixed solution was obtained. To this solution, 20.6 g (0.07 mol) of 3,3′-4,4′-biphenyltetracarboxylic dianhydride was added in powder form with stirring under ice cooling, and the mixture was stirred under ice cooling for 2 hours. . After further stirring at room temperature for 2 hours, 5-aminotetrazole (0.0056 mol) was added, and the mixture was stirred at room temperature for 24 hours to obtain a polyamic acid varnish. After coating this varnish on a silicon substrate, the film was formed at a final curing temperature of 400 ° C. for 1 hour, the coefficient of thermal expansion was 4.5 ppm / ° C., and the glass transition temperature (Tg) was 400 ° C. or higher.
Since this film shows strong adhesion to the silicon substrate, this resin is particularly useful as a resin for forming the first insulating resin layer when a silicon semiconductor substrate is used.
２．放熱基板（銅基板）と熱膨脹率を合わせたポリイミド樹脂の合成
　反応器に、２，２’－ジ（ｐ－アミノフェニル）－６，６’－ビスベンゾオキサゾール２０．２５ｇ（０．０４８モル）、２，５－ビス（４－アミノベンゾイル）チオフェン６．０６ｇ（０．０１８８モル）、並びに溶剤として、Ｎ，Ｎ－ジメチルアセトアミド１００ｇ、及びＮ－メチル－２－ピロリドン１００ｇを投入し、混合溶液とした。この溶液に、氷冷攪拌下、３，３’－４，４’－ビフェニルテトラカルボン酸二無水物２０．６ｇ（０．０７モル）を粉体のまま加え、氷冷下で２時間攪拌した。さらに室温で２時間攪拌した後、５－アミノテトラゾール０．４７６ｇ（０．００５６モル）を加え、室温で２４時間攪拌してポリアミド酸ワニスを得た。このワニスを銅基板上に塗工後、最終キュア温度３５０℃、１時間で製膜した膜の熱膨脹率は１４．７ｐｐｍ／℃、ガラス転移温度（Ｔｇ）は３５０℃以上であった。この膜は放熱基板（銅基板）と強い密着性を示すことから、後述するパワー半導体モジュール１００Ｂ、１００Ｃ、１００Ｅ等において、この樹脂は第２絶縁樹脂層の形成用樹脂として有用である。 2. Synthesis of polyimide resin combining heat dissipation substrate (copper substrate) and coefficient of thermal expansion In a reactor, 20.25 g (0.048 mol) of 2,2'-di (p-aminophenyl) -6,6'-bisbenzoxazole , 2,5-bis (4-aminobenzoyl) thiophene (6.06 g, 0.0188 mol) and N, N-dimethylacetamide (100 g) and N-methyl-2-pyrrolidone (100 g) as a solvent It was. To this solution, 20.6 g (0.07 mol) of 3,3′-4,4′-biphenyltetracarboxylic dianhydride was added in powder form with stirring under ice cooling, and the mixture was stirred under ice cooling for 2 hours. . Further, after stirring at room temperature for 2 hours, 0.476 g (0.0056 mol) of 5-aminotetrazole was added and stirred at room temperature for 24 hours to obtain a polyamic acid varnish. After coating this varnish on a copper substrate, the film was formed at a final curing temperature of 350 ° C. for 1 hour, the thermal expansion coefficient was 14.7 ppm / ° C., and the glass transition temperature (Tg) was 350 ° C. or higher. Since this film exhibits strong adhesion to the heat dissipation substrate (copper substrate), this resin is useful as a resin for forming the second insulating resin layer in the power semiconductor modules 100B, 100C, 100E and the like described later.
３．放熱基板（銅基板）と熱膨脹率を合わせたポリイミド樹脂の合成
　反応器に、２，２’－ジ（ｐ－アミノフェニル）－６，６’－ビスベンゾオキサゾール２５．８７ｇ（０．０６１８モル）、２，５－ビス（４－アミノベンゾイル）チオフェン０．８６６ｇ（０．００２７モル）、並びに溶剤として、Ｎ，Ｎ－ジメチルアセトアミド１００ｇ、及びＮ－メチル－２－ピロリドン１００ｇを投入し、混合溶液とした。この溶液に、氷冷攪拌下、ピロメリット酸二無水物１５．３ｇ（０．０７モル）を粉体のまま加え、氷冷下で２時間攪拌した。さらに室温で２時間攪拌した後、５－アミノテトラゾール０．４７６（０．００５６モル）を加え、室温下２４時間攪拌してポリアミド酸ワニスを得た。このワニスを銅基板上に塗工後、最終キュア温度３５０℃、１時間で製膜した膜の熱膨脹率は８．２ｐｐｍ／℃、ガラス転移温度（Ｔｇ）は３５０℃以上であった。この膜は銅基板と強い密着性を示すことから、後述するパワー半導体モジュール１００Ｂ、１００Ｃ、１００Ｅ等において、この樹脂は第２絶縁樹脂層の形成用樹脂として有用である。 3. Synthesis of polyimide resin combining heat dissipation substrate (copper substrate) and thermal expansion rate In a reactor, 25.87 g (0.0618 mol) of 2,2′-di (p-aminophenyl) -6,6′-bisbenzoxazole , 2,5-bis (4-aminobenzoyl) thiophene 0.866 g (0.0027 mol) and N, N-dimethylacetamide 100 g and N-methyl-2-pyrrolidone 100 g as a solvent It was. To this solution, 15.3 g (0.07 mol) of pyromellitic dianhydride was added in powder form with stirring under ice cooling, and the mixture was stirred under ice cooling for 2 hours. Furthermore, after stirring at room temperature for 2 hours, 5-aminotetrazole 0.476 (0.0056 mol) was added and stirred at room temperature for 24 hours to obtain a polyamic acid varnish. After coating this varnish on a copper substrate, the film was formed at a final curing temperature of 350 ° C. for 1 hour, the thermal expansion coefficient was 8.2 ppm / ° C., and the glass transition temperature (Tg) was 350 ° C. or higher. Since this film exhibits strong adhesion to the copper substrate, this resin is useful as a resin for forming the second insulating resin layer in power semiconductor modules 100B, 100C, 100E and the like described later.
　上記パワー半導体１００Ａで説明した、半導体チップ、半導体基板、第１絶縁樹脂層、第２絶縁樹脂層等については、後述するパワー半導体モジュール１００Ｂ、１００Ｃ、１００Ｄ、及び１００Ｅについても同様である。 The semiconductor chip, the semiconductor substrate, the first insulating resin layer, the second insulating resin layer, and the like described in the power semiconductor 100A are the same for the power semiconductor modules 100B, 100C, 100D, and 100E described later.
　本発明の半導体装置のうち、半導体チップが２個以上実装されたパワー半導体モジュールの一例を図２に示す。図２中、（ａ）はパワー半導体モジュール１００Ｂを上から見た模式図であり、（ｂ）は、（ａ）におけるＸ－Ｙの断面を横から見た模式図である。 FIG. 2 shows an example of a power semiconductor module in which two or more semiconductor chips are mounted in the semiconductor device of the present invention. 2A is a schematic view of the power semiconductor module 100B viewed from above, and FIG. 2B is a schematic view of the XY cross section of FIG. 2A viewed from the side.
　図２に示すパワー半導体モジュール１００Ｂは、放熱基板１４に、３つのパワー半導体チップが、それぞれの裏面電極３２で放熱基板１４の配線メタル部位（図示を省略）と金属接合された構造を有している。また、パワー半導体チップは、半導体基板２００、表面第１電極３５、裏面電極３２を有し、それらが第１絶縁樹脂層により封止されており、表面第１電極３５が、第１絶縁樹脂層中に形成された第１貫通ビア３４を介して、表面第２電極３６と接続されている。 A power semiconductor module 100B shown in FIG. 2 has a structure in which three power semiconductor chips are metal-bonded to a wiring metal portion (not shown) of the heat dissipation board 14 at each back electrode 32 on the heat dissipation board 14. Yes. Further, the power semiconductor chip has a semiconductor substrate 200, a front surface first electrode 35, and a back surface electrode 32, which are sealed with a first insulating resin layer, and the front surface first electrode 35 has a first insulating resin layer. It is connected to the surface second electrode 36 through a first through via 34 formed therein.
　このパワー半導体モジュール１００Ｂにおいては、放熱基板１４の面に対して３つの素子を封止した第２絶縁樹脂層２１上部までの厚みが均一になることが好ましい。この結果、表面第１電極と表面第２電極は平行になる。この形状を達成する方法としては、後述するように切削法が優れている。 In the power semiconductor module 100B, it is preferable that the thickness up to the upper part of the second insulating resin layer 21 in which the three elements are sealed with respect to the surface of the heat dissipation substrate 14 is uniform. As a result, the surface first electrode and the surface second electrode become parallel. As a method for achieving this shape, a cutting method is excellent as will be described later.
　下部熱拡散伝導基板等の放熱機構を有するパワー半導体モジュールの一例を示す模式図を図３に示す。
　図３に示すパワー半導体モジュール１００Ｃは、放熱基板１４が下部熱拡散伝導基板１５に接合された構造を有している。従って、半導体チップで発生した熱は、放熱基板１４の下部から効率よく放熱される。 A schematic diagram showing an example of a power semiconductor module having a heat dissipation mechanism such as a lower thermal diffusion conductive substrate is shown in FIG.
The power semiconductor module 100 </ b> C shown in FIG. 3 has a structure in which the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15. Therefore, the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat dissipation substrate 14.
　下部熱拡散伝導基板及び上部放熱シート等の放熱機構を有するパワー半導体モジュールの一例の模式図を図４に示す。
　図４に示すパワー半導体モジュール１００Ｄは、放熱基板１４が下部熱拡散伝導基板１５に接合され、表面第２電極引き出し配線３８と接合され、該表面第２電極引き出し配線３８と表面第２電極とが金属接合された構造を有している。
　図４に示すパワー半導体モジュール１００Ｄにおいては、半導体チップで発生した熱は、放熱基板１４の下部から効率よく放熱される。加えて、半導体チップで発生した熱が、パワー半導体モジュール１００Ｄの上部からも効率よく放熱される。 FIG. 4 shows a schematic diagram of an example of a power semiconductor module having a heat dissipation mechanism such as a lower heat diffusion conductive substrate and an upper heat dissipation sheet.
In the power semiconductor module 100D shown in FIG. 4, the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15, and is bonded to the surface second electrode lead-out wiring 38. The surface second electrode lead-out wiring 38 and the surface second electrode are connected to each other. It has a metal bonded structure.
In the power semiconductor module 100 </ b> D shown in FIG. 4, the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat dissipation substrate 14. In addition, the heat generated in the semiconductor chip is efficiently radiated from the upper part of the power semiconductor module 100D.
　下部熱拡散伝導基板及び上部放熱シート等の放熱機構を有するパワー半導体モジュールの別の例の模式図を図５に示す。
　図５に示すパワー半導体モジュール１００Ｅは、（ｉ）放熱基板１４が下部熱拡散伝導基板１５に接合され、さらに、上部放熱シート１６が表面第２電極引き出し配線３８と接合され、（ｉｉ）該表面第２電極引き出し配線３８は表面第２電極と金属接合され、さらに、（ｉｉｉ）裏面電極３２と接続されている放熱基板上電極１７を放熱基板１４の表面に設け、この放熱基板上電極１７と表面第２電極３７とは第２貫通ビア３９によって接続され、放熱機能を有するリード電極１８が表面第２電極３７と金属接合された構造を有している。 FIG. 5 shows a schematic diagram of another example of a power semiconductor module having a heat dissipation mechanism such as a lower heat diffusion conductive substrate and an upper heat dissipation sheet.
In the power semiconductor module 100E shown in FIG. 5, (i) the heat dissipation substrate 14 is bonded to the lower thermal diffusion conductive substrate 15, and the upper heat dissipation sheet 16 is bonded to the surface second electrode lead-out wiring 38; The second electrode lead-out wiring 38 is metal-bonded to the front surface second electrode, and (iii) the heat dissipation substrate upper electrode 17 connected to the back electrode 32 is provided on the surface of the heat dissipation substrate 14. The surface second electrode 37 is connected by a second through via 39 and has a structure in which the lead electrode 18 having a heat dissipation function is metal-bonded to the surface second electrode 37.
　従って、図５に示すパワー半導体モジュール１００Ｅにおいては、半導体チップで発生した熱は、放熱基板１４の下部から効率よく放熱され、上部からも効率よく放熱され、かつ、第２貫通ビア３９を用いる放熱機構が設けられているため、半導体チップから発生する熱をさらに効率よく放熱することができる。
　また、配線を集約することが可能となり、半導体装置の薄型化、小型化が達成され、上部放熱シート１６の取り付けも有利になる。 Therefore, in the power semiconductor module 100E shown in FIG. 5, the heat generated in the semiconductor chip is efficiently radiated from the lower part of the heat radiating substrate 14, is also efficiently radiated from the upper part, and is radiated using the second through via 39. Since the mechanism is provided, the heat generated from the semiconductor chip can be radiated more efficiently.
Further, the wiring can be integrated, the semiconductor device can be made thinner and smaller, and the attachment of the upper heat dissipation sheet 16 is also advantageous.
　なお、図４、５に示すパワー半導体モジュールにおいては、放熱シート１６の代わりに、上部放熱基板を用いてもよく、放熱フィンを有する放熱部材を直結することもできる。
　また、図４、５に記載されるように上部放熱基板１６に配線を集約する方法に限定されず、例えば、下部熱拡散伝導基板１５側に配線を集約することもできる。 In the power semiconductor module shown in FIGS. 4 and 5, an upper heat dissipation board may be used instead of the heat dissipation sheet 16, and a heat dissipation member having a heat dissipation fin can be directly connected.
4 and 5, the method is not limited to the method of consolidating the wirings on the upper heat dissipation substrate 16. For example, the wirings can be consolidated on the lower thermal diffusion conductive substrate 15 side.
　本発明の半導体装置は、図１～５に示す半導体装置に限定されず、本発明の主旨を逸脱しない範囲で、半導体基板の種類、表面第１電極、裏面電極、絶縁樹脂層、表面第２電極、貫通ビアの形状や配置などを自由に変更することができる。 The semiconductor device of the present invention is not limited to the semiconductor device shown in FIGS. 1 to 5, and the type of the semiconductor substrate, the first surface electrode, the back surface electrode, the insulating resin layer, the second surface surface are within the scope not departing from the gist of the present invention. The shape and arrangement of electrodes and through vias can be freely changed.
　本発明の半導体装置は、半導体チップ全体が絶縁性及び耐熱性に優れる第１絶縁樹脂及び第２絶縁樹脂で封止されてなる。したがって、本発明の半導体装置は水分等から半導体チップが保護され、素子劣化が生じにくい。
　また、本発明の半導体装置は、半導体基板や放熱基板と封止樹脂の熱膨脹率を制御することができる。従って、半導体装置の製造時や使用時において、封止界面の熱応力差による界面応力を低減でき、半導体装置製造歩留まり、製品信頼性が大幅に向上する。 In the semiconductor device of the present invention, the entire semiconductor chip is sealed with a first insulating resin and a second insulating resin that are excellent in insulation and heat resistance. Therefore, in the semiconductor device of the present invention, the semiconductor chip is protected from moisture and the like, and element deterioration is unlikely to occur.
Further, the semiconductor device of the present invention can control the thermal expansion rate of the semiconductor substrate, the heat dissipation substrate, and the sealing resin. Therefore, the interface stress due to the thermal stress difference at the sealing interface can be reduced during the manufacture and use of the semiconductor device, and the semiconductor device manufacturing yield and product reliability are greatly improved.
２）半導体装置の製造方法
　本発明の半導体装置の製造方法は、以下の工程１～４をこの順で有することを特徴とする。
（工程１）半導体基板の表面側に形成された表面第１電極と、前記半導体基板の裏面側に形成された裏面電極とを備える半導体チップと、前記表面第１電極上に形成された１又は２以上の第１貫通ビア形成用金属ポストと、前記半導体チップの表面部及び前記第１貫通ビア形成用金属ポストを封止する第１絶縁樹脂層とを有する、１又は２以上の半導体チップ封止体を、その裏面電極で放熱基板と金属接合する工程
（工程２）放熱基板と金属接合された前記半導体チップ封止体全体を覆うように、前記放熱基板表面に第２絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第２絶縁樹脂層を形成する工程
（工程３）前記第１絶縁樹脂層及び前記第２絶縁樹脂層表面を薄化処理して、第１絶縁樹脂層と第２絶縁樹脂層を平坦化し、貫通ビア形成用金属ポストの上面を露出させる工程
（工程４）前記第１絶縁樹脂層と前記第２絶縁樹脂層の表面上の少なくとも第１絶縁樹脂部に表面第２電極を形成する工程 2) Manufacturing Method of Semiconductor Device The manufacturing method of the semiconductor device of the present invention is characterized by having the following steps 1 to 4 in this order.
(Step 1) a semiconductor chip comprising a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate, and 1 or formed on the front surface first electrode One or more semiconductor chip seals having two or more first through via forming metal posts and a first insulating resin layer for sealing the surface portion of the semiconductor chip and the first through via forming metal posts. Step of metal-bonding the stationary body to the heat dissipation substrate with the back electrode (Step 2) For forming the second insulating resin layer on the surface of the heat dissipation substrate so as to cover the entire semiconductor chip sealing body metal-bonded to the heat dissipation substrate A step of applying a resin and heating at 300 to 450 ° C. to form a second insulating resin layer (Step 3) The first insulating resin layer and the surface of the second insulating resin layer are subjected to a thinning process to thereby form a first insulating resin layer. Flatten the resin layer and the second insulating resin layer Forming a second electrode surface on at least the first insulating resin portion on the surface of the via-forming step of exposing the upper surface of the metal posts (Step 4) the said first insulating resin layer a second insulating resin layer
　工程１で用いる半導体チップ封止体の製造方法の具体例については後述する。
　工程２において用いる第２絶縁樹脂層形成用樹脂としては、先に半導体装置の説明中で挙げたものと同様のものを使用することができる。
　工程３における薄化処理としては、例えば、切削法や研磨法が挙げられ、これらを組み合わせてもよい。
　工程４における表面第２電極を形成する方法としては、例えば、スパッタ蒸着法によって、金属膜を全面に形成した後、パターン化する方法や、あらかじめ、所定のパターンになるように金属膜を形成する方法が挙げられる。
　本発明の半導体装置の製造方法は、上述した本発明の半導体装置を製造するのに特に適している。 A specific example of the manufacturing method of the semiconductor chip sealing body used in step 1 will be described later.
As the resin for forming the second insulating resin layer used in step 2, the same resins as those described above in the description of the semiconductor device can be used.
Examples of the thinning process in step 3 include a cutting method and a polishing method, and these may be combined.
As a method of forming the surface second electrode in the step 4, for example, a metal film is formed on the entire surface by a sputtering vapor deposition method and then patterned, or a metal film is formed in advance so as to have a predetermined pattern. A method is mentioned.
The semiconductor device manufacturing method of the present invention is particularly suitable for manufacturing the above-described semiconductor device of the present invention.
　以下、本発明の製造方法を、図５に示すパワー半導体モジュール１００Ｅを製造する場合を例にとり、図６により具体的に説明する。
　図６中、図６（ａ）～図６（ｄ）が上記工程１（工程１ａ～工程１ｄ）、図６（ｅ）が工程２（工程２ａ）、図６（ｆ）が工程３(工程３ａ)、図６（ｇ）が工程４（工程４ａ）のそれぞれを説明する図である。また、図６（ｈ）は、図６（ｇ）に示す状態のものに、さらに、下部熱拡散伝導基板１５及び上部放熱シート１６を接合する工程を説明する図である。 Hereinafter, the manufacturing method of the present invention will be described in detail with reference to FIG. 6, taking as an example the case of manufacturing the power semiconductor module 100E shown in FIG.
In FIG. 6, FIGS. 6 (a) to 6 (d) are steps 1 (step 1a to step 1d), FIG. 6 (e) is step 2 (step 2a), and FIG. 6 (f) is step 3 (step). 3a) and FIG. 6 (g) are diagrams illustrating each of step 4 (step 4a). FIG. 6H is a diagram for explaining a process of joining the lower thermal diffusion conductive substrate 15 and the upper heat dissipation sheet 16 to the state shown in FIG. 6G.
　本発明の半導体装置の製造方法は、この工程に記載のものに限定されない。また、目的の半導体装置の構造に合わせて、図６に記載の工程の中から必要な工程のみを行うことで、図１～４に記載の半導体装置を製造することもできる。 The manufacturing method of the semiconductor device of the present invention is not limited to the one described in this step. Further, the semiconductor device shown in FIGS. 1 to 4 can be manufactured by performing only necessary steps from the steps shown in FIG. 6 in accordance with the structure of the target semiconductor device.
工程１ａ：図６（ａ）に示すように、放熱基板１４上にめっきレジスト２３を成膜し、パターニングすることにより、貫通ビアホール３９ａを開口する。このとき、裏面電極と接続される放熱基板上電極１７上に開口部を設けることが好ましい。 Step 1a: As shown in FIG. 6A, a plating resist 23 is formed on the heat dissipation substrate 14 and patterned to open a through via hole 39a. At this time, it is preferable to provide an opening on the heat dissipation substrate upper electrode 17 connected to the back electrode.
工程１ｂ：図６（ｂ）に示すように、前記貫通ビアホール３９ａ内をめっきにより金属を充填し、第２貫通ビア用金属ポスト３９ｂを形成する。めっきの方法は特に制限されないが、電解めっき法を用いることが好ましい。 Step 1b: As shown in FIG. 6B, the through via hole 39a is filled with metal by plating to form a second through via metal post 39b. The plating method is not particularly limited, but it is preferable to use an electrolytic plating method.
工程１ｃ：図６（ｃ）に示すように、めっき終了後、常法によりめっきレジストを除去する。なお、工程１ａ～１ｃの代わりに、金属ポスト材を放熱基板１４に金属接合することで、同様の第２貫通ビア用金属ポストを形成してもよい。 Step 1c: As shown in FIG. 6C, after the end of plating, the plating resist is removed by a conventional method. Instead of the steps 1a to 1c, the same metal post for the second through via may be formed by metal bonding the metal post material to the heat dissipation substrate 14.
工程１ｄ：図６（ｄ）に示すように、半導体チップ封止体を、その裏面電極で放熱基板１４と金属接合する。 Step 1d: As shown in FIG. 6D, the semiconductor chip sealing body is metal-bonded to the heat dissipation substrate 14 with the back electrode.
　なお、工程１ｄは、後述する工程１ｅの前であれば、工程１ｄを実施する順番は特に制限されない。例えば、工程１ａの前に、半導体チップ封止体を放熱基板に金属接合してもよい。 In addition, as long as the process 1d is before the process 1e mentioned later, the order in which the process 1d is implemented is not particularly limited. For example, the semiconductor chip sealing body may be metal-bonded to the heat dissipation substrate before step 1a.
工程２ａ：図６（ｅ）に示すように、半導体チップ封止体及び第２貫通ビア用金属ポスト３９ｂが埋め込まれるように第２絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第２絶縁樹脂層２１を形成する。 Step 2a: As shown in FIG. 6E, a second insulating resin layer forming resin is applied so that the semiconductor chip sealing body and the second through via metal post 39b are embedded, and heated at 300 to 450 ° C. Thus, the second insulating resin layer 21 is formed.
　この場合、第２絶縁樹脂層形成用樹脂を塗布し、乾燥して得られた塗膜（以下、「塗膜Ａ１」ということがある。）を３００～４５０℃に加熱する前に、前記塗膜Ａ１を、第２絶縁樹脂層形成用樹脂（第２絶縁樹脂層形成用樹脂の有機溶媒溶液）に用いられている有機溶媒（以下、「溶媒Ａ１」ということがある。」と親和性のある溶媒（以下、「溶媒Ｂ１」ということがある。）中に、１０～４０℃で１～６０分間浸漬させる工程をさらに設けることも好ましい。 In this case, before the coating film obtained by applying and drying the second insulating resin layer forming resin (hereinafter sometimes referred to as “coating film A1”) is heated to 300 to 450 ° C., the above coating is applied. The film A1 is compatible with an organic solvent (hereinafter, also referred to as “solvent A1”) used in the second insulating resin layer forming resin (an organic solvent solution of the second insulating resin layer forming resin). It is also preferable to further provide a step of immersing in a certain solvent (hereinafter sometimes referred to as “solvent B1”) at 10 to 40 ° C. for 1 to 60 minutes.
　より具体的には、第２絶縁樹脂層形成用樹脂を塗布し、得られた塗膜を、溶媒の残留量が、塗膜全体に対し、通常１～４５重量％、好ましくは３～４０重量％、より好ましくは５～３５重量％となるまで、乾燥温度５０～１３０℃で１～６０分間乾燥して塗膜Ａ１を得た後、得られた塗膜Ａ１を、溶媒Ｂ１中に、１０～４０℃で１～６０分間浸漬させる工程をさらに設ける。これにより、前記塗膜Ａ１から溶媒Ａ１を効率よく除去することができ、結果として、放熱基板１４との密着性に優れる第２絶縁樹脂層２１を形成することができる。 More specifically, the resin for forming the second insulating resin layer is applied, and the resulting coating film has a residual solvent amount of usually 1 to 45% by weight, preferably 3 to 40% by weight, based on the entire coating film. %, More preferably 5 to 35% by weight, after drying at a drying temperature of 50 to 130 ° C. for 1 to 60 minutes to obtain a coating film A1, the obtained coating film A1 is added to 10% in the solvent B1. A step of immersing at ˜40 ° C. for 1 to 60 minutes is further provided. Thereby, the solvent A1 can be efficiently removed from the coating film A1, and as a result, the second insulating resin layer 21 having excellent adhesion with the heat dissipation substrate 14 can be formed.
　溶媒Ａ１としては、第２絶縁樹脂層形成用樹脂がポリイミド前駆体である場合、通常、Ｎ－メチルピロリドン、Ｎ，Ｎ－ジメチルホルムアミド、Ｎ，Ｎ－ジメチルアセトアミド、テトラメチル尿素、ヘキサメチルリン酸トリアミド等のアミド系溶媒；又は、ジメチルスルホキシド、スルホラン等の含硫黄系溶媒；が用いられる。従って、用いる溶媒Ｂ１としては、アミド系溶媒及び含硫黄系溶媒以外の極性溶媒が好ましい。例えば、水；メタノール、エタノール、プロパノール等のアルコール系溶媒；アセトン、メチルエチルケトン、ジエチルケトン等のケトン系溶媒；及びこれらの溶媒の二種以上からなる混合溶媒；等が挙げられる。 As the solvent A1, when the resin for forming the second insulating resin layer is a polyimide precursor, usually N-methylpyrrolidone, N, N-dimethylformamide, N, N-dimethylacetamide, tetramethylurea, hexamethylphosphoric acid Amide solvents such as triamide; or sulfur-containing solvents such as dimethyl sulfoxide and sulfolane are used. Accordingly, the solvent B1 used is preferably a polar solvent other than the amide solvent and the sulfur-containing solvent. For example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
　また、第２絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃に１～１２０分間加熱して第２絶縁樹脂層２１を形成する場合、前記塗膜Ａ１を１３０～２５０℃に加熱した後、一端、０～１２０℃、好ましくは１０～１００℃、より好ましくは２０～１００℃に冷却し、再度２５０～４５０℃に加熱して、第２絶縁樹脂層２１を形成することも、放熱基板１４との密着性に優れる第２絶縁樹脂層を形成する上で好ましい。この場合、冷却する方法は、所定温度まで下げることができる方法であればよく、冷却時間は適宜決定することができる。例えば、放冷によって冷却することができる。 Further, when the second insulating resin layer forming resin is applied and heated to 300 to 450 ° C. for 1 to 120 minutes to form the second insulating resin layer 21, the coating film A1 is heated to 130 to 250 ° C. Further, the second insulating resin layer 21 can be formed by cooling to one end, 0 to 120 ° C., preferably 10 to 100 ° C., more preferably 20 to 100 ° C., and again heating to 250 to 450 ° C. 14 is preferable for forming a second insulating resin layer having excellent adhesion to the resin. In this case, the cooling method may be any method that can lower the temperature to a predetermined temperature, and the cooling time can be appropriately determined. For example, it can cool by standing_to_cool.
　第２絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃に加熱して第２絶縁樹脂層２１を形成する場合、このキュア温度でめっき充填物も同時にアニールされる。従って、第２貫通ビア用金属ポスト３９ｂと表面第１電極との密着性向上、第２貫通ビアの強度向上、第２貫通ビアの電気伝導性向上、第２貫通ビアと第１絶縁樹脂層との密着性向上等が達成される。 When the second insulating resin layer forming resin is applied and heated to 300 to 450 ° C. to form the second insulating resin layer 21, the plating filler is also annealed simultaneously at this curing temperature. Accordingly, the adhesion between the second through via metal post 39b and the surface first electrode, the strength of the second through via, the electrical conductivity of the second through via, the second through via and the first insulating resin layer are improved. The improvement of the adhesion is achieved.
工程３ａ：図６（ｆ）に示すように、放熱基板１４を台座(図示を省略)に固定して、表面の樹脂封止部分を切削し、第１貫通ビア用金属ポスト３９ｂ及び第２貫通ビア用金属ポスト３９ｂの上面を露出させる。切削は、公知の切削加工機（例えば、ＤｉＳＣＯ社製、サーフェイスブレーナーＤＦＳ８９２０等）を用いて行うことができる。 Step 3a: As shown in FIG. 6 (f), the heat dissipation substrate 14 is fixed to a pedestal (not shown), the resin sealing portion on the surface is cut, and the first through via metal post 39b and the second penetration The upper surface of the via metal post 39b is exposed. The cutting can be performed using a known cutting machine (for example, a surface brainer DFS8920 manufactured by DiSCO).
工程４ａ：図６（ｇ）に示すように、切削面に金属膜を形成し、パターン化することで表面第２電極３６、３７を形成する。金属膜の形成方法は特に制限されない。例えば、スパッタ蒸着法によって、金属膜を形成することができる。 Step 4a: As shown in FIG. 6G, a metal film is formed on the cut surface and patterned to form the surface second electrodes 36 and 37. The method for forming the metal film is not particularly limited. For example, a metal film can be formed by sputtering deposition.
　また、図６（ｈ）に示すように、工程４ａに引き続いて、得られた半導体装置において、その上下両面にそれぞれ熱拡散基板１５、放熱シート１６を接合することができる。
　この場合、図示を省略しているが、上部放熱シート１６は表面第２電極引き出し配線と接合され、該表面第２電極引き出し配線は表面第２電極と金属接合される。この様な構造とすることにより、半導体チップで発生した熱はパワー半導体モジュールの上部からも効率よく放熱される。
　以上のようにして、図５に示すパワー半導体モジュール１００Ｅを製造することができる。 Moreover, as shown in FIG.6 (h), following the process 4a, in the obtained semiconductor device, the thermal diffusion board | substrate 15 and the thermal radiation sheet | seat 16 can be joined to the upper and lower surfaces, respectively.
In this case, although not shown, the upper heat radiation sheet 16 is bonded to the surface second electrode lead wiring, and the surface second electrode lead wiring is metal-bonded to the surface second electrode. With this structure, the heat generated in the semiconductor chip is efficiently radiated from the upper part of the power semiconductor module.
As described above, the power semiconductor module 100E shown in FIG. 5 can be manufactured.
　次に、本発明に好ましく用いられる半導体チップの製造工程の一例を図７（ａ）～（ｉ）に示す。以下、順に説明する。
図７（ａ）：半導体基板２００上に、表面第１電極（図示を省略）を有する半導体素子１１を作製する。半導体基板としては、シリコン基板の他に、シリコンカーバイド基板やガリウムナイトライド基板を使用することができる。 Next, an example of the manufacturing process of the semiconductor chip preferably used in the present invention is shown in FIGS. Hereinafter, it demonstrates in order.
FIG. 7A: A semiconductor element 11 having a first surface electrode (not shown) is fabricated on a semiconductor substrate 200. FIG. As the semiconductor substrate, a silicon carbide substrate or a gallium nitride substrate can be used in addition to the silicon substrate.
図７（ｂ）：半導体素子１１上にめっきレジスト２３を成膜する。塗工膜厚はめっき厚みを考慮して決定できる。通常はめっき厚みが３０～６０μｍになるようにすると良い。また、めっきレジスト２３を成膜する代わりに、めっき対応感光性シートを用いてもよい。 FIG. 7B: A plating resist 23 is formed on the semiconductor element 11. The coating film thickness can be determined in consideration of the plating thickness. Usually, the plating thickness is preferably 30 to 60 μm. Further, instead of forming the plating resist 23, a photosensitive sheet for plating may be used.
図７（ｃ）：めっきレジスト２３をパターニングすることにより必要な部位に貫通ビアホール３４ａを開口する。このとき、表面第１電極上を開口することが好ましい。
図７（ｄ）：次いで、得られた貫通ビアホール３４ａ内をめっき法により金属で充填して、第１貫通ビア用金属ポスト３４ｂを形成する。
　めっき方法は特に制限されないが、電解めっき法を用いることが好ましい。
図７（ｅ）：めっき終了後、常法によりめっきレジストを剥離する。 FIG. 7 (c): By patterning the plating resist 23, through via holes 34a are opened at necessary portions. At this time, it is preferable to open on the surface first electrode.
FIG. 7D: Next, the obtained through via hole 34a is filled with a metal by a plating method to form a first through via metal post 34b.
The plating method is not particularly limited, but it is preferable to use an electrolytic plating method.
FIG. 7E: After the plating is finished, the plating resist is peeled off by a conventional method.
図７（ｆ）：半導体基板２００上全体に第１貫通ビア用金属ポスト３４ｂが埋め込まれるように第１絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第１絶縁樹脂層２０を形成し、半導体素子１１と前記金属ポスト３４ｂを封止する。 FIG. 7F: First insulating resin layer forming resin is applied so that the first through via metal post 34b is embedded on the entire semiconductor substrate 200, and heated at 300 to 450 ° C. to form the first insulating resin layer. 20 is formed, and the semiconductor element 11 and the metal post 34b are sealed.
　この場合、第１絶縁樹脂層形成用樹脂を塗布し、乾燥して得られた塗膜（以下、「塗膜Ａ２」ということがある。）を３００～４５０℃に加熱する前に、前記塗膜Ａ２を、第１絶縁樹脂層形成用樹脂（第１絶縁樹脂層形成用樹脂の有機溶媒溶液）に用いられている有機溶媒（以下、「溶媒Ａ２」ということがある。」と親和性のある溶媒（以下、「溶媒Ｂ２」ということがある。）中に、１０～４０℃で、１～６０分間浸漬させる工程をさらに設けることも好ましい。 In this case, before the coating film obtained by applying and drying the first insulating resin layer forming resin (hereinafter sometimes referred to as “coating film A2”) is heated to 300 to 450 ° C., the above coating is applied. The film A2 has an affinity with an organic solvent (hereinafter sometimes referred to as “solvent A2”) used in the first insulating resin layer forming resin (the organic solvent solution of the first insulating resin layer forming resin). It is also preferable to further provide a step of immersing in a solvent (hereinafter sometimes referred to as “solvent B2”) at 10 to 40 ° C. for 1 to 60 minutes.
　より具体的には、第１絶縁樹脂層形成用樹脂を塗布し、得られた塗膜を、溶媒の残留量が、塗膜全体に対し、通常１～４５重量％、好ましくは３～４０重量％、より好ましくは５～３５重量％となるまで、乾燥温度５０～１３０℃で１～６０分間乾燥して塗膜Ａ２を得た後、得られた塗膜Ａ２を、溶媒Ｂ２中に、１０～４０℃で１～６０分間浸漬させる。この工程を設ける。これにより、前記塗膜Ａ２から有機溶媒を効率よく除去することができ、結果として、半導体基板２００との密着性に優れる第１絶縁樹脂層２１を形成することができる。 More specifically, the first insulating resin layer forming resin is applied, and the resulting coating film has a residual solvent amount of usually 1 to 45% by weight, preferably 3 to 40% by weight, based on the entire coating film. %, More preferably 5 to 35% by weight, after drying at a drying temperature of 50 to 130 ° C. for 1 to 60 minutes to obtain a coating film A2, the resulting coating film A2 is added to 10% in solvent B2. Soak for 1 to 60 minutes at ˜40 ° C. This step is provided. Thereby, the organic solvent can be efficiently removed from the coating film A2, and as a result, the first insulating resin layer 21 having excellent adhesion to the semiconductor substrate 200 can be formed.
　溶媒Ａ２としては、第１絶縁樹脂層形成用樹脂がポリイミド前駆体である場合、通常、Ｎ－メチルピロリドン、Ｎ，Ｎ－ジメチルホルムアミド、Ｎ，Ｎ－ジメチルアセトアミド、テトラメチル尿素、ヘキサメチルリン酸トリアミド等のアミド系溶媒；又は、ジメチルスルホキシド、スルホラン等の含硫黄系溶媒；が用いられる。従って、用いる溶媒Ｂ２としては、アミド系溶媒及び含硫黄系溶媒以外の極性溶媒が好ましい。例えば、水；メタノール、エタノール、プロパノール等のアルコール系溶媒；アセトン、メチルエチルケトン、ジエチルケトン等のケトン系溶媒；及びこれらの溶媒の二種以上からなる混合溶媒；等が挙げられる。 As the solvent A2, when the first insulating resin layer forming resin is a polyimide precursor, usually N-methylpyrrolidone, N, N-dimethylformamide, N, N-dimethylacetamide, tetramethylurea, hexamethylphosphoric acid Amide solvents such as triamide; or sulfur-containing solvents such as dimethyl sulfoxide and sulfolane are used. Accordingly, the solvent B2 to be used is preferably a polar solvent other than the amide solvent and the sulfur-containing solvent. For example, water; alcohol solvents such as methanol, ethanol, and propanol; ketone solvents such as acetone, methyl ethyl ketone, and diethyl ketone; and a mixed solvent composed of two or more of these solvents;
　また、第１絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃に１～１２０分間加熱して第１絶縁樹脂層２０を形成する場合、前記塗膜Ａ２を１３０～２５０℃に加熱した後、一端、０～１２０℃、好ましくは１０～１００℃、より好ましくは２０～１００℃に冷却し、再度２５０～４５０℃に加熱して第１絶縁樹脂層２０を形成することも、半導体基板２００との密着性に優れる第１絶縁樹脂層を形成する上で好ましい。この場合、冷却する方法は、所定温度まで下げることができる方法であればよく、冷却時間は適宜決定することができる。例えば、放冷によって冷却することができる。 When the first insulating resin layer forming resin is applied and heated to 300 to 450 ° C. for 1 to 120 minutes to form the first insulating resin layer 20, the coating film A2 is heated to 130 to 250 ° C. The first insulating resin layer 20 may be formed by cooling to one end, 0 to 120 ° C., preferably 10 to 100 ° C., more preferably 20 to 100 ° C., and again heating to 250 to 450 ° C. It is preferable when forming the 1st insulating resin layer excellent in adhesiveness. In this case, the cooling method may be any method that can lower the temperature to a predetermined temperature, and the cooling time can be appropriately determined. For example, it can cool by standing_to_cool.
　第１絶縁樹脂層２０を塗布し、３００～４５０℃に加熱して第１絶縁樹脂層を形成するとき、このキュア温度でめっき充填物も同時にアニールされる。従って、第１貫通ビア用金属ポスト３４ｂと表面第１電極との密着性向上、第１貫通ビアの強度向上、第１貫通ビアの電気伝導性向上、第１貫通ビアと第１絶縁樹脂層との密着性向上等が達成される。 When the first insulating resin layer 20 is applied and heated to 300 to 450 ° C. to form the first insulating resin layer, the plating filler is also annealed simultaneously at this curing temperature. Therefore, the adhesion between the first through via metal post 34b and the surface first electrode, the strength of the first through via, the electrical conductivity of the first through via, the first through via and the first insulating resin layer are improved. The improvement of the adhesion is achieved.
　また、所望により、半導体基板２００側を台座(図示を省略)に固定して第１絶縁樹脂層２０の表面を薄化加工し、厚みを均一にする（図示を省略）。この工程は次の裏面加工を精度よく行うためのものであり、必須の工程ではない。また、この工程を行う場合であっても、本発明の半導体装置を製造するのであれば、この工程において、第１貫通ビア用金属ポスト３４ｂの上面を露出させるため、この工程においては第１貫通ビア用金属ポスト３４ｂの上面の露出までは必要とはされない。 If desired, the semiconductor substrate 200 side is fixed to a pedestal (not shown) and the surface of the first insulating resin layer 20 is thinned to make the thickness uniform (not shown). This step is for accurately performing the next back surface processing, and is not an essential step. Even when this step is performed, if the semiconductor device of the present invention is manufactured, the upper surface of the first through via metal post 34b is exposed in this step. It is not necessary to expose the upper surface of the via metal post 34b.
　薄化加工の加工法については特に制限されない。例えば、切削法や研磨法が挙げられ、これらを組み合わせてもよい。なかでも、切削法は加工速度に優れるため好ましい。切削法においては、公知の切削加工機（例えば、ＤｉＳＣＯ社製、サーフェイスブレーナーＤＦＳ８９２０等）を用いることができる。 薄 There are no particular restrictions on the thinning method. Examples thereof include a cutting method and a polishing method, and these may be combined. Of these, the cutting method is preferable because of its excellent processing speed. In the cutting method, a known cutting machine (for example, a surface brainer DFS8920 manufactured by DiSCO) can be used.
図７（ｇ）：上記のように第１絶縁樹脂層２０の表面処理の後、必要に応じてその表面に金属膜を全面形成する。次いで金属膜面を固定して半導体基板２００の裏面を切削、研磨して薄板化する。この工程は必須の工程ではないが、半導体基板の厚みを、好ましくは４００μｍ以下、より好ましくは３０μｍ～２００μｍに薄板化することにより、変換効率に優れた薄型の半導体装置が得ることができる。 FIG. 7G: After the surface treatment of the first insulating resin layer 20 as described above, a metal film is formed on the entire surface as necessary. Next, the metal film surface is fixed, and the back surface of the semiconductor substrate 200 is cut and polished to form a thin plate. Although this step is not an essential step, a thin semiconductor device with excellent conversion efficiency can be obtained by reducing the thickness of the semiconductor substrate to preferably 400 μm or less, more preferably 30 μm to 200 μm.
図７（ｈ）：所望により裏面研磨後、裏面電極３２を作製する。表面第２電極と裏面電極の金属膜は残留応力が均等になるように膜組成、膜厚を調整して製膜する。両面金属箔の残留応力を調製することで、半導体基板２００を薄板化した後であっても、該半導体基板２００が反ることはない。 FIG. 7 (h): The back electrode 32 is fabricated after the back surface is polished if desired. The metal film of the second electrode on the front surface and the back electrode is formed by adjusting the film composition and film thickness so that the residual stress is uniform. By adjusting the residual stress of the double-sided metal foil, the semiconductor substrate 200 does not warp even after the semiconductor substrate 200 is thinned.
図７（ｉ）：ダイシングにより、半導体チップを個別化する。個別化しても半導体基板２００に対して上限の残留応力が均等化しているので半導体チップの平坦化が維持されている。
　以上の工程で得られた半導体チップは、図２～５に記載のパワー半導体モジュールを製造するための半導体チップ封止体として好ましく用いられる。 FIG. 7I: Individual semiconductor chips are obtained by dicing. Even if individualized, since the upper limit residual stress is equalized with respect to the semiconductor substrate 200, the flatness of the semiconductor chip is maintained.
The semiconductor chip obtained by the above steps is preferably used as a semiconductor chip sealing body for manufacturing the power semiconductor module shown in FIGS.
　本発明に用いられる半導体チップの製造工程は上記のものに限定されない。例えば、図７（ａ）～（ｄ）に示す工程の代わりに、金属ポスト材をシリコン基板に金属接合することで、同様の貫通ビア用第１金属ポストを形成してもよい。
　また、図７（ｆ）に示す工程において平坦化した第１絶縁樹脂面に金属膜を形成せずに、仮固定基板等に固定することで基板の反りを抑制し、裏面基板研磨、裏面電極作製工程を行うこともできる。 The manufacturing process of the semiconductor chip used in the present invention is not limited to the above. For example, instead of the steps shown in FIGS. 7A to 7D, the same first metal post for through via may be formed by metal bonding a metal post material to a silicon substrate.
Further, the first insulating resin surface flattened in the step shown in FIG. 7 (f) is not formed with a metal film, but is fixed to a temporarily fixed substrate or the like, thereby suppressing the warpage of the substrate, polishing the back substrate, and back electrode A manufacturing process can also be performed.
　また、工程７（ｅ）において用いる第１絶縁樹脂として、感光性ポリイミドを用いることもできる。感光性ポリイミドとしては、例えば、特開２００４－２８５１２９号公報記載の低熱膨張型感光性ポリイミド等が利用できる。工程７（ｅ）において、感光性ポリイミドを用いることで、図７（ａ）～（ｃ）の方法によって貫通ビア用金属ポストを形成する代わりに、貫通ビアホールを空けた後めっき充填して、貫通ビア用金属ポストを形成することができる。
　この他に、感光性ポリイミドは図７（ｅ）の封止工程において、ダイシングラインの開口を目的として利用することができるため好ましい。
　さらに、第２表面電極が形成された後に、この電極に配線を有する絶縁性放熱シート、配線を有する絶縁性放熱基板および放熱機能を有するリード電極から選ばれる放熱用部品を金属接合する工程を設けてもよい。 Photosensitive polyimide can also be used as the first insulating resin used in step 7 (e). As the photosensitive polyimide, for example, a low thermal expansion photosensitive polyimide described in JP-A No. 2004-285129 can be used. In step 7 (e), by using photosensitive polyimide, instead of forming through via metal posts by the method of FIGS. 7 (a) to 7 (c), through via holes are formed and plated and filled. Via metal posts can be formed.
In addition, photosensitive polyimide is preferable because it can be used for the purpose of opening a dicing line in the sealing step of FIG.
Furthermore, after the second surface electrode is formed, there is provided a step of metal-joining a heat radiating component selected from an insulating heat radiating sheet having wiring on the electrode, an insulating heat radiating substrate having wiring, and a lead electrode having a heat radiating function May be.
　１１・・・半導体素子
　１２・・・半導体チップ
　１４・・・放熱基板
　１４ａ・・・銅パターン
　１４ｂ・・・セラミックス基板
　１５・・・下部熱拡散伝導基板
　１６・・・上部放熱シート
　１７・・・放熱基板上電極
　２０・・・第１絶縁樹脂層
　２１・・・第２絶縁樹脂層
　２３・・・めっきレジスト
　３２・・・裏面電極
　３４・・・第１貫通ビア
　３４ａ・・・貫通ビア
　３４ｂ・・・第１貫通ビア用金属ポスト
　３５・・・表面第１電極
　３６、３７・・・表面第２電極
　３８・・・表面第２電極引き出し配線
　３９・・・第２貫通ビア
　３９ａ・・・貫通ビアホール
　３９ｂ・・・第２貫通ビア用金属ポスト
　６０・・・ＤＢＣ絶縁基板
　６１・・・パワー半導体素子
　６２・・・外部導出端子
　６３・・・ボンディングワイヤ
　６４・・・放熱ベース
　６５・・・樹脂ケース
　６６・・・蓋
　６２・・・エミッタ電極
　６３・・・ゲート電極
　６４・・・コレクタ電極
　１００Ａ、１００Ｂ、１００Ｃ、１００Ｄ、１００Ｅ・・・パワー半導体モジュール
　２００・・・半導体基板 DESCRIPTION OF SYMBOLS 11 ... Semiconductor element 12 ... Semiconductor chip 14 ... Heat dissipation board 14a ... Copper pattern 14b ... Ceramic substrate 15 ... Lower thermal diffusion conductive substrate 16 ... Upper heat dissipation sheet 17 ... Heat dissipating substrate electrode 20 ... first insulating resin layer 21 ... second insulating resin layer 23 ... plating resist 32 ... back electrode 34 ... first through via 34a ... through via 34b ..First through via metal post 35... Surface first electrode 36, 37... Surface second electrode 38... Surface second electrode lead-out wiring 39... Second through via 39 a. Via hole 39b ... Metal post for second through via 60 ... DBC insulating substrate 61 ... Power semiconductor element 62 ... External lead-out terminal 63 ... Bonding wire 64 ... Radiation base 65 Resin case 66 ... lid 62 ... emitter electrode 63 ... gate electrode 64 ... collector electrodes 100A, 100B, 100C, 100D, 100E ··· power semiconductor module 200 ... semiconductor substrate

Claims (20)

  1. 　半導体基板の表面側に形成された表面第１電極と、前記半導体基板の裏面側に形成された裏面電極とを備える１又は２以上の半導体チップが、前記裏面電極で放熱基板と金属接合されている半導体装置であって、
    前記半導体チップの表面部を封止する第１絶縁樹脂層と、
    前記半導体チップの側面部及び放熱基板表面を封止する第２絶縁樹脂層と、
    少なくとも前記第１絶縁樹脂層上に形成された表面第２電極と、及び
    前記第１絶縁樹脂層内を貫通し、前記表面第１電極と前記表面第２電極とを接続する１又は２以上の第１貫通ビアと、
    を有することを特徴とする半導体装置。     One or two or more semiconductor chips each including a first surface electrode formed on the front surface side of the semiconductor substrate and a back electrode formed on the back surface side of the semiconductor substrate are metal-bonded to the heat dissipation substrate by the back surface electrode. A semiconductor device comprising:
    A first insulating resin layer for sealing the surface portion of the semiconductor chip;
    A second insulating resin layer for sealing the side surface portion of the semiconductor chip and the surface of the heat dissipation substrate;
    At least one surface second electrode formed on the first insulating resin layer, and one or two or more that penetrate through the first insulating resin layer and connect the surface first electrode and the surface second electrode A first through via;
    A semiconductor device comprising:
  2. 　前記放熱基板の表面積が前記半導体基板の表面積と等しいか、又はそれより大きいものであり、前記放熱基板が、前記半導体基板の裏面全体を覆うように前記裏面電極と金属接合されてなる請求項１に記載の半導体装置。 The surface area of the heat dissipation substrate is equal to or greater than the surface area of the semiconductor substrate, and the heat dissipation substrate is metal-bonded to the back electrode so as to cover the entire back surface of the semiconductor substrate. A semiconductor device according to 1.
  3. 　前記半導体チップを構成する半導体基板の厚みが４００μｍ以下である請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a thickness of a semiconductor substrate constituting the semiconductor chip is 400 μm or less.
  4. 　前記第２絶縁樹脂層内を貫通する１又は２以上の第２貫通ビアをさらに有する請求項１～３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, further comprising one or more second through vias penetrating through the second insulating resin layer.
  5. 　前記裏面電極と接続されている放熱基板上電極を前記放熱基板表面に有し、前記放熱基板上電極と前記表面第２電極が、前記第２貫通ビアにより接続されていることを特徴とする請求項４に記載の半導体装置。 The heat dissipation substrate upper electrode connected to the back electrode is provided on the surface of the heat dissipation substrate, and the heat dissipation substrate upper electrode and the surface second electrode are connected by the second through via. Item 5. The semiconductor device according to Item 4.
  6. 　前記第１絶縁樹脂層が、熱膨張率が２～２１ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂から構成され、前記第２絶縁樹脂層が、熱膨脹率が２～５０ｐｐｍ／℃の樹脂層を形成する絶縁性樹脂から構成されていることを特徴とする請求項１～５のいずれかに記載の半導体装置。 The first insulating resin layer is made of an insulating resin that forms a resin layer having a thermal expansion coefficient of 2 to 21 ppm / ° C., and the second insulating resin layer is a resin layer having a thermal expansion coefficient of 2 to 50 ppm / ° C. 6. The semiconductor device according to claim 1, comprising an insulating resin to be formed.
  7. 　前記第１絶縁樹脂層が、ガラス転移温度３００℃以上である絶縁性樹脂から構成され、第２絶縁層樹脂が、ガラス転移温度が２４０℃以上である絶縁性樹脂から構成されていることを特徴とする請求項１～６のいずれかに記載の半導体装置。 The first insulating resin layer is made of an insulating resin having a glass transition temperature of 300 ° C. or higher, and the second insulating layer resin is made of an insulating resin having a glass transition temperature of 240 ° C. or higher. The semiconductor device according to any one of claims 1 to 6.
  8. 　前記第１絶縁樹脂層及び前記第２絶縁樹脂層が、ポリイミド樹脂、ポリベンズイミダゾール樹脂及びポリベンズオキサゾール樹脂からなる群から選ばれる一種又は二種以上の絶縁性樹脂から構成されていることを特徴とする請求項１～７のいずれかに記載の半導体装置。 The first insulating resin layer and the second insulating resin layer are composed of one or more insulating resins selected from the group consisting of a polyimide resin, a polybenzimidazole resin, and a polybenzoxazole resin. The semiconductor device according to any one of claims 1 to 7.
  9. 　前記第１貫通ビア及び／又は第２貫通ビアが、めっき法又は金属ポスト材を用いる金属接合法により形成されたものである、請求項１～８のいずれかに記載の半導体装置。 9. The semiconductor device according to claim 1, wherein the first through via and / or the second through via are formed by a plating method or a metal bonding method using a metal post material.
  10. 　配線を有する絶縁性放熱シートを有し、その配線部が前記表面第２電極と金属接合されている請求項１～９のいずれかに記載の半導体装置。 10. The semiconductor device according to claim 1, further comprising an insulating heat-dissipating sheet having wiring, the wiring portion of which is metal-bonded to the surface second electrode.
  11. 　リード電極を有し、そのリード電極が前記表面第２電極と金属接合されている請求項１～１０のいずれかに記載の半導体装置。 11. The semiconductor device according to claim 1, further comprising a lead electrode, the lead electrode being metal-bonded to the surface second electrode.
  12. 　以下の工程１～４をこの順で有することを特徴とする半導体装置の製造方法。
    （工程１）半導体基板の表面側に形成された表面第１電極と、前記半導体基板の裏面側に形成された裏面電極とを備える半導体チップと、
    前記表面第１電極上に形成された１又は２以上の第１貫通ビア形成用金属ポストと、前記半導体チップの表面部及び前記第１貫通ビア形成用金属ポストを封止する第１絶縁樹脂層とを有する、１又は２以上の半導体チップ封止体を、
    その裏面電極で放熱基板と金属接合する工程
    （工程２）放熱基板と金属接合された前記半導体チップ封止体全体を覆うように、前記放熱基板表面に第２絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第２絶縁樹脂層を形成する工程
    （工程３）前記第１絶縁樹脂層及び第２絶縁樹脂層表面を薄化処理して、第１絶縁樹脂層と第２絶縁樹脂層を平坦化し、貫通ビア形成用金属ポストの上面を露出させる工程
    （工程４）少なくとも第１絶縁樹脂層表面上に、表面第２電極を形成する工程     A method for manufacturing a semiconductor device, comprising the following steps 1 to 4 in this order:
    (Step 1) a semiconductor chip comprising a front surface first electrode formed on the front surface side of the semiconductor substrate and a back surface electrode formed on the back surface side of the semiconductor substrate;
    One or more first through via forming metal posts formed on the first surface electrode, and a first insulating resin layer for sealing the surface portion of the semiconductor chip and the first through via forming metal post. 1 or 2 or more semiconductor chip sealing bodies having
    A step of metal bonding to the heat dissipation substrate with the back electrode (step 2) A second insulating resin layer forming resin is applied to the surface of the heat dissipation substrate so as to cover the entire semiconductor chip sealing body metal-bonded to the heat dissipation substrate. Step of forming a second insulating resin layer by heating at 300 to 450 ° C. (Step 3) Thinning treatment is performed on the surfaces of the first insulating resin layer and the second insulating resin layer. Step of flattening the insulating resin layer and exposing the upper surface of the metal post for forming the through via (Step 4) Step of forming the surface second electrode on at least the surface of the first insulating resin layer
  13. 　前記半導体基板の厚みが４００μｍ以下である請求項１２に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 12, wherein the thickness of the semiconductor substrate is 400 μm or less.
  14. 　工程４の後に、前記表面第２電極に、配線を有する絶縁性放熱シート、配線を有する絶縁性放熱基板および放熱機能を有するリード電極から選ばれる放熱用部品を、該放熱用部品の配線部又はリード電極部で金属接合する工程をさらに有する、請求項１２又は１３に記載の半導体装置の製造方法。 After step 4, a heat radiating component selected from an insulating heat radiating sheet having wiring, an insulating heat radiating substrate having wiring, and a lead electrode having a heat radiating function on the surface second electrode, a wiring portion of the heat radiating component or The method for manufacturing a semiconductor device according to claim 12, further comprising a step of metal bonding at the lead electrode portion.
  15. 　少なくとも工程２の前に、以下の工程ａ～ｃを有する請求項１２～１４のいずれかに記載の半導体装置の製造方法。
    （工程ａ）放熱基板表面にめっきレジスト膜を成膜し、前記放熱基板の所定部が露出するように、めっきレジスト膜に開口部を設ける工程
    （工程ｂ）前記開口部内に金属を充填し、第２貫通ビア形成用金属ポストを形成する工程
    （工程ｃ）めっきレジスト膜を除去する工程     The method for manufacturing a semiconductor device according to any one of claims 12 to 14, further comprising the following steps a to c before at least step 2.
    (Step a) Forming a plating resist film on the surface of the heat dissipation substrate and providing an opening in the plating resist film so that a predetermined portion of the heat dissipation substrate is exposed (Step b) Filling the opening with a metal, Step of forming second through via forming metal post (step c) Step of removing plating resist film
  16. 　少なくとも工程２の前に、放熱基板表面の所定位置に、第２貫通ビア形成用金属ポストを金属接合法により形成する工程を有する、請求項１２～１４のいずれかに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to any one of claims 12 to 14, further comprising a step of forming a second through via forming metal post by a metal bonding method at a predetermined position on the surface of the heat dissipation substrate at least before step 2. .
  17. 　前記半導体チップ封止体が、以下の工程１．１～１．５、１．７及び１．８をこの順で有する製造工程により得られたものである、請求項１２～１６のいずれかに記載の半導体装置の製造方法。
    （工程１．１）表面第１電極が形成された半導体基板の表面にめっきレジスト膜を成膜する工程
    （工程１．２）前記表面第１電極の所定部が露出するように、めっきレジスト膜に開口部を設ける工程
    （工程１．３）前記開口部に金属を充填し、第１貫通ビア形成用金属ポストを形成する工程
    （工程１．４）めっきレジスト膜を除去する工程
    （工程１．５）前記第１貫通ビア形成用金属ポストを覆うように、前記半導体基板表面に第１絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第１絶縁樹脂層を形成し、同時に前記金属ポストのアニール処理を行う工程
    （工程１．７）前記半導体基板の裏面に裏面電極を形成する工程
    （工程１．８）前記半導体基板をダイシングにより個片化する工程     The semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.1 to 1.5, 1.7 and 1.8 in this order. The manufacturing method of the semiconductor device of description.
    (Step 1.1) Step of depositing a plating resist film on the surface of the semiconductor substrate on which the first surface electrode is formed (Step 1.2) A plating resist film so that a predetermined portion of the first surface electrode is exposed. (Step 1.3) Step of filling the opening with metal and forming a metal post for forming a first through via (Step 1.4) Step of removing the plating resist film (Step 1. 5) A first insulating resin layer forming resin is applied to the surface of the semiconductor substrate so as to cover the first through via forming metal post, and heated at 300 to 450 ° C. to form a first insulating resin layer. Simultaneously annealing the metal posts (Step 1.7) Step of forming a back electrode on the back surface of the semiconductor substrate (Step 1.8) Step of dicing the semiconductor substrate by dicing
  18. 　前記（工程１．５）の後、（工程１．７）の前に、（工程１．６）前記半導体基板の裏面の薄板化処理により、半導体基板の厚みを４００μｍ以下にする工程を有する請求項１７に記載の半導体装置の製造方法。 (Step 1.6) After (Step 1.5) and before (Step 1.7), (Step 1.6) having a step of reducing the thickness of the semiconductor substrate to 400 μm or less by thinning the back surface of the semiconductor substrate. Item 18. A method for manufacturing a semiconductor device according to Item 17.
  19. 　前記半導体チップ封止体が、以下の工程１．９、１．１０、１．１２及び１．１３をこの順で有する製造工程により得られたものである、請求項１２～１５のいずれかに記載の半導体装置の製造方法。
    （工程１．９）表面第１電極が形成された半導体基板の前記表面第１電極上に、第１貫通ビア形成用金属ポストを金属接合法により形成する工程
    （工程１．１０）前記第１貫通ビア形成用金属ポストを覆うように、前記半導体基板表面に第１絶縁樹脂層形成用樹脂を塗布し、３００～４５０℃で加熱して第１絶縁樹脂層を形成する工程
    （工程１．１２）前記半導体基板の裏面に裏面電極を形成する工程
    （工程１．１３）前記半導体基板をダイシングにより個片化する工程     The semiconductor chip sealing body is obtained by a manufacturing process having the following steps 1.9, 1.10, 1.12 and 1.13 in this order. The manufacturing method of the semiconductor device of description.
    (Step 1.9) Forming a first through via forming metal post by a metal bonding method on the surface first electrode of the semiconductor substrate on which the surface first electrode is formed (Step 1.10) A step of applying a first insulating resin layer forming resin to the surface of the semiconductor substrate so as to cover the through via forming metal post and heating at 300 to 450 ° C. to form a first insulating resin layer (step 1.12) ) Step of forming a back electrode on the back surface of the semiconductor substrate (step 1.13) Step of dicing the semiconductor substrate by dicing
  20. 　前記（工程１．１０）の後、工程（１．１２）の前に、（工程１．１１）前記半導体基板の裏面の薄板化処理により、半導体基板の厚みを４００μｍ以下にする工程を有する請求項１９に記載の半導体装置の製造方法。 (Step 1.11) After (Step 1.10) and before Step (1.12), (Step 1.11) has a step of reducing the thickness of the semiconductor substrate to 400 μm or less by thinning the back surface of the semiconductor substrate. Item 20. A method for manufacturing a semiconductor device according to Item 19.
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