WO2012083672A1 - 三维半导体存储器件及其制备方法 - Google Patents

三维半导体存储器件及其制备方法 Download PDF

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WO2012083672A1
WO2012083672A1 PCT/CN2011/076674 CN2011076674W WO2012083672A1 WO 2012083672 A1 WO2012083672 A1 WO 2012083672A1 CN 2011076674 W CN2011076674 W CN 2011076674W WO 2012083672 A1 WO2012083672 A1 WO 2012083672A1
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霍宗亮
刘明
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention relates to the field of microelectronics, and in particular, to a nonvolatile high-density three-dimensional semiconductor memory device and a method of fabricating the same. Background technique
  • Semiconductor memory technology is one of the key technologies in the field of microelectronics.
  • Current storage technology research focuses on high-density, high-performance non-volatile flash technology research.
  • the traditional FLASH technology encounters more and more serious technical difficulties in the process of achieving the ratio change, such as crosstalk, slow writing speed, etc., so it is difficult to adapt to the development of the storage technology of the 20 nanometer node. Claim. Therefore, high-capacity storage needs to develop new storage technologies.
  • Resistive random access memory is a reversible conversion between high impedance and low resistance of a storage medium under the action of an electrical signal to distinguish two states.
  • the memory cell structure is generally formed by stacking three layers of an upper electrode, a resistive material and a lower electrode in sequence, which has the advantages of simple structure, easy manufacturing, and compatibility with an existing CMOS process. To this end, three-dimensional integration of resistive memory cells is expected to enable high-density data storage and is expected to be used in a variety of applications such as Solid State Disk.
  • FIG. 1 is a schematic illustration of a prior art semiconductor memory device of the 1D1R structure. As shown in FIG. 1, although the 1D1R type three-dimensional resistive memory device can increase the storage density to some extent, since the diode constituting the memory cell is generally composed of a PN junction, it is difficult to achieve a true ratio of the height of the memory cell. .
  • the height of the conventional PN junction will be greater than 100 nanometers. In order to increase the forward bias current and suppress the reverse bias current, it is even necessary to use a layer of intrinsic silicon in the middle of the PN junction, in order to suppress the interdiffusion of metal and P-type silicon in the lower metal electrode.

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  • Semiconductor Memories (AREA)

Description

三维半导体存储器件及其制备方法
技术领域
本发明涉及微电子技术领域， 尤其涉及一种非易失性高密度的三维 半导体存储器件及其制备方法。 背景技术
半导体存储技术是微电子技术领域的关键技术之一。 随着信息技术 从网络和计算为核心转入以存储为核心， 存储技术的研究成为了信息技 术研究的重要方向。 当前存储技术的研究主要集中在高密度、 高性能的 非挥发性闪存技术研究上面。 随着器件尺寸的不断縮小， 传统 FLASH技 术在实现变比的过程中遭遇到越来越严重的技术难点， 如串扰、 写入速 度慢等， 因而难以适应后 20纳米结点的存储技术发展的要求。 因此， 大 容量存储需求需要发展新的存储技术。
近年来， 阻变存储技术引起了众多研究者的注意， 并被认为是后 20 纳米结点的关键技术。 电阻随机存储器（RRAM)是利用电信号作用下存 储介质在高阻和低阻间的可逆转换来区分两态。 存储单元结构一般由上 电极、 阻变材料和下电极三层依次堆叠形成， 其具有结构简单， 制造容 易， 以及和现有 CMOS工艺兼容的优点。 为此， 对阻变存储单元的三维 集成将有望实现高密度的数据存储并有望用于固态磁盘 （Solid State Disk) 等多种应用。
鉴于常规十字结 （cross-bar)型阻变存储单元之间的串扰效应， 常规 的阻变存储技术需要借助于二极管或者选择晶体管来实现单元的选择， 其中， 1D1R和 1T1R是两种典型的存储结构。 三维阻变存储主要是实现 这两种典型存储结构的三维集成。图 1为现有技术 1D1R结构的半导体存 储器件的示意图。如图 1所示， 尽管 1D1R型三维阻变存储器件可以在一 定程度上提高存储密度，然而由于构成存储单元的二极管一般是由 PN结 所构成， 因此其很难实现存储单元高度的真正变比。常规 PN结的高度将 大于 100纳米， 为了提高正偏电流， 抑制反偏电流， 甚至需要在 PN结中 间采用一层本征硅， 为了抑制下金属电极中的金属与 P型硅的互扩散也

Claims

权禾 lj 要 求
1、 一种三维半导体存储器件， 其特征在于， 包括衬底和位于所 述衬底上方的一个或多个垂直存储阵列串，每个所述存储阵列串包括 垂直型环栅晶体管和垂直环状阻变单元， 其中：
在位线方向上，相邻的所述垂直存储阵列串的所述垂直型环栅晶 体管共享源区， 所述垂直型环栅晶体管的栅极通过绝缘层隔离， 所述 垂直环状阻变单元的上电极通过绝缘层隔离，共享的所述源区作为所 述存储阵列串的位线；
在字线方向上，相邻的所述垂直存储阵列串的所述垂直型环栅晶 体管的源区通过浅槽隔离区隔离，所述垂直型环栅晶体管的栅极相互 连接， 所述垂直环状阻变单元的上电极相互连接。
2、 根据权利要求 1所述的三维半导体存储器件， 其特征在于， 所述垂直型环栅晶体管包括：
源区， 形成于所述衬底的上方；
沟道区， 形成于所述源区上方， 垂直于所述衬底；
漏极， 形成于所述沟道区和所述垂直环状阻变单元之间； 以及 栅绝缘层和栅极， 依次形成于所述沟道区的侧面。
3、 根据权利要求 2所述的三维半导体存储器件， 其特征在于， 所述垂直环状阻变单元包括纵向设置的一个或多个环状电阻子单元， 所述环状电阻子单元包括：
下电极， 形成于所对应的垂直型环栅晶体管的漏极上， 对应同一 垂直型环栅晶体管的一个或多个环状电阻子单元共享下电极；
阻变功能层， 形成于所述下电极预设位置的侧面， 用于区分信息 状态； 以及
上电极， 形成于所述阻变功能层上方， 构成垂直环状阻变单元的 各层上电极之间互相绝缘，相邻的垂直环状阻变单元的环状电阻子单 元的上电极， 在位线方向相互绝缘， 在字线方向则共享连接到阵列外 围。
4、 根据权利要求 2所述的三维半导体存储器件， 其特征在于， 所述垂直型环栅晶体管中，
所述源极， 通过注入形成， 或通过形成金属硅化物形成， 或者通 过金属埋层形成；
所述沟道区， 通过对所述衬底的刻蚀完成， 或通过外延生长或者 沉积工艺完成；
所述栅极， 通过先形成栅极然后形成沟道的 "gate-first"工艺完 成， 或通过先完成沟道在形成栅极的 "gate-last"工艺完成；
所述栅介质层， 通过沉积工艺完成； 以及
所述漏极， 通过掺杂注入形成， 或通过硅化工艺形成， 或通过沉 积金属方式形成。
5、 根据权利要求 4所述的三维半导体存储器件， 其特征在于， 所述沟道区的材料为以下材料中的一种： 硅、 多晶硅或锗； 所述栅极的材料为以下材料中的一种： 多晶硅、金属或金属硅化 所述栅介质层的材料为以下材料中的一种： 8102或 SiOxNy。
6、 根据权利要求 3所述的三维半导体存储器件， 其特征在于， 所述下电极由单层金属、 金属钝化层和金属双层结构构成； 所述阻变薄膜功能层，通过沉积单层阻变材料或者多层阻变材料 形成， 通过改变功能层材料的相位予以实现。
7、 根据权利要求 6所述的三维半导体存储器件， 其特征在于， 所述下电极的材料为以下材料中的一种： Ag， Au， Cu, W， Ti，
Pt， Ti， Ta, TiN, TaN或 WN;
所述阻变功能层为以下材料中的一种： P xCaxMn03， 其中 0<x<l ; SrTiO.3 ; SrZr03; Hf02; Cu02; Ti02; Zr02; NiOx其中， 0<x<2; Nb205; MoO; Ge2Sb2Te5; GeTe或 GeTeC;
所述上电极为以下材料中的一种或多种： Ag、 Au、 Cu、 W、 Ti、 Pt、 Ti、 Ta、 窗、 TaN或 WN。
8、 一种三维半导体存储器件的制备方法， 其特征在于， 包括： 在衬底上制备垂直环栅晶体管； 在制备了所述垂直环栅晶体管的衬底上形成垂直环状阻变单元， 从而完成三维半导体存储器件的制备。
9、 根据权利要求 8所述的三维半导体存储器件制备方法， 其特 征在于， 所述在衬底上制备垂直环栅晶体管包括：
在所述衬底上形成浅槽隔离区定义位线区域；
采用离子注入工艺或者硅化工艺在所述位线区域形成位线； 在已形成位线的所述衬底上沉积 Si02绝缘层 /SiN牺牲层 /Si02绝 缘层堆栈；
在沉积 Si02/SiN/Si02堆栈的所述衬底上在位线区域上方刻蚀形 成通孔， 定义沟道区域；
在所述定义沟道区域的衬底上采用外延工艺形成沟道，或者采用 沉积并退火的工艺在通孔区域形成沟道区；
采用离子注入形成漏区；
在形成漏区的衬底上刻蚀定义形成字线区域；
在形成字线区域的衬底上移去 SiN牺牲层；
在移去 SiN牺牲层的衬底上采用 gate-last工艺的栅介质和栅极沉 积和回刻； 以及
沉积绝缘介质层隔离区。
10、根据权利要求 9所述的三维半导体存储器件制备方法， 其特 征在于， 所述刻蚀定义形成字线区域之前还包括：
沉积金属或者硅化形成低阻漏接触区。
1 1、根据权利要求 9所述的三维半导体存储器件制备方法， 其特 征在于，所述在制备了垂直环栅晶体管的衬底上制备垂直环状阻变单 元包括：
交替沉积多层的隔绝层和牺牲层 SiN， 通过厚度定义阻变单元尺 寸， 所述牺牲层的层数对应于环状电阻子单元的个数；
通孔刻蚀定义阻变阵列单元的下电极区域，所述下电极区域向下 连接所述垂直环栅晶体管的漏极；
在通孔区域沉积金属钝化层和下电极金属；
在字线方向刻蚀堆栈层定义阻变单元的上电极尺寸； 移去 SiN牺牲层；
沉积形成阻变功能层薄膜和上电极， 回刻完成单元间隔离; 进行绝缘层介质沉积， 外围金属连线。
PCT/CN2011/076674 2010-12-22 2011-06-30 三维半导体存储器件及其制备方法 Ceased WO2012083672A1 (zh)

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