WO2012043742A1 - Procédé de fabrication de substrat de boîtier pour montage d'éléments semi-conducteurs - Google Patents

Procédé de fabrication de substrat de boîtier pour montage d'éléments semi-conducteurs Download PDF

Info

Publication number
WO2012043742A1
WO2012043742A1 PCT/JP2011/072423 JP2011072423W WO2012043742A1 WO 2012043742 A1 WO2012043742 A1 WO 2012043742A1 JP 2011072423 W JP2011072423 W JP 2011072423W WO 2012043742 A1 WO2012043742 A1 WO 2012043742A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal foil
carrier
carrier metal
multilayer
plating
Prior art date
Application number
PCT/JP2011/072423
Other languages
English (en)
Japanese (ja)
Inventor
田村　匡史
学 杉林
邦司 鈴木
清男 服部
Original Assignee
日立化成工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立化成工業株式会社 filed Critical 日立化成工業株式会社
Priority to CN201180045417.4A priority Critical patent/CN103119710B/zh
Priority to KR1020137005647A priority patent/KR101466524B1/ko
Publication of WO2012043742A1 publication Critical patent/WO2012043742A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Definitions

  • the present invention relates to a method for manufacturing a package substrate for mounting a semiconductor element capable of increasing the density.
  • PoP Package on Package
  • SiP System in Package
  • an interlayer connection hole is provided in an insulating base material provided with a thin copper foil having a thickness of about 2 ⁇ m, and a thickness of about 0.1 ⁇ m is formed on the thin copper foil and in the interlayer connection hole.
  • Perform thin electroless copper plating form a plating resist on it, thicken the part that will become the outer layer circuit by pattern electroplating, then remove the plating resist and etch the entire surface to perform pattern electroplating.
  • Patent Document 1 There is a method of forming an outer layer circuit by removing only a portion that is not (that is, only a thin portion of a conductor)
  • a support substrate is formed by providing an insulating resin on the carrier copper foil surface of an ultrathin copper foil (thickness 1 to 5 ⁇ m) with a carrier copper foil that can be physically peeled, After forming a conductor pattern to be an outer layer circuit by pattern copper plating, forming an insulating resin and interlayer connection on it, the support substrate including the carrier copper foil is physically peeled off, and the ultrathin copper foil is removed by etching Thus, there is a method of forming a fine outer layer circuit (Patent Document 2).
  • a wiring film having a predetermined pattern is formed on the surface of the intermediate film of the carrier film, conductive pillars are formed on the surface of the wiring film by pattern plating, and two wiring members on which an interlayer insulating film is formed are prepared.
  • wiring is formed by stacking and integrating so that the end surfaces of pillars are in contact with each other, removing the carrier film by etching using the intermediate film as an etching stop layer, and further removing the intermediate film by etching (Patent Document 3).
  • the carrier film is removed by etching using the intermediate film as an etching stop layer, and further the intermediate film is removed by etching.
  • the yield is lowered because defects such as pinholes are likely to occur in the etching stop layer.
  • etching is performed in two stages, the unevenness on the surface of the formed outer layer circuit may increase, and the connection reliability with the semiconductor element may decrease.
  • connection terminal flip chip connection or wire bonding connection is used for electrical connection between the semiconductor element and the connection terminal of the package substrate.
  • connection terminal becomes finer, the influence of surface irregularities on the connection reliability tends to increase. For this reason, flattening of the surface of the outer layer circuit to be the connection terminal is required.
  • formation of bumps, pillars, etc. may be required depending on the connection form with the semiconductor element to be mounted.
  • the present invention has been made in view of the above problems, yield can be improved by suppressing the adhesion of resin powder, there is fine and adhesive force by forming an embedded circuit without undercut, An outer layer circuit having a flat surface can be formed, and a method for manufacturing a package substrate for mounting a semiconductor element capable of forming various metal structures such as bumps and pillars by forming a three-dimensional circuit at an arbitrary position is provided. .
  • the present invention relates to the following.
  • a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order is prepared, and a base metal foil side of the multilayer metal foil and a base material are laminated to form a core substrate.
  • a step of physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and the second carrier remaining on the core substrate A step of performing a first pattern plating on the metal foil, a step of forming an insulating layer on the second carrier metal foil including the first pattern plating, and a second of the multilayer metal foil.
  • a step of physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and the second carrier remaining on the core substrate A step of performing a first pattern plating on the metal foil, a step of forming an insulating layer on the second carrier metal foil including the first pattern plating, and a second of the multilayer metal foil.
  • Step of performing pattern plating of 2 and before A step of removing the second carrier metal foil other than the portion subjected to the second pattern plating by etching and forming a three-dimensional circuit on the first pattern plating or on the insulating layer.
  • a manufacturing method of a package substrate (3) A multilayer metal foil in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order is prepared, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate.
  • a step of physically peeling the first carrier metal layer between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and the second carrier remaining on the core substrate A step of performing a first pattern plating on the metal foil, a step of forming an insulating layer on the second carrier metal foil including the first pattern plating, and a second of the multilayer metal foil.
  • the multilayer metal foil has a peel strength between the second carrier metal foil and the base metal foil, the first carrier metal foil and the second carrier metal foil
  • a method of manufacturing a package substrate for mounting a semiconductor element which is a multilayer metal foil formed larger than the peel strength between.
  • the multilayer metal foil is formed on the surface of the second carrier copper foil provided with irregularities having an average roughness (Ra) of 0.3 ⁇ m to 1.2 ⁇ m in advance.
  • Ra average roughness
  • the present invention it is possible to improve the yield by suppressing the adhesion of the resin powder, and it is possible to form an outer layer circuit having a fine and adhesive force and a flat surface by forming an embedded circuit that does not cause an undercut.
  • a multilayer metal foil 9 formed by laminating a first carrier metal foil 10, a second carrier metal foil 11, and a base metal foil 12 in this order is prepared.
  • the first carrier metal foil 10 is for protecting the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side), and is physically separated from the second carrier metal foil 11. It is possible.
  • the material and thickness are not particularly limited as long as the surface of the second carrier metal foil 11 can be protected. However, from the viewpoint of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is preferably 1 to 35 ⁇ m. Moreover, it is preferable to provide the peeling layer 13 between the 1st carrier metal foil 10 and the 2nd carrier metal foil 11 for stabilizing the peeling strength between these metal foils 10 and 11, and peeling.
  • the layer 13 is preferably one in which the peel strength is stabilized even if the heating and pressurization at the time of laminating with the insulating resin are performed a plurality of times.
  • a release layer 13 include those in which a metal oxide layer and an organic agent layer disclosed in JP-A-2003-181970 are formed, and Cu—Ni—Mo disclosed in JP-A-2003-094553. Examples thereof include those made of an alloy and those containing a metal oxide of Ni and W or a metal oxide of Ni and Mo shown in the republished patent WO 2006/013735.
  • the second carrier metal foil 11 serves as a seed layer for supplying a current for performing the first pattern plating 18 on the surface after the first carrier metal foil 10 is peeled off.
  • the material and thickness are not particularly limited. However, from the viewpoint of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is 1 to 18 ⁇ m. Can be used. However, as will be described later, when the outer layer circuit 2 is formed (FIG. 7 (n), FIG. 8 (n), FIG. 10 (m)), it is removed by etching, so variation in etching amount is reduced as much as possible.
  • an ultrathin metal foil of 1 to 5 ⁇ m is preferable.
  • the release layer 13 is preferably provided between the first carrier metal foil 10 and the base metal foil 12, in order to stabilize the peel strength between these metal foils 10, 12, the release layer 13, as described above.
  • the release layer 14 is preferably conductive so that the second carrier metal foil 11 and the base metal foil 12 are integrated to act as a seed layer.
  • the peeling layer 14 physically peels between the 2nd carrier metal foil 11 and the base metal foil 12, it is desirable to transfer to the base metal foil 12 side.
  • the base metal foil 12 is positioned on the side laminated with the base material 16 when the multilayer metal foil 9 is laminated with the base material 16 to produce the core substrate 17. It can be physically peeled between.
  • the material and the thickness are not particularly limited as long as they have adhesiveness with the base material 16, but the material is copper foil or aluminum foil in terms of versatility and handleability.
  • the thickness is preferably 9 to 70 ⁇ m. Further, in order to stabilize the peel strength between the second carrier metal foil 11 and the metal foil 11, it is preferable to provide the peel layer 14 as described above.
  • the multilayer metal foil 9 is a multilayer metal foil 9 having three or more layers of metal foils (for example, as described above, the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12), Physical separation between at least two locations (for example, as described above, between the first carrier metal foil 10 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the base metal foil 12) Use what is possible.
  • foreign matter such as resin powder may adhere to the surface of the first carrier metal foil 10.
  • the second carrier metal that is not affected by foreign matters such as resin powder is obtained by physically peeling the first carrier metal foil 10 from the second carrier metal foil 11. Since the surface of the foil 11 is formed, a high-quality metal foil surface can be secured. Therefore, even when the first pattern plating 18 is performed using the second carrier metal foil 11 as a seed layer, the occurrence of defects can be suppressed, so that the yield can be improved.
  • the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 are laminated to form a core substrate 17.
  • the base material 16 is laminated and integrated with the multilayer metal foil 9 to form the core substrate 17.
  • the base material 16 is generally used as the insulating layer 3 of the semiconductor element mounting package substrate 1. Can be used. Examples of the substrate 16 include glass epoxy and glass polyimide.
  • the core substrate 17 serves as a support substrate when the package substrate 1 is manufactured using the multilayer metal foil 9. By ensuring rigidity, workability is improved and damage during handling is prevented. The main role is to improve the yield. For this reason, it is desirable that the substrate 16 has a reinforcing material such as glass fiber.
  • a prepreg such as glass epoxy or glass polyimide is overlapped with the multilayer metal foil 9 and heated / heated using a hot press or the like. It can be formed by pressing and laminating and integrating.
  • Multilayer metal foil 9 is laminated on both sides of substrate 16 (upper and lower sides in FIG. 2 (a)), and the subsequent steps are performed to advance the process of manufacturing two package substrates 1 in a single process. Therefore, man-hours can be reduced.
  • the laminated board of a symmetrical structure can be comprised on both sides of the core board
  • the first carrier metal foil is physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9.
  • the first carrier metal foil 10 On the surface of the first carrier metal foil 10, there may be a case where foreign matters such as resin powder from a prepreg or the like that becomes a material of the base material 16 at the time of lamination adhere.
  • foreign matter such as resin powder adhered to the surface may cause defects such as disconnection or short circuit in the circuit, leading to a decrease in yield. there is a possibility.
  • the first carrier metal foil 10 is peeled and removed in this way, a circuit can be formed using the second carrier metal foil 11 to which no foreign matter such as resin powder adheres.
  • the peeling work can be easily performed by adjusting the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. Can do.
  • the surface of the 2nd carrier metal foil 11 is exposed to the 2nd carrier metal foil 11 side after peeling the 1st carrier metal foil 10, it is on the 2nd carrier metal foil 11 performed by a post process.
  • the formation of the plating resist and the formation of the first pattern plating 18 are not hindered by the release layer 13.
  • the peel strength between the second carrier metal foil 11 and the base metal foil 12 is greater than the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. It is desirable that the multilayer metal foil 9 be formed. This suppresses simultaneous peeling between the second carrier metal foil 11 and the base metal foil 12 when physically peeling between the first carrier metal foil 10 and the second carrier metal foil 11. be able to.
  • the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11 at the initial stage before heating and pressurization (before the core substrate 17 is formed by laminating the prepreg serving as the base material 16), 2 N / m to 50 N / m, 10 N / m to 70 N / m between the second carrier metal foil 11 and the base metal foil 12, and peeling between the first carrier metal foil 10 and the second carrier metal foil 11
  • the strength is 5 N / m to 20 N / m less than the peel strength between the second carrier metal foil 11 and the base metal foil 12, and after heating and pressurizing (a prepreg serving as a base material 16 is laminated to form a core substrate
  • the rate of change in peel strength after forming 17 is about 20% or less relative to the initial value, the peel does not peel off due to handling in the manufacturing process, but peels off even after heating and pressurizing. Easy to do, Upon the release of the first carrier metal foil 10 duck, good workability since the second carrier metal foil 11 can be prevented peeling is
  • the adjustment of the peel strength is performed by using the second carrier metal foil 11 serving as the base of the release layer. This can be achieved by adjusting the roughness of the surface (the surface on the first carrier metal foil 10 side) or by adjusting the plating solution composition and conditions for forming a metal oxide or alloy plating layer to be a release layer. .
  • the first pattern plating 18 is performed on the second carrier metal foil 11 remaining on the core substrate 17.
  • the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side) does not adhere to foreign matters such as resin powder from the prepreg used at the time of lamination, so the circuit resulting from this Defects can be suppressed.
  • the first pattern plating 18 can be performed using electroplating after forming a plating resist (not shown) on the second carrier metal foil 11.
  • a plating resist a photosensitive resist used in a general package substrate manufacturing process can be used.
  • the electroplating copper sulfate plating used in a general package substrate manufacturing process can be used.
  • the multilayer metal foil 9 is formed by laminating the first carrier metal foil 10 on the surface of the second carrier metal foil 11 provided with irregularities having an average roughness (Ra) of 0.3 ⁇ m to 1.2 ⁇ m in advance via a release layer 13.
  • the multilayer metal foil 9 is desirable. Thereby, the surface of the second carrier metal foil 11 after the first carrier metal foil 10 is physically peeled off together with the peeling layer 13 has irregularities with an average roughness (Ra) provided in advance of 0.3 ⁇ m to 1.2 ⁇ m.
  • the plating resist for the first pattern plating 18 is formed on the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side), the adhesion and resolution of the plating resist are improved.
  • the surface roughness of the irregularities provided on the surface of the second carrier metal foil 11 has an average roughness (Ra) of 0.3 to 1.2 ⁇ m, while improving the adhesion and resolution of the plating resist. It is desirable at the point which can ensure the peelability after 1 pattern plating 18.
  • the average roughness (Ra) is less than 0.3 ⁇ m, the adhesion of the plating resist tends to be insufficient, and when the average roughness (Ra) exceeds 1.2 ⁇ m, the plating resist becomes difficult to follow and the adhesion is insufficient. Tend to occur.
  • the average roughness (Ra) is desirably 0.5 ⁇ m to 0.9 ⁇ m.
  • the average roughness (Ra) is an average roughness (Ra) defined by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like.
  • adjustment of average roughness (Ra) is the composition (additive etc.) of the electro copper plating at the time of forming the copper foil as the 2nd carrier metal foil 11 if the 2nd carrier metal foil 11 is a copper foil. And the conditions (current density, time, etc.) can be adjusted.
  • the insulating layer 3 is laminated on the second carrier metal foil 11 including the first pattern plating 18 to form a laminate 22.
  • the insulating layer 3 one generally used as the insulating layer 3 of the package substrate 1 can be used.
  • the insulating layer 3 include an epoxy resin and a polyimide resin.
  • an epoxy or polyimide adhesive sheet, a glass epoxy or a glass polyimide prepreg is heated and heated using a hot press or the like. It can be formed by pressing and laminating and integrating.
  • the laminated body 22 refers to one laminated on the second carrier metal foil 11 including the first pattern plating 18 among those laminated and integrated.
  • this conductor layer 20 is also included.
  • the inner layer circuit 6 is formed by the conductor layer 20 or the interlayer connection 5 for connecting the conductor layer 20 is formed, the inner layer circuit 6 and the interlayer connection 5 are also included.
  • the interlayer connection hole 21 may be formed, and the interlayer connection 5 and the inner layer circuit 6 may be formed.
  • the interlayer connection 5 can be formed, for example, by forming the interlayer connection hole 21 by using a so-called conformal method and then plating the interlayer connection hole 21.
  • electroless copper plating, electrolytic copper plating, filled via plating, or the like can be used as the thick plating after thin electroless copper plating is performed as the base plating.
  • the inner layer circuit 6 can be formed, for example, by plating the interlayer connection hole 21 and then removing the unnecessary conductor layer 20 by etching.
  • the insulating layer 3 and the conductor layer 20 are further formed on the inner circuit 6 and the interlayer connection 5, Similarly to the case of FIGS. 3E and 3F, the inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 can be formed so as to have a desired number of layers.
  • the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Exfoliate and separate.
  • the peeling layer 14 between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9 is moved to the base metal foil 12 side.
  • an etching resist 25 is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled, and the second structure of the laminated body 22 is obtained.
  • the two-carrier metal foil 11 is etched to expose the first pattern plating 18 on the surface of the insulating layer 3 and to form a three-dimensional circuit 24 on the first pattern plating 18 or on the insulating layer 3.
  • the second pattern plating 23 is performed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled, and the second pattern.
  • the second carrier metal foil 11 other than the portion where the plating 23 has been performed is removed by etching to expose the first pattern plating 18 on the surface of the insulating layer 3, and on the first pattern plating 18 or the insulating layer 3.
  • a three-dimensional circuit 24 can also be formed.
  • the second carrier metal foil 11 of the separated laminate 22 is removed by etching or the like, and the first pattern plating 18 is replaced with the insulating layer 3.
  • Expose to the surface of. 7 (l), (m), (n), FIG. 8 (l), (m), (n) and FIG. 10 (l), (m), (n) are shown in FIG. 6 (k). Only the lower part of the laminated body 22 separated as shown in FIG.
  • the outer layer circuit 2 when the outer layer circuit 2 is formed, the side surface of the outer layer circuit 2 is not eroded by etching, so that no undercut occurs, so that the fine outer layer circuit 2 can be formed. Further, since the outer layer circuit 2 formed in the present invention is embedded in the insulating layer 3, not only the bottom surface of the outer layer circuit 2 but also the side surfaces on both sides are in close contact with the insulating layer 3, so that the fine circuit Even so, sufficient adhesion can be ensured. Further, when an ultrathin copper foil having a thickness of 1 ⁇ m to 5 ⁇ m is used as the second carrier metal foil 11, the second carrier metal foil 11 can be removed even with a slight etching amount, so that it is embedded in the insulating layer 3.
  • connection terminal with the semiconductor element can be provided in the outer layer circuit 2 at a position overlapping the interlayer connection 5 in plan view, the connection terminal with the semiconductor element is provided directly above or immediately below the interlayer connection 5. It is possible to cope with downsizing and high density. Furthermore, it is possible to form various metal structures such as bumps and pillars by forming the solid circuit 24 at an arbitrary place, and by changing the thickness of the second carrier metal foil 11 and the second pattern plating 23, any metal structure can be formed. Therefore, it is possible to cope with various semiconductor elements (not shown) and connection forms with other package substrates. For example, as shown in FIG. 9, PoP can be configured without providing a cavity.
  • solder resist 4 and protective plating 8 may be formed as necessary.
  • the protective plating 8 nickel plating and gold plating which are generally used as protective plating for connection terminals of the package substrate are desirable.
  • a package substrate having a flat and fine embedded circuit at a position overlapping with an interlayer connection, which is suitable for wire bonding and flip chip connection.
  • a package substrate can be formed.
  • a package substrate having various metal structures such as bumps and pillars can be formed by forming a three-dimensional circuit at an arbitrary location.
  • Example 1 First, as shown in FIG. 1, the multilayer metal foil 9 formed by laminating the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12 in this order was prepared.
  • the first carrier metal foil 10 is a 9 ⁇ m copper foil
  • the second carrier metal foil 11 is a 3 ⁇ m ultrathin copper foil
  • the base metal foil 12 is an 18 ⁇ m copper foil.
  • a release layer 14 was provided on the surface of the base metal foil 12 (the surface on the second carrier metal foil 11 side) so that physical peeling was possible. Further, the surface of the second carrier metal foil 11 (the surface on the first carrier metal foil 10 side) was provided with irregularities having an average roughness (Ra) of 0.7 ⁇ m in advance.
  • a release layer 13 was provided on the unevenness, that is, between the first carrier metal foil 10 so as to allow physical peeling.
  • the release layers 13 and 14 between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) and Mo (molybdenum). ), And forming a metal oxide layer using a plating bath containing citric acid.
  • the peel strength was adjusted by adjusting the current density and time to adjust the amount of metal oxide forming the peel layers 13 and 14. At this time, the initial peel strength before heating and pressurization (before forming the core substrate 17 by laminating the prepreg serving as the base material 16) is 47 N between the base metal foil 12 and the second carrier metal foil 11.
  • the distance between the second carrier metal foil 11 and the first carrier metal foil 10 was 29 N / m. Note that the rate of change in peel strength after heating and pressing (after forming the core substrate 17 by laminating the prepreg serving as the base material 16) was about 10% higher than the initial level.
  • the multilayer metal foil 9 shown in FIG. 1 was produced as follows. (1) As the base metal foil 12, an electrolytic copper foil having a thickness of 18 ⁇ m was used, immersed in sulfuric acid 30 g / L for 60 seconds, washed with acid and then washed with running water for 30 seconds.
  • Nickel sulfate hexahydrate as a plating bath containing Ni (nickel), Mo (molybdenum), and citric acid, with the washed electrolytic copper foil as the cathode, the Ti electrode plate with iridium oxide coating as the anode, and Ni (nickel), Mo (molybdenum), and citric acid 30 g / L, sodium molybdate dihydrate 3.0 g / L, trisodium citrate dihydrate 30 g / L, pH 6.0, bath temperature of 30 ° C. Electrolytic treatment was performed at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum.
  • a release layer 13 containing a metal oxide was formed.
  • the surface after forming the release layer 13 is subjected to electrolytic plating at a current density of 4 A / dm 2 for 600 seconds using the same bath as the above (3), and the first carrier metal foil 10 having a thickness of 9 ⁇ m A metal layer was formed.
  • Granular roughened particles were formed on the surface in contact with the substrate 16 by copper sulfate plating, and subjected to chromate treatment and silane coupling agent treatment. Further, the chromate treatment was applied to the surface not in contact with the substrate 16.
  • the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 were laminated to form a core substrate 17.
  • a glass epoxy prepreg was used as the substrate 16, and the multilayer metal foils 9 were stacked on both upper and lower sides of the prepreg, and were laminated and integrated by heating and pressing using a hot press.
  • the first carrier metal foil 10 was physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9.
  • the first pattern plating 18 was performed on the second carrier metal foil 11 remaining on the core substrate 17.
  • the first pattern plating 18 was formed using copper sulfate electroplating after forming a photosensitive plating resist on the second carrier metal foil 11.
  • a copper foil (12 ⁇ m) is laminated as the insulating layer 3 and the conductor layer 20 on the second carrier metal foil 11 including the first pattern plating 18 to form a laminate 22.
  • the insulating layer 3 was formed by laminating and integrating an epoxy adhesive sheet by heating and pressing using a hot press.
  • the interlayer connection 5 was formed by forming the interlayer connection hole 21 using a conformal method and then plating the interior of the interlayer connection hole 21.
  • thin electroless copper plating was performed as a base plating
  • a photosensitive plating resist was formed
  • thick plating was performed by copper sulfate electroplating.
  • the inner layer circuit 6 was formed by removing the unnecessary conductor layer 20 by etching.
  • the insulating layer 3 and the conductor layer 20 are further formed on the inner circuit 6 and the interlayer connection 5,
  • the inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 were formed to form a laminate 22 having four conductor layers 20.
  • the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Peeled off and separated.
  • an etching resist is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled, and the second of the laminated body 22 is formed.
  • the carrier metal foil 11 was etched to expose the first pattern plating 18 on the surface of the insulating layer 3 and to form a three-dimensional circuit 24 on the first pattern plating 18 or on the insulating layer 3.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher.
  • the amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed. Specifically, electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 7.5 A / dm 2 for 15 seconds.
  • a release layer 13 containing a metal oxide made of nickel and molybdenum was formed.
  • the initial peel strength before heating and pressurization at this time is 23 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10.
  • the peel strength after heating / pressurizing was about 10 to 20% higher than the initial level.
  • a package substrate was fabricated in the same manner as in Example 1 except for this.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher.
  • the amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 5 A / dm 2 for 20 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 2 A / dm 2 for 20 seconds. And a release layer 13 containing a metal oxide made of molybdenum.
  • the initial peel strength before heating and pressing at this time is 15 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10.
  • the peel strength after heating / pressurizing was about 10 to 20% higher than the initial level.
  • a package substrate was fabricated in the same manner as in Example 1 except for this.
  • Example 4 The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher.
  • the amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 25 A / dm 2 for 4 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 20 A / dm 2 for 4 seconds. And a release layer 13 containing a metal oxide made of molybdenum.
  • the initial peel strength before heating and pressurization at this time is 68 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10.
  • the peel strength after heating / pressurizing was about 5 to 10% higher than the initial value.
  • the multilayer metal foil 9 prepared above instead of the steps shown in FIGS. 7 (l), (m), and (n) of Example 1, it is shown in FIGS. 8 (l), (m), and (n).
  • the second pattern metal plating 23 is performed on the second carrier metal foil 11 of the laminate 22 separated and peeled, and the second carrier metal foil 11 other than the portion where the second pattern metal plating 23 is performed is etched.
  • the first pattern plating 18 was exposed on the surface of the insulating layer 3 and the three-dimensional circuit 24 was formed on the first pattern plating 18 or the insulating layer 3.
  • a package substrate was fabricated in the same manner as in Example 1 except for this step.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher.
  • the amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds. And a release layer 13 containing a metal oxide made of molybdenum.
  • the initial peel strength before heating and pressurization at this time is 43 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10.
  • the peel strength after heating and pressing was about 10 to 15% higher than the initial value.
  • a package substrate was fabricated in the same manner as in Example 4 except for this.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher.
  • the amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 2.5 A / dm 2 for 40 seconds. A release layer 13 containing a metal oxide made of nickel and molybdenum was formed.
  • the initial peel strength before heating and pressurization at this time is 22 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10.
  • the peel strength after heating and pressing was about 5 to 15% higher than the initial level.
  • a package substrate was fabricated in the same manner as in Example 4 except for this.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni (nickel), Mo (molybdenum), and quencher.
  • the amount of the metal oxide forming the release layers 13 and 14 was adjusted and changed by changing the current when forming the metal oxide layer using a plating bath containing an acid. Specifically, electrolytic treatment is performed at a current density of 20 A / dm 2 for 5 seconds to form a release layer 14 containing a metal oxide composed of nickel and molybdenum, and electrolytic treatment is performed at a current density of 10 A / dm 2 for 10 seconds. And a release layer 13 containing a metal oxide made of molybdenum.
  • the initial peel strength before heating and pressurization at this time is 45 N / m between the base metal foil 12 and the second carrier metal foil 11, and between the second carrier metal foil 11 and the first carrier metal foil 10.
  • Table 1 shows the finished state of the outer layer circuit 2 embedded in the insulating layer 3 for Examples 1 to 7, the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11, the second The peel strength between the carrier metal foil 11 and the base metal foil 12 and the presence or absence of peeling of the carrier metal foil during handling are shown.
  • ⁇ in Table 1 indicates no undercut.
  • no undercut had occurred.
  • the second carrier metal foil 11 is made of ultra-thin copper having a thickness of 3 ⁇ m, the second carrier metal foil 11 was uniformly removed with a slight etching amount, and the surface of the outer circuit 2 was almost flat. Also, in all of Examples 1 to 6, there is a gap between the first carrier metal foil 10 and the second carrier metal foil 11 or between the second carrier metal foil 11 and the base metal foil 12 by handling in the manufacturing process. There was no peeling (“ ⁇ ” in Table 1 indicates no peeling). Further, when peeling between the first carrier metal foil 10 and the second carrier metal foil 11, there was no peeling between the second carrier metal foil 11 and the base metal foil 12.
  • Measurement of the initial peel strength (N / m) before heating / pressurization (before forming the core substrate 17 by laminating the prepreg to be the base material 16) is made of a multilayer metal foil sample cut to a width of 10 mm. Then, using Tensilon RTM-100 (made by Orientec Co., Ltd., trade name, “Tensilon” is a registered trademark), according to JIS Z 0237 90 degree peeling method, One carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction, and then the second carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction.
  • the peel strength after heating and pressurization (after forming the core substrate 17 by laminating the prepreg as the base material 16) was also measured in the same manner as the initial peel strength, and the rate of change relative to the initial value was obtained.
  • the conditions of the heating and pressurization when laminating the multilayer metal foil 9 and the glass epoxy prepreg serving as the base material 16 to form the core substrate 17 are as follows: a pressure of 3 MPa, a temperature of 175.degree. The time is 1.5 hr.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat de boîtier pour le montage d'éléments semi-conducteurs, permettant d'améliorer le rendement par suppression du dépôt de poudre de résine. La surface de ce substrat peut comporter un ensemble de circuits constituant une couche externe par rapport à une couche isolante, l'ensemble de circuits étant très fin et fournissant une excellente force d'adhérence due à la formation de l'ensemble de circuits intégrés sans gravure sous-jacente. En outre, divers types de structures métalliques, telles que des bosses et des colonnes, peuvent être obtenues par la formation d'un ensemble de circuits tridimensionnel à des emplacements arbitraires. Le procédé selon l'invention consiste : à préparer une feuille métallique multicouche comprenant une première feuille métallique de support, une deuxième feuille métallique de support et une feuille métallique de base stratifiées, et à former un substrat central par stratification de la feuille métallique multicouche sur un substrat ; à retirer physiquement la première feuille métallique de support de la feuille métallique multicouche ; à réaliser une première métallisation sélective sur la deuxième feuille métallique de support ; à former un corps stratifié par stratification de la couche isolante sur la première métallisation sélective ; à séparer le corps stratifié et la deuxième feuille métallique de support du substrat central ; et à réaliser une gravure par formation d'une réserve de gravure sur la deuxième feuille métallique de support du corps stratifié séparé.
PCT/JP2011/072423 2010-09-29 2011-09-29 Procédé de fabrication de substrat de boîtier pour montage d'éléments semi-conducteurs WO2012043742A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201180045417.4A CN103119710B (zh) 2010-09-29 2011-09-29 半导体元件搭载用封装基板的制造方法
KR1020137005647A KR101466524B1 (ko) 2010-09-29 2011-09-29 반도체소자 탑재용 패키지 기판의 제조 방법

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2010-218898 2010-09-29
JP2010218898 2010-09-29
JP2011207249A JP5896200B2 (ja) 2010-09-29 2011-09-22 半導体素子搭載用パッケージ基板の製造方法
JP2011-207249 2011-09-22

Publications (1)

Publication Number Publication Date
WO2012043742A1 true WO2012043742A1 (fr) 2012-04-05

Family

ID=45893180

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/072423 WO2012043742A1 (fr) 2010-09-29 2011-09-29 Procédé de fabrication de substrat de boîtier pour montage d'éléments semi-conducteurs

Country Status (5)

Country Link
JP (1) JP5896200B2 (fr)
KR (1) KR101466524B1 (fr)
CN (1) CN103119710B (fr)
TW (1) TWI601245B (fr)
WO (1) WO2012043742A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101436830B1 (ko) 2013-04-30 2014-09-02 대덕전자 주식회사 다기능 회로판 제조 방법
WO2017078849A1 (fr) * 2015-11-06 2017-05-11 Apple Inc. Substrat ultra-mince de support
EP3241415A1 (fr) * 2014-12-30 2017-11-08 Circuit Foil Luxembourg Feuilles de cuivre pelables, procédé de fabrication de substrat sans noyau, et substrat sans noyau obtenu par le procédé de fabrication
JPWO2018003703A1 (ja) * 2016-07-01 2019-05-16 三菱瓦斯化学株式会社 半導体素子搭載用パッケージ基板の製造方法及び半導体素子実装基板の製造方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8970035B2 (en) 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
JP2014072326A (ja) * 2012-09-28 2014-04-21 Hitachi Chemical Co Ltd 半導体素子搭載用パッケージ基板及びその製造方法
KR101448529B1 (ko) * 2013-06-17 2014-10-08 주식회사 심텍 프라이머층을 이용하는 세미어디티브법을 적용하는 인쇄회로기판의 제조 방법
JP6223909B2 (ja) * 2013-07-11 2017-11-01 新光電気工業株式会社 配線基板及びその製造方法
TWI474450B (zh) 2013-09-27 2015-02-21 Subtron Technology Co Ltd 封裝載板及其製作方法
TWI474449B (zh) 2013-09-27 2015-02-21 Subtron Technology Co Ltd 封裝載板及其製作方法
CN104576402B (zh) * 2013-10-18 2017-10-13 旭德科技股份有限公司 封装载板及其制作方法
CN103596362B (zh) * 2013-11-08 2016-08-31 溧阳市江大技术转移中心有限公司 一种具有交错间隔的合金柱的印刷电路板
CN105746003B (zh) * 2013-11-22 2018-12-21 三井金属矿业株式会社 具有包埋电路的印刷线路板的制造方法及用该制造方法得到的印刷线路板
KR101557574B1 (ko) * 2014-03-07 2015-10-05 주식회사 심텍 내장형 지지 구조물을 구비하는 인쇄회로기판 및 이의 제조 방법
KR101597996B1 (ko) * 2014-05-22 2016-02-29 대덕전자 주식회사 회로기판 및 제조방법
JP6493404B2 (ja) * 2014-07-18 2019-04-03 三菱瓦斯化学株式会社 積層体の製造方法及び半導体素子搭載用基板の製造方法
WO2016067422A1 (fr) 2014-10-30 2016-05-06 三井金属鉱業株式会社 Feuille de cuivre avec support et procédé de fabrication de circuit imprimé utilisant ladite feuille
TWI573230B (zh) * 2015-06-26 2017-03-01 矽品精密工業股份有限公司 封裝件及其封裝基板
KR101893503B1 (ko) * 2016-05-27 2018-08-30 (주) 화인켐 미세배선용 연성 회로 기판 및 이의 제조방법
CN109315069B (zh) * 2016-07-07 2021-01-08 名幸电子有限公司 立体配线基板、立体配线基板的制造方法及立体配线基板用基材
JP7172597B2 (ja) * 2016-08-05 2022-11-16 三菱瓦斯化学株式会社 支持基板、支持基板付積層体及び半導体素子搭載用パッケージ基板の製造方法
KR102023729B1 (ko) * 2017-08-23 2019-09-23 (주)심텍 인쇄회로기판 및 그 제조 방법
CN108718485B (zh) * 2018-06-07 2021-02-02 珠海元盛电子科技股份有限公司 一种制造细线厚铜双面fpc的半加成法技术
CN113811093A (zh) * 2021-08-09 2021-12-17 广州方邦电子股份有限公司 金属箔、覆铜层叠板、线路板及线路板的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127429A (ja) * 1999-10-25 2001-05-11 Hitachi Chem Co Ltd 多層印刷配線板の製造方法
JP2008218450A (ja) * 2007-02-28 2008-09-18 Shinko Electric Ind Co Ltd 配線基板の製造方法及び電子部品装置の製造方法
JP2010093286A (ja) * 2009-12-15 2010-04-22 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2010098086A (ja) * 2008-10-16 2010-04-30 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2010199616A (ja) * 2010-05-12 2010-09-09 Shinko Electric Ind Co Ltd 配線基板の製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3973197B2 (ja) * 2001-12-20 2007-09-12 三井金属鉱業株式会社 キャリア箔付電解銅箔及びその製造方法
JP4273895B2 (ja) * 2003-09-24 2009-06-03 日立化成工業株式会社 半導体素子搭載用パッケージ基板の製造方法
CN100481403C (zh) * 2005-03-17 2009-04-22 日立电线株式会社 电子装置用基板及其制造方法以及电子装置制造方法
JP5410660B2 (ja) * 2007-07-27 2014-02-05 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置及びその製造方法
KR20100065689A (ko) * 2008-12-08 2010-06-17 삼성전기주식회사 금속범프를 갖는 인쇄회로기판 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127429A (ja) * 1999-10-25 2001-05-11 Hitachi Chem Co Ltd 多層印刷配線板の製造方法
JP2008218450A (ja) * 2007-02-28 2008-09-18 Shinko Electric Ind Co Ltd 配線基板の製造方法及び電子部品装置の製造方法
JP2010098086A (ja) * 2008-10-16 2010-04-30 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2010093286A (ja) * 2009-12-15 2010-04-22 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2010199616A (ja) * 2010-05-12 2010-09-09 Shinko Electric Ind Co Ltd 配線基板の製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101436830B1 (ko) 2013-04-30 2014-09-02 대덕전자 주식회사 다기능 회로판 제조 방법
EP3241415A1 (fr) * 2014-12-30 2017-11-08 Circuit Foil Luxembourg Feuilles de cuivre pelables, procédé de fabrication de substrat sans noyau, et substrat sans noyau obtenu par le procédé de fabrication
WO2017078849A1 (fr) * 2015-11-06 2017-05-11 Apple Inc. Substrat ultra-mince de support
US9899239B2 (en) 2015-11-06 2018-02-20 Apple Inc. Carrier ultra thin substrate
JP2018533848A (ja) * 2015-11-06 2018-11-15 アップル インコーポレイテッドＡｐｐｌｅ Ｉｎｃ． キャリア超薄型基板
JPWO2018003703A1 (ja) * 2016-07-01 2019-05-16 三菱瓦斯化学株式会社 半導体素子搭載用パッケージ基板の製造方法及び半導体素子実装基板の製造方法
EP3480843A4 (fr) * 2016-07-01 2019-06-19 Mitsubishi Gas Chemical Company, Inc. Procédé de fabrication d'un substrat de boîtier permettant de porter un élément semi-conducteur, et procédé de fabrication d'un substrat monté sur un élément semi-conducteur
US10727081B2 (en) 2016-07-01 2020-07-28 Mitsubishi Gas Chemical Company, Inc. Method for manufacturing package substrate for mounting a semiconductor device, and method for manufacturing semiconductor device mounting substrate
TWI718316B (zh) * 2016-07-01 2021-02-11 日商三菱瓦斯化學股份有限公司 半導體元件搭載用封裝基板之製造方法及半導體元件安裝基板之製造方法
JP7044997B2 (ja) 2016-07-01 2022-03-31 三菱瓦斯化学株式会社 半導体素子搭載用パッケージ基板の製造方法及び半導体素子実装基板の製造方法

Also Published As

Publication number Publication date
JP5896200B2 (ja) 2016-03-30
JP2012094840A (ja) 2012-05-17
TW201218323A (en) 2012-05-01
CN103119710A (zh) 2013-05-22
CN103119710B (zh) 2015-11-25
TWI601245B (zh) 2017-10-01
KR101466524B1 (ko) 2014-11-27
KR20130043684A (ko) 2013-04-30

Similar Documents

Publication Publication Date Title
JP5896200B2 (ja) 半導体素子搭載用パッケージ基板の製造方法
US10117336B2 (en) Method of manufacturing a wiring substrate
CN106409688B (zh) 一种超薄无芯封装基板的加工方法和结构
JP2012216824A (ja) 半導体素子搭載用パッケージ基板の製造方法
JP5473838B2 (ja) 支持体金属箔付き複合金属層、これを用いた配線板とその製造方法、この配線板を用いた半導体パッケージの製造方法
CN106340461B (zh) 一种超薄无芯封装基板的加工方法和结构
JP2012212818A (ja) 電子部品内蔵基板及びその製造方法
WO2012121373A1 (fr) Procédé de production d'un substrat de boîtier pour le montage d'un élément à semi-conducteur, substrat de boîtier pour le montage d'un élément à semi-conducteur et boîtier à semi-conducteur
KR20120085673A (ko) 다층 배선기판
JP2006019591A (ja) 配線基板の製造方法および配線基板
CN103489796B (zh) 元件内埋式半导体封装件的制作方法
JP5672524B2 (ja) 半導体素子搭載用パッケージ基板の製造方法
TWI727506B (zh) 半導體封裝的製造方法及使用於彼的黏著片
JP2008004862A (ja) プリント配線板及びその製造方法
JP5716948B2 (ja) 半導体素子搭載用パッケージ基板の製造方法
TW201437436A (zh) 帶載體極薄銅箔、貼銅積層板及無芯基板
JP6689691B2 (ja) 配線基板及びその製造方法
JP2008227538A (ja) 配線基板の製造方法、及び配線基板
JP2014072326A (ja) 半導体素子搭載用パッケージ基板及びその製造方法
JP2005072085A (ja) 配線基板の製造方法、及び配線基板
JP2023074750A (ja) 多層配線基板および多層配線基板の製造方法
JP2011159695A (ja) 半導体素子搭載用パッケージ基板及びその製造方法
KR20090065617A (ko) 초박판형 패키지 기판 제조 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180045417.4

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11829295

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20137005647

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11829295

Country of ref document: EP

Kind code of ref document: A1