WO2011152051A1 - ウェーハの汚染防止方法、検査方法および製造方法 - Google Patents

ウェーハの汚染防止方法、検査方法および製造方法 Download PDF

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Publication number
WO2011152051A1
WO2011152051A1 PCT/JP2011/003094 JP2011003094W WO2011152051A1 WO 2011152051 A1 WO2011152051 A1 WO 2011152051A1 JP 2011003094 W JP2011003094 W JP 2011003094W WO 2011152051 A1 WO2011152051 A1 WO 2011152051A1
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Prior art keywords
wafer
quality inspection
silicon wafer
back surface
contamination
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PCT/JP2011/003094
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English (en)
French (fr)
Japanese (ja)
Inventor
栄治 神山
健司 青木
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株式会社Sumco
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Priority to KR1020127034315A priority Critical patent/KR101356400B1/ko
Priority to JP2012518256A priority patent/JP5500249B2/ja
Priority to DE112011101877.0T priority patent/DE112011101877B4/de
Publication of WO2011152051A1 publication Critical patent/WO2011152051A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67219—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices

Definitions

  • the present invention relates to a wafer contamination prevention method, an inspection method, and a manufacturing method, and more particularly, to prevent wafer-to-wafer cross-contamination (cross-contamination) in a manufactured wafer quality inspection process, and thus to reduce the contamination of the wafer.
  • the present invention relates to a wafer contamination prevention method, inspection method, and manufacturing method that can be obtained.
  • a silicon wafer for example, a polished wafer is manufactured as follows. That is, single crystal silicon is grown by the Czochralski method (CZ method), etc., and after the silicon single crystal is cut into blocks, it is sliced thinly, rough polishing (lapping) process, etching process, mirror polishing (polishing) process After the final cleaning, various inspections are performed, and if no abnormality is confirmed, the product is completed and shipped.
  • CZ method Czochralski method
  • an object of the present invention is to propose a method for advantageously avoiding the problem of contamination particularly in a silicon wafer subjected to DSP processing.
  • the inventors have first intensively studied the cause of contamination in a silicon wafer after inspection. As a result, there is a source of contamination at the edge of the wafer, which is particularly a cross contamination in the quality inspection process. It has come to be found that the generation of is a major factor.
  • the wafer edge is complex in the evaluation and analysis method and inferior in detection capability. For this reason, it is not as easy to remove the contamination at the wafer edge as the main surface, and the wafer edge may not be completely removed even after the final cleaning step.
  • the edge of the silicon wafer is held from the DSP process to the previous process of the quality inspection process, and the back surface is held in the quality inspection process.
  • the inventors have found that it is effective for preventing contamination, and have completed the present invention.
  • the wafer contamination prevention method of the present invention in the silicon wafer production line, when the double-side polished silicon wafer is transported to the quality inspection process and quality inspection is performed in the quality inspection process, An end portion of the silicon wafer is held, and the back surface of the silicon wafer is held in the quality inspection step.
  • the back surface of the silicon wafer is held by vacuum adsorption or electrostatic adsorption.
  • the wafer contamination prevention method of the present invention is characterized in that an oxide film is formed on at least the back surface of the main surface and back surface of the silicon wafer before the quality inspection step.
  • the oxide film has a thickness of 5 to 1000 angstroms.
  • the wafer inspection method of the present invention is a pre-process of the quality inspection process when the silicon wafer after the double-side polishing is transported to the quality inspection process in the silicon wafer production line and the quality inspection is performed in the quality inspection process. Then, the end of the silicon wafer is held, and the back surface of the silicon wafer is held in the quality inspection step.
  • the back surface of the silicon wafer is held by vacuum adsorption or electrostatic adsorption.
  • an oxide film is formed on at least the back surface of the main surface and the back surface of the silicon wafer before the quality inspection step.
  • the thickness of the oxide film is 5 to 1000 angstroms.
  • the wafer manufacturing method of the present invention is a silicon wafer manufacturing method in which a double-side polishing process is performed on a silicon wafer cut out from a silicon ingot, and a quality inspection step is performed thereafter.
  • the edge part of a silicon wafer is hold
  • the back surface of the silicon wafer is held by vacuum adsorption or electrostatic adsorption.
  • an oxide film is formed on at least the back surface of the main surface and back surface of the silicon wafer before the quality inspection step.
  • the oxide film has a thickness of 5 to 1000 angstroms.
  • the wafer edge is not retained during the wafer quality inspection process. Therefore, it is possible to prevent the occurrence of cross contamination between the wafers, and as a result, a wafer with reduced contamination can be obtained.
  • FIG. 1 It is a figure which shows the flowchart of an example of the manufacturing method of the wafer of this invention. It is a figure which shows MCL of the (a) edge part and (b) back surface of a 300 mm silicon wafer by the contamination prevention method of this invention. It is a figure which shows MCL of the (a) edge part and (b) back surface of a 200 mm silicon wafer by the conventional method. It is a figure which shows MCL of the (a) edge part and (b) back surface of a 300 mm silicon wafer by the conventional method.
  • the wafer contamination prevention method of the present invention is the above-described silicon wafer production line, wherein the DSP-processed silicon wafer is transported to a quality inspection apparatus after the final cleaning process, and when the quality inspection is performed in the quality inspection process, An end of the silicon wafer is held in a pre-process of the quality inspection process, and a back surface of the silicon wafer is held in the quality inspection process.
  • the wafer contamination prevention method of the present invention only the edge of the wafer is held in all steps after the DSP processing step and before the quality inspection step, and the holding means is switched in the next wafer quality inspection step. It is important to prevent cross contamination. As a result, even if the wafer edge is contaminated after the DSP processing, the contaminated portion at the edge is not touched in the quality inspection process, so that cross contamination in the inspection process can be prevented.
  • the method of holding the edge of the wafer in the process after the DSP processing is to carry out processing and transporting by holding three or more appropriate locations.
  • the method for holding the back surface of the wafer can employ, for example, vacuum suction holding using a known vacuum chuck or electrostatic suction holding using a known electrostatic chuck, From the viewpoint of preventing particles from adhering to the back surface of the wafer, it is preferable to employ vacuum suction holding. At that time, an appropriate position is sucked and held so as not to cause the wafer to be bent or the like which affects the quality inspection of the wafer.
  • the back surface subjected to the DSP treatment is held by vacuum suction, for example, contact marks may remain on the back surface.
  • This contact mark is caused by a microscopic structural change of the wafer surface due to the holding part coming into contact with the back surface of the wafer. For example, contamination or defects such as metal occur to reduce the device yield. Therefore, it does not affect the contamination prevention method of the present invention.
  • the wafer edge is closer to the surface of the main surface, which is the device forming portion, and contamination due to cross contamination becomes resident there, it can be a major cause of a decrease in device yield.
  • the protection performance of the back surface against contact marks can be improved by coating at least the back surface of the main surface and back surface of the wafer with a protective material such as an oxide film in advance.
  • a protective material such as an oxide film in advance.
  • the oxide film include a natural oxide film obtained by leaving the wafer in the atmosphere and a thermal oxide film formed by performing various heat treatments. Further, the oxide film may be formed by, for example, SC-1 cleaning or ozone cleaning of the wafer. Furthermore, an oxide film can be formed on the back surface of the wafer by spraying ozone water on the back surface of the wafer using a single wafer cleaning machine. Thereafter, when the back surface of the wafer is vacuum-adsorbed, contact marks remain on the back-side oxide film formed as described above. After the inspection process is completed, for example, hydrofluoric acid cleaning and / or subsequent alkali cleaning is performed. Contact marks can be removed by removing the oxide film.
  • the thickness of the oxide film is 5 to 1000 angstroms. If the thickness is less than 5 angstroms, the oxide film is thin, so that contact marks remain on the back surface of the wafer after the oxide film is removed. On the other hand, if it exceeds 1000 angstroms, the formation time of the oxide film becomes long and the productivity decreases.
  • a preferable thickness of the oxide film is 5 to 20 angstroms. If it is this range, after removing an oxide film, it can prevent that a contact trace remains on the wafer back surface, and can prevent the fall of productivity.
  • Cross contamination between wafers can be prevented by the above-described wafer contamination prevention method, that is, by holding the wafer end until the quality inspection pre-process and holding the wafer back surface in the quality inspection process.
  • a defect occurs before the quality inspection, and the contaminated wafer flows to the inspection process, or a wafer with a low cleanliness level is erroneously measured by an inspection device due to human error.
  • the wafer back surface holder of the inspection apparatus may be contaminated due to the above factors. Even if such contamination occurs, the wafer holding position is set as described above so that the contamination on the wafer back surface holder is cleaned by a highly clean wafer. The cleanliness of the wafer back surface holder can be recovered.
  • the wafer inspection method of the present invention is characterized in that the wafer end is held until the previous process of quality inspection, and the wafer back surface is held in the quality inspection process, thereby preventing cross contamination between wafers. Have. Therefore, the specific processing other than the wafer holding position in the inspection process is not limited at all. Specifically, the flatness, the number of particles, damage, contamination, etc. of the cleaned silicon wafer are inspected. As an example, a method for inspecting the flatness of a wafer and the number of particles on the wafer surface will be described below.
  • the flatness of the wafer can be measured using a flatness measuring instrument such as a capacitance method or an optical method.
  • a capacitance type measuring instrument the front and back surfaces of the silicon wafer to be inspected are sandwiched between two probes, and the capacitance between the probe and the wafer is obtained while rotating the wafer, The thickness of the wafer is measured from the difference in distance from the probe to the front and back surfaces of the wafer, and the flatness is calculated from the obtained thickness.
  • an optical flatness measuring instrument interference fringes generated by the phase difference between the reflected light from the reference surface and the reflected light from the wafer surface are detected by a CCD camera, and the level of the wafer surface is detected. Measure the difference directly.
  • Particles and crystal defects existing on the surface of the silicon wafer are inspected by a particle inspection apparatus.
  • the surface of the wafer to be inspected is irradiated with laser light, the intensity of the scattered laser light is detected as signal light by a particle inspection apparatus, and the defect is identified as a bright spot defect (Light) using the intensity of this signal light.
  • Point Defects hereinafter referred to as “LPD”.
  • LPD Point Defects
  • the wafer end is held until the quality inspection pre-process, and the wafer back surface is held in the quality inspection process, thereby cross-contamination between the wafers. It has the feature to prevent. Therefore, there is no limitation on specific processing other than the wafer holding position in the manufacturing process.
  • FIG. 1 an example of the manufacturing method of the silicon wafer of this invention is shown.
  • step S1 for example, the Czochralski (CZ) method is used to melt the polycrystalline silicon charged in the quartz crucible to about 1400 ° C., and then the seed crystal is immersed in the liquid surface and pulled up while rotating. To produce a silicon ingot.
  • CZ Czochralski
  • the oxygen concentration in the silicon ingot can be controlled by using a magnetic field application Czochralski (MCZ) method in which a magnetic field is applied during manufacture of the ingot.
  • MCZ magnetic field application Czochralski
  • step S2 after the outer periphery grinding process of the obtained silicon ingot is performed to make the diameter uniform, the silicon ingot is sliced to a thickness of about 1 mm using a wire saw or an inner peripheral cutting machine. Get a wafer.
  • step S3 the obtained silicon wafer is transferred to a polishing apparatus, and lapping is performed on the silicon wafer using an alumina abrasive or the like.
  • the thickness of the wafer can be set to a predetermined value, and the parallelism of the front and back surfaces of the wafer can be increased.
  • step S4 acid etching using an aqueous solution consisting of at least one of hydrofluoric acid, nitric acid, acetic acid, and phosphoric acid, or alkaline etching using an aqueous potassium hydroxide solution or an aqueous sodium hydroxide solution, or the above acid etching
  • aqueous solution consisting of at least one of hydrofluoric acid, nitric acid, acetic acid, and phosphoric acid
  • alkaline etching using an aqueous potassium hydroxide solution or an aqueous sodium hydroxide solution, or the above acid etching
  • step S5 a mirror polishing process is performed on the silicon wafer subjected to the etching process using a polishing apparatus.
  • DSP processing for polishing both surfaces of the wafer is performed. That is, a silicon wafer is fitted into a carrier, the wafer is sandwiched between an upper surface plate and a lower surface plate with a polishing cloth, and a slurry such as colloidal silica is poured between the upper and lower surface plates and the wafer, The carriers are rotated in opposite directions to perform mirror polishing on both sides of the silicon wafer. Thereby, the unevenness
  • step S6 the silicon wafer that has been subjected to the double-side polishing treatment is transferred to a cleaning process.
  • the SC-1 cleaning solution that is a mixture of ammonia water, hydrogen peroxide water, and water, hydrochloric acid, hydrogen peroxide Particles, organic matter, metals, etc. on the wafer surface are removed using SC-2 cleaning liquid which is water and a mixture of water.
  • step S7 the cleaned silicon wafer is transferred to an inspection process, and the flatness of the wafer, the number of LPDs on the wafer surface, damage, contamination of the wafer surface, etc., as in the above-described inspection process of the present invention.
  • the wafer when holding the wafer after being transported to the inspection process, it is important to adsorb the back surface, not the end portion of the wafer. Only wafers satisfying a predetermined quality in this inspection process are shipped as products.
  • an annealing wafer, an epitaxial wafer, or an SOI (Silicon On Insulator) wafer can be obtained by subjecting the wafer obtained in the above steps to an annealing process or an epitaxial film growth process as necessary. .
  • a silicon wafer having a diameter of 300 mm obtained by slicing a grown silicon single crystal and performing DSP processing according to the steps from Step S1 to Step S5 in FIG. 1 is quality after the DSP processing (Step S5).
  • the process up to the previous process of the inspection process is held and processed and transferred.
  • the wafer is cleaned in the final cleaning process (step S6), the wafer is transferred to the particle inspection apparatus in the quality inspection process (step S7). Particles were inspected by holding the back surface by vacuum suction. Thereafter, MCL (Metal Conjugation Level) on the back surface and the edge of the silicon wafer was analyzed.
  • MCL Metal Conjugation Level
  • the main surface and the back surface of the wafer are cleaned using SC-1 cleaning liquid to form an oxide film having a thickness of about 10 angstroms on the main surface and the back surface of the wafer.
  • the back surface of the wafer was held by vacuum suction with the oxide film formed on the back surface of the wafer.
  • the oxide films formed on the main surface and the back surface of the wafer were removed by hydrofluoric acid cleaning and subsequent alkali cleaning after the quality inspection process (step S7).
  • an alkaline cleaning liquid (SC-1 cleaning liquid) mainly composed of ammonia and hydrogen peroxide was used.
  • FIG. 2 is a diagram in which an example of the result of analyzing the MCL is plotted, and shows the MCL on the (a) end portion and (b) the back surface of the silicon wafer.
  • the process was performed in units of 25 cassettes, and 27 wafers extracted one by one after the quality inspection were evaluated. Although each of the measurement points includes analysis variations, it is considered that the contamination level is observed up to the previous process of the quality inspection process. As can be seen from this figure, the amount of contamination is dragged to the wafer to be inspected thereafter in the case of MCL that is one digit higher as seen on the back side of FIG. 3B and the end of FIG. 4A.
  • step S7 it can be seen that there is no memory effect, and that each lot varies independently and no cross contamination occurs. Further, since the back surface of the mirror-polished wafer is vacuum-sucked, it can be seen from FIG. 2B that the amount of contamination on the back surface of the wafer is within a normal value range. In this way, even if the wafer back surface adsorption part of the quality inspection device is contaminated due to the above-mentioned measurement of a wafer with a low cleanliness level as described above, the back surface is always cleaned up. Since the wafer is put into the inspection apparatus, the back surface adsorption portion of the apparatus can be kept clean by the self-cleaning action. Further, it was confirmed that no contact mark remained on the back surface of the wafer from which the oxide film was removed after the quality inspection process (step S7).
  • a silicon wafer having a diameter of 200 mm obtained by slicing a grown silicon single crystal and subjected to a DSP treatment is processed by holding a “back surface” from the SSP (Single Side Polishing) process to the previous process of the quality inspection process. After carrying the wafer and cleaning the wafer in the final cleaning step, the wafer was transferred to the particle inspection device in the quality inspection step, and the “back surface” of the silicon wafer was held to inspect the particles. Thereafter, the MCL on the back surface and the edge of the silicon wafer was analyzed. In the same way as described above, the MCL analysis wafers were processed in units of 25 cassettes, and all 27 wafers extracted one after the quality inspection were evaluated.
  • SSP Single Side Polishing
  • FIG. 3 is a diagram in which the results are plotted in chronological order, and shows (a) the end portion and (b) the back surface MCL of the silicon wafer. From this result, it is considered that cross-contamination occurred earlier or earlier in this time series. Further, as is clear from FIG. 3B, unlike the case where the fluctuations are independently made for each lot as shown in FIG. 2, contamination occurs on the back surface of the wafer before the quality inspection process. In this case as well, it can be seen that the influence of contamination remains on the back surface of wafers from a contaminated wafer to several lots.
  • Comparative Example 2 Slicing the grown silicon single crystal and holding the “edge” of the 300 mm diameter silicon wafer that has been subjected to DSP processing, which is a new processing method than SSP, from the DSP processing to the pre-process of the quality inspection process Then, after processing and transporting and cleaning the wafer in the final cleaning step, the wafer was transported to the particle inspection device in the quality inspection step, and the “edge” of the silicon wafer was held to inspect the particles. Thereafter, the MCL on the back surface and the edge of the silicon wafer was analyzed. In the same way as described above, the MCL analysis wafers were processed in units of 25 cassettes, and all 27 wafers extracted one after the quality inspection were evaluated.
  • FIG. 4 is a diagram in which the results are plotted in chronological order, and shows (a) the end portion and (b) the back surface MCL of the silicon wafer.
  • FIG. 4 (a) unlike the case where each lot varies independently as shown in FIG.
  • the wafer is held in a state where the MCL at the end is high, and the influence of the wafer having the high MCL remains, so that it is estimated that cross contamination occurs.
  • high-speed wafer handling is required, and wear at the end is remarkable, and there is a concern about generation of dust due to long-term use.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
PCT/JP2011/003094 2010-06-01 2011-06-01 ウェーハの汚染防止方法、検査方法および製造方法 WO2011152051A1 (ja)

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Application Number Priority Date Filing Date Title
KR1020127034315A KR101356400B1 (ko) 2010-06-01 2011-06-01 웨이퍼의 오염 방지 방법, 검사 방법 및 제조 방법
JP2012518256A JP5500249B2 (ja) 2010-06-01 2011-06-01 ウェーハの汚染防止方法、検査方法および製造方法
DE112011101877.0T DE112011101877B4 (de) 2010-06-01 2011-06-01 Verfahren zur Verhinderung von Kontamination von Wafern und Verfahren zur Herstellung von Wafern

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JP2010-125734 2010-06-01
JP2010125734 2010-06-01

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US9634160B2 (en) 2011-12-16 2017-04-25 Lg Electronics Inc. Solar cell and method for manufacturing the same

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