WO2011134389A1 - Ffs型tft-lcd阵列基板的制造方法 - Google Patents

Ffs型tft-lcd阵列基板的制造方法 Download PDF

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Publication number
WO2011134389A1
WO2011134389A1 PCT/CN2011/073335 CN2011073335W WO2011134389A1 WO 2011134389 A1 WO2011134389 A1 WO 2011134389A1 CN 2011073335 W CN2011073335 W CN 2011073335W WO 2011134389 A1 WO2011134389 A1 WO 2011134389A1
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Prior art keywords
photoresist
region
film
array substrate
remaining
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PCT/CN2011/073335
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English (en)
French (fr)
Inventor
宋泳錫
崔承镇
刘圣烈
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北京京东方光电科技有限公司
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Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Priority to KR1020117031558A priority Critical patent/KR101279982B1/ko
Priority to EP18208581.1A priority patent/EP3483926B1/en
Priority to JP2013506471A priority patent/JP5868949B2/ja
Priority to US13/381,157 priority patent/US8603843B2/en
Priority to EP11774380.7A priority patent/EP2565916B1/en
Publication of WO2011134389A1 publication Critical patent/WO2011134389A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • the present invention relates to a method of fabricating an FFS type TFT-LCD array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • FPD main flat panel display
  • the TFT-LCD is divided into a vertical electric field type and a horizontal electric field type.
  • the vertical electric field type TFT-LCD needs to form a pixel electrode on the array substrate and form a common electrode on the color filter substrate; however, the horizontal electric field type TFT-LCD needs to simultaneously form the pixel electrode and the common electrode on the array substrate. Therefore, when fabricating an array substrate of a horizontal electric field type TFT-LCD, it is necessary to additionally add a mask process for forming a common electrode with respect to the array substrate of the vertical electric field type TFT-LCD.
  • the vertical electric field type TFT-LCD includes: Twist Nematic (TN) type TFT-LCD; horizontal electric field type TFT-LCD includes: Fringe Field Switching (FFS) type TFT-LCD, In-Plane Switching (referred to as IPS) type TFT-LCD.
  • FFS Fringe Field Switching
  • IPS In-Plane Switching
  • the horizontal electric field type TFT-LCD, especially the FFS type TFT-LCD, has the advantages of wide viewing angle and high aperture ratio, and is widely used in the field of liquid crystal displays.
  • the FFS type TFT-LCD array substrate is formed by forming a structural pattern by a plurality of patterning processes, and each of the patterning processes includes exposing, developing, etching, and stripping the remaining photoresist, etc., using a mask, respectively.
  • the etching process includes dry etching and wet etching. Therefore, the number of patterning processes can measure the complexity of fabricating a TFT-LCD array substrate, and reducing the number of patterning processes means a reduction in manufacturing cost.
  • the prior art six patterning processes include: common electrode patterning, gate and gate electrode patterning, active layer patterning, source/drain electrode patterning, via patterning, and pixel electrode patterning.
  • Step 1 Depositing a first transparent conductive film, and forming a pattern of a plate-shaped common electrode through a common mask;
  • Step 2 depositing a first metal film, forming a gate line, a gate electrode, and a common power using a common mask The pattern of the polar line;
  • Step 3 sequentially depositing a first insulating film, a semiconductor film, a doped semiconductor film, and a second metal film, forming an active layer (a semiconductor layer and a doped semiconductor layer), a TFT channel by using a dual tone mask , a pattern of source electrodes, drain electrodes, and data lines;
  • Step 4 depositing a second insulating film, forming a pattern of via holes by using a second double-mask, forming a pattern of connection holes in a gate line region of the PAD region, a data line region of the PAD region, and a common electrode line region of the PAD region;
  • Step 5 Depositing a second transparent conductive film to form a pattern of slit pixel electrodes by a common mask.
  • An embodiment of the present invention provides a method for fabricating an FFS type TFT-LCD array substrate, comprising: Step 1: sequentially forming a first transparent conductive film, a first metal film, and a doped semiconductor film on a transparent substrate, and then Forming a stack of the first transparent conductive film, the first metal film, and the doped semiconductor film to form a pattern including a source electrode, a drain electrode, a data line, and a pixel electrode; Step 2: forming a semiconductor film, Patterning the semiconductor film to form a pattern of the doped semiconductor layer and a pattern of the semiconductor layer including the TFT channel; Step 3: forming an insulating film and a second metal film, and the insulating film and the second metal film The layer is patterned to form a pattern including a PAD region data line connection hole, a gate line, a gate electrode, and a common electrode line; Step 4, forming a second transparent conductive film, and patterning the second transparent conductive film to form a common The pattern of the electrodes
  • Another embodiment of the present invention provides a method for fabricating an FFS type TFT-LCD array substrate, comprising: Step 1: sequentially forming a first transparent conductive film, a first metal film, and a doped semiconductor film on a transparent substrate, Forming a stack of the first transparent conductive film, the first metal film, and the doped semiconductor film to form a pattern including a source electrode, a drain electrode, a data line, and a pixel electrode; Step 2: forming a semiconductor film, Forming the semiconductor film to form a pattern of the doped semiconductor layer and a pattern of the semiconductor layer including the TFT channel; Step 3': forming an insulating film and a second metal film, and the insulating film and the second metal film Patterning is performed, and then a second transparent conductive film is formed, and a ground lift-off process and an etching process are performed to form a pattern of the data line connection hole, the gate line, the gate electrode, and the common electrode line of the PAD region.
  • a further embodiment of the present invention provides a method for fabricating an FFS type TFT-LCD array substrate, comprising: Step 100: sequentially forming a semiconductor film and a doped semiconductor film on the transparent substrate, and the semiconductor film and the doping Forming a laminate of the semiconductor film to form a pattern including the semiconductor layer and the doped semiconductor layer; Step 200: forming a first transparent conductive film and a first metal film, the first transparent conductive film and the first metal film The layer is patterned to form a pattern including a source electrode, a drain electrode, a doped semiconductor layer, a TFT channel, a data line, and a pixel electrode; Step 300: forming an insulating film, patterning the insulating film, and forming a PAD region a pattern of the data line connecting holes; step 400, forming a second transparent conductive film and a second metal film, patterning the stack of the second transparent conductive film and the second metal film, forming a gate line, a gate electrode And the pattern of the common electrode.
  • FIG. 1 is a plan view showing a FFS type TFT-LCD array substrate
  • FIG. 2A is a cross-sectional view taken along line AA of FIG. 1, showing a cross-sectional view of a pixel region
  • FIG. 2B is a cross-sectional view of a data line of a PAD region of an FFS type TFT-LCD array substrate
  • FIG. 2C is an FFS type TFT- a cross-sectional view of a gate line of a PAD region of an LCD array substrate;
  • FIG. 3 is a flow chart of fabricating an FFS type TFT-LCD array substrate according to Embodiment 1 of the present invention
  • FIGS. 4A-4C are cross-sectional views of depositing a first transparent conductive film, a first metal film, and a doped semiconductor film on a transparent substrate
  • Figure 4A is a cross-sectional view of the pixel region
  • Figure 4B is a cross-sectional view of the gate line of the PAD region
  • Figure 4C is a cross-sectional view of the data line of the PAD region
  • Figure 5A - Figure 5C is a diagram 4A- FIG. 4C is a cross-sectional view of the structure after the photoresist is coated and exposed and developed
  • FIGS. 4A-4C are cross-sectional views of depositing a first transparent conductive film, a first metal film, and a doped semiconductor film on a transparent substrate
  • Figure 4A is a cross-sectional view of the pixel region
  • Figure 4B is a cross
  • FIGS. 6A-6C are cross-sectional views showing the structure of FIGS. 5A-5C after etching;
  • FIG. 7A to FIG. 7C are cross-sectional views showing the photoresist of FIG. 6A to FIG. 6C after ashing;
  • FIG. 8A- FIG. 8C is a cross-sectional view showing the structure of FIGS. 7A to 7C after etching;
  • FIG. 9A to FIG. 9C are cross-sectional views after peeling off the photoresist of FIGS. 8A to 8C;
  • FIGS. 10A-10C are cross-sectional views of the semiconductor thin film deposited on the structure of FIGS. 9A-9C;
  • FIGS. 11A-11C are the exposure and development processes after the photoresist is applied to the structure of FIGS. 10A-10C. Sectional view;
  • FIGS. 11A-11C are cross-sectional views showing the etching process of the structure of FIGS. 11A-11C; 13A to 13C are cross-sectional views after peeling off the photoresist of Figs. 12A to 12C;
  • FIGS. 14A to 14C are cross-sectional views showing the structure of Figs. 13A to 13C after depositing an insulating film and a second metal film;
  • FIGS. 15A-15C are cross-sectional views showing a photoresist coated on the structure of Figs. 14A to 14C and subjected to exposure and development processing;
  • FIGS. 16A to FIG. 16C are cross-sectional views showing the etching process of the structure of FIGS. 15A to 15C;
  • FIGS. 17A to 17C are cross-sectional views showing the photoresist of FIGS. 16A to 16C after the ashing process;
  • 18A-FIG. 18C are cross-sectional views of the photoresist of FIGS. 17A-17C after etching process;
  • FIGS. 19A-19C are cross-sectional views of the photoresist of FIGS. 18A-18C after being stripped;
  • 20A to 20C are cross-sectional views showing the deposition of a second transparent conductive film on the structure of Figs. 19A to 19C;
  • 21A-21C are cross-sectional views of the structure of FIGS. 20A-20C after being coated with a photoresist and subjected to exposure and development processing;
  • FIGS. 22A to 22C are cross-sectional views showing the structure of Figs. 21A to 21C after etching;
  • FIG. 23A to Fig. 23C are cross-sectional views after stripping the photoresist of Figs. 22A to 22C;
  • Figure 24 is a flow chart showing the fabrication of an FFS type TFT-LCD array substrate according to Embodiment 2 of the present invention
  • Figures 25A to 25C are cross-sectional views showing the deposition of an insulating film and a second metal film on the structure of Figures 13A to 13C;
  • 26A to 26C are cross-sectional views after exposure and development processing after applying a photoresist on the structures of Figs. 25A to 25C;
  • FIGS. 26A-26C are cross-sectional views showing the structure of FIGS. 26A to 26C after etching
  • FIG. 28A to FIG. 28C are cross-sectional views showing the photoresist of FIG. 27A to FIG. 27C after ashing
  • FIG. 29A- FIG. 29C is a cross-sectional view showing the structure of FIGS. 28A to 28C after etching
  • FIG. 30A to FIG. 30C are cross-sectional views showing the structure of FIGS. 29A to 29C after ashing
  • FIG. 31 A- 31 C is a cross-sectional view after depositing a second transparent conductive film on the structures of FIGS. 30A to 30C;
  • 32A to 32C are cross-sectional views after the ground stripping process is performed on the structures of Figs. 31A to 31C;
  • FIG. 33A to 33C are cross-sectional views showing an etching process of the structure of Figs. 32A to 32C; and Fig. 34 is a flow chart showing the fabrication of an FFS type TFT-LCD array substrate according to Embodiment 3 of the present invention; 35A to 35C are cross-sectional views showing a semiconductor film and a doped semiconductor film deposited on a transparent substrate, wherein FIG. 35A is a cross-sectional view of a pixel region, and FIG. 35B is a cross-sectional view of a gate line of the PAD region. 35C is a cross-sectional view of the data line of the PAD region;
  • 36A to 36C are cross-sectional views after exposure and development processing after applying a photoresist on the structures of Figs. 35A to 35C;
  • FIG. 37A-37C are cross-sectional views showing the etching process of the structure of Figs. 36A-36C;
  • FIGs. 38A-38C are cross-sectional views of the photoresist after stripping the Figs. 37A-37C;
  • 39A-39C are cross-sectional views showing the deposition of the first transparent conductive film and the first metal film on the structures of Figs. 38A-38C;
  • 40A to 40C are cross-sectional views after exposure and development processing after applying a photoresist on the structures of Figs. 39A to 39C;
  • FIGS. 41A to 41C are cross-sectional views showing the etching process of the structures of Figs. 40A to 40C; and Figs. 42A to 42C are cross-sectional views showing the photoresist of Figs. 41A to 41C after ashing; Fig. 43A - Figure 43C is a cross-sectional view of the first metal film of Figures 42A-42C after etching process;
  • 44A-44C are cross-sectional views showing the etching process of the doped semiconductor film of Figs. 43A-43C;
  • 45A-45C is a cross-sectional view of the photoresist after peeling off the photoresist of FIG. 44A-44C;
  • FIGS. 46A to 46C are cross-sectional views showing the deposition of an insulating film on the structure of Figs. 45A to 45C;
  • FIGs. 47A to 47C are views showing the application of the photoresist on the structure of Figs. 46A to 46C after exposure and development. Sectional view;
  • FIGS. 48A to 48C are cross-sectional views showing the structure of Figs. 47A to 47C after etching;
  • FIG. 49A to Fig. 49C are cross-sectional views of the photoresist after peeling off the patterns of Figs. 48A to 48C;
  • 50A to 50C are cross-sectional views showing the deposition of the second transparent conductive film and the second metal film on the structures of Figs. 49A to 49C;
  • 51A to 51C are cross-sectional views after exposure and development processing after applying a photoresist on the structures of Figs. 50A to 50C;
  • FIGS. 52A-52C are cross-sectional views showing the structure of FIGS. 50A-50C after etching
  • FIG. 53A-53C are cross-sectional views showing the photoresist of FIG. 52A-52C after ashing process
  • 54A-FIG. 54C are cross-sectional views showing the structure of FIGS. 53A-53C after an etching process
  • 55A to 55C are cross-sectional views after the photoresist of FIGS. 54A to 54C is peeled off.
  • the Array Substrate includes: a gate line 1, a data line 2, a thin film transistor (Thm Firm Transistor, abbreviated as TFT) 3, a pixel electrode 4, a common electrode 50, and a common electrode line 5.
  • TFT Thin Firm Transistor
  • the gate line 1 is laterally disposed on the transparent substrate
  • the data line 2 is longitudinally disposed on the transparent substrate
  • the TFT 3 is disposed at the intersection of the gate line 1 and the data line 2.
  • TFT3 is an active switching element.
  • the pixel electrode 4 is a slit electrode.
  • the common electrode 50 is located below the pixel electrode 4, and mostly overlaps, and the common electrode 50 and the pixel electrode form an electric field for driving the liquid crystal.
  • the common electrode line 5 is connected to the common electrode 50.
  • the reference numeral "50" refers to a slit which is not a long strip, but a plate-like common electrode below the slit.
  • 2A-2C are cross-sectional views of an FFS type TFT-LCD array substrate.
  • 2A is a cross-sectional view taken along line A-A of FIG. 1, showing a cross-sectional structure of a pixel portion of the array substrate.
  • the array substrate further includes: a transparent substrate 11, a common electrode 50, a gate electrode 12, a gate insulating layer 13, a semiconductor layer 14, a doped semiconductor layer 15, a source electrode 16, a drain electrode 17, and a passivation layer. 18.
  • the gate electrode 12 is integrally formed with the gate line 1
  • the source electrode 16 is integrally formed with the data line 2
  • the drain electrode 17 and the pixel electrode 4 are generally connected by a via hole 180.
  • the active layer (the semiconductor layer 14 and the doped semiconductor layer 15) is electrically conductive, and the data signal of the data line 2 can pass from the source electrode 16 to the drain electrode 17 via the TFT channel 19. Finally, it is input to the pixel electrode 4.
  • the pixel electrode 4 obtains a signal and forms an electric field for driving the liquid crystal to rotate with the plate-like common electrode 50. Since the pixel electrode 4 has the slit 49, a horizontal electric field is formed with the common electrode 50.
  • 2B is a cross-sectional view of a data line of a PAD region of an FFS type TFT-LCD P train substrate
  • 2C is a cross-sectional view of a gate line of a PAD region of an FFS type TFT-LCD array substrate.
  • the PAD region is a crimping region, and is a region where a signal line such as a gate line, a data line, and a common electrode line is crimped to a lead of an external driving circuit board.
  • the PAD region is located on one of the four sides of the array substrate or on two adjacent sides. In order to electrically connect the leads and the signal lines, there must be no insulation covering the signal lines above the PAD area. As can be seen from FIGS.
  • the data lines 2 and the gate lines 1 of the PAD region are provided with connection holes 181, 182, and the structure indicated by reference numeral 700 is formed by etching a transparent conductive film to form a pixel electrode.
  • the formed transparent conductive layer is electrically conductive
  • the reference numerals 300 and 400 in Fig. 2B are structures formed when the doped semiconductor film and the semiconductor film are etched, without affecting the communication of the data line 2.
  • the external leads can be directly soldered to the transparent conductive layer 700 of FIGS. 2B and 2C to realize the connection between the array substrate and the driving circuit board.
  • a connection hole is also formed above the common electrode line for connecting with an external lead, and the structure thereof is substantially the same as that of FIG. 2C.
  • the entire substrate needs to be etched twice, usually by wet etching, in which the substrate is immersed in the etching solution to remove the portion that is not covered by the photoresist and can be eroded by the etching solution.
  • wet etching in which the substrate is immersed in the etching solution to remove the portion that is not covered by the photoresist and can be eroded by the etching solution.
  • the etching parameters need to be strictly controlled, usually by controlling the etching time.
  • the TFT channel is often overetched (Over Etch).
  • Fig. 3 is a flow chart showing a method of manufacturing an FFS type TFT-LCD array substrate according to Embodiment 1 of the present invention.
  • a method for manufacturing an FFS type TFT-LCD array substrate according to Embodiment 1 of the present invention includes:
  • Step 1 sequentially forming a first transparent conductive film, a first metal film, and a doped semiconductor film on the transparent substrate, and then patterning the first transparent conductive film, the first metal film, and the doped semiconductor film to form a source including a pattern of electrodes, drain electrodes, data lines, and pixel electrodes;
  • Step 2 forming a semiconductor film, patterning the semiconductor film, forming a pattern of a doped semiconductor layer and a pattern of a semiconductor layer including a TFT channel;
  • Step 3 depositing an insulating film and a second metal film, and injecting the insulating film and the second metal film Patterning, forming a pattern including a data line connection hole, a gate line, a gate electrode, and a common electrode line of the PAD region;
  • Step 4 Form a second transparent conductive film, and pattern the second transparent conductive film to form a pattern including the common electrode.
  • the FFS type TFT-LCD array substrate is manufactured by four patterning processes, which reduces the number of processes compared with the prior art, greatly saves cost, and improves the cost.
  • the market is competitive.
  • the first patterning process of the method of fabricating the FFS type TFT-LCD array substrate of the embodiment 1 according to the present invention includes the following steps:
  • Step 11 depositing a first transparent conductive film 100, a first metal film 200, and a doped semiconductor film 400 on the transparent substrate 11, as shown in FIGS. 4A-4C.
  • the first transparent conductive film 100, the first metal may be sequentially deposited on the transparent substrate 11 (such as a glass substrate or a quartz substrate) by plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods.
  • the film 200 and the doped semiconductor film 400; the first transparent conductive film 100 may be a transparent conductive material such as ITO or germanium.
  • the first metal thin film 200 may be a single-layer thin film formed of a metal such as molybdenum, aluminum, aluminum bismuth alloy, tungsten, chromium, copper or the like, or may be a multilayer thin film formed by depositing the above metal layers.
  • Step 12 Applying a photoresist 1000 on the doped semiconductor film 400 of the structure of FIGS. 4A to 4C, and exposing and developing the photoresist through a prefabricated mask.
  • the mask used in this step is a two-tone mask (for example, a halftone mask or a gray tone mask).
  • the two-tone mask can be classified into a complete light leakage region, a partial light leakage region, and a non-light leakage region depending on the degree of light transmission or intensity.
  • the photoresist 100 forms an unexposed area, a partially exposed area, and a fully exposed area, and then developed, and the photoresist in the fully exposed area is washed away by the agent; the photoresist in the partially exposed area The upper layer is exposed and washed away, leaving the underlying photoresist, whereby the thickness of the photoresist layer is reduced; the thickness of the photoresist in the unexposed areas remains unchanged.
  • the unexposed area corresponds to the data line 2 of the array substrate (refer to FIG. 1 ), the source electrode and the leakage current.
  • the partially exposed area corresponds to the area of the pixel electrode 4 (see FIG. 1) of the array substrate, and the fully exposed area corresponds to the remaining area of the array substrate, as shown in FIGS. 5A-5C.
  • Step 13 performing an etching process on the structure of FIG. 5A to FIG. 5C, removing the doped semiconductor film 400, the first metal thin film 200, and the first transparent conductive film 100 in the fully exposed region, and forming the data line 2 and the pixel electrode. 4 graphics.
  • the etching process of this step includes a three-step etching.
  • the first step is to etch the doped semiconductor film 400 by using an etching solution doped with a semiconductor material
  • the second step is to engrave the first metal film 200 by using a metal material etching solution (for example, a mixture of phosphoric acid and nitric acid).
  • the pattern of the data line 2 is obtained by etching, and the third step is to remove the first transparent conductive film 100 by using an etching solution of ITO or IZO to form a pattern of the pixel electrode 4, as shown in Figs. 6A to 6C.
  • large-area patterns can be etched by wet etching.
  • the so-called wet etching is to put the object to be etched into the etching solution, so that the etching liquid etches away the exposed object to be etched.
  • the metal material etching solution can only etch away the metal material, that is, the first metal film.
  • the areas covered by the photoresist that is, the partially exposed areas and the unexposed areas, are not corroded by photoresist protection.
  • the film in the fully exposed area is etched away by direct contact with the etching solution.
  • the residual film forms the desired pattern.
  • Step 14 The photoresist 100 of FIGS. 6A-6C is subjected to an ashing process to expose the doped semiconductor film 400 of the partially exposed region, as shown in FIGS. 7A-7C.
  • the role of the ashing process is to remove a certain thickness of photoresist.
  • the thickness of the photoresist removed is the same as the thickness of the photoresist remaining in the partially exposed area in step 12, that is, after the ashing process, the photoresist is retained only in the non-exposed area, and no photoresist is in other areas. Remaining.
  • Step 15 performing an etching process on the structure of FIGS. 7A-7C, removing the doped semiconductor film 400 and the first metal film 200 in the partially exposed region, forming a pattern including the source electrode 16 and the drain electrode 17, as shown in FIG. 8A- 8C.
  • the etching process of this step includes a two-step etching. The doped semiconductor film 400 is first etched, and then the first metal film 200 is etched, thereby forming the source electrode 16 and the drain electrode 17, and exposing the pixel electrode 4.
  • Step 16 Strip the remaining photoresist 1000 in Figures 8A- 8C, as shown in Figures 9A-9C.
  • the second patterning process includes the following steps:
  • Step 21 On the structure of FIGS. 9A-9C, a semiconductor thin film 300 is deposited, as shown in FIG. 10A- Step 22: coating a photoresist 2000 on the semiconductor film 300 of FIGS. 10A-10C, exposing and developing the photoresist through a pre-made mask, so that the photoresist 2000 includes a fully exposed region and Do not expose the area.
  • the unexposed regions correspond to regions of the semiconductor layer 14 (see FIG. 2) of the array substrate, and the fully exposed regions correspond to the remaining regions, as shown in FIGS. 11A-11C.
  • the mask used in this step is a normal mask, which has a completely leaky area and a light-free area.
  • Step 23 An etching process is performed on Figs. 11A to 11C, and the semiconductor film 300 of the fully exposed region is removed, and a semiconductor layer 14 and a doped semiconductor layer 15, are formed, as shown in Figs. 12A to 12C.
  • the doped semiconductor layer 400 may be etched while etching the semiconductor layer film 300.
  • the TFT channel is naturally formed without etching. Therefore, it is possible to avoid the problem that over-etching defects are generated when the doped semiconductor thin film is formed into a TFT channel as in the prior art.
  • Step 24 Strip the remaining photoresist 2000 of Figures 12A-12C, as shown in Figures 13A-13C.
  • a third patterning process of the method of manufacturing the FFS type TFT-LCD array substrate according to Embodiment 1 of the present invention will be described in detail based on Figs. 14A to 19C.
  • the third patterning process includes the following steps:
  • Step 31 On the structure of FIGS. 13A to 13C, an insulating film 500 and a second metal film 600 are sequentially deposited, as shown in FIGS. 14A to 14C;
  • Step 32 Applying a photoresist 3000 on the second metal film in FIGS. 14A to 14C, exposing and developing the photoresist 300 through a pre-made mask, so that the photoresist 300 includes an unexposed area. , partially exposed areas and fully exposed areas.
  • the non-exposed area corresponds to a region of the gate electrode 12, the gate line 1 and the common electrode line 5 of the array substrate, and the fully exposed area corresponds to an area of the data line 2 of the PAD area of the array substrate, and the partially exposed area corresponds to The remaining area of the array substrate is as shown in Figures 15A-15C.
  • Step 33 performing an etching process on the structure of 15A-FIG. 15C, removing the second metal film 600 and the insulating film 500 in the fully exposed region, and forming a pattern including the PAD region data line connection hole and the gate insulating layer 13, as shown in FIG. 16A- Figure 16C.
  • Step 34 performing an ashing process on the photoresist 3000 of FIGS. 16A-16C, exposing the second metal film 600 of the partially exposed region, and retaining a certain thickness of the photoresist in the non-exposed area, such as 17A-17C.
  • Step 35 performing an etching process on the structures of FIGS. 17A-17C to remove the partially exposed regions
  • the second metal film 600 of the domain is patterned to include the common electrode line 5 (see FIG. 1), the gate electrode 12, and the gate line 1, as shown in FIGS. 18A-18C.
  • Step 36 The remaining photoresist 3000 of Figs. 18A- 18C is peeled off, as shown in Figs. 19A-19C.
  • a fourth patterning process of the method of fabricating the FFS type TFT-LCD array substrate according to Embodiment 1 of the present invention will be described in detail with reference to Figs. 20A to 23C.
  • the fourth patterning process includes the following steps:
  • Step 41 On the structure of FIGS. 19A to 19C, a second transparent conductive film 700 is deposited as shown in FIG.
  • Step 42 Applying a photoresist 4000 on the second transparent conductive film 700 of FIG. 20A to FIG. 20C, exposing and developing the photoresist 4000 through a pre-formed mask, so that the photoresist 4000 is completely exposed.
  • the non-exposed area corresponds to the common electrode 50 of the array substrate (refer to FIG. 1 ), the data line 2 of the PAD area, and the area of the gate line 1 of the PAD area, and the fully exposed area corresponds to the remaining area, as shown in FIG. 21A - 21C.
  • Step 44 An etching process is performed on the structure of Figs. 21A to 21C, and the second transparent conductive film 700 of the fully exposed region is removed to form a pattern including the common electrode 50, as shown in Figs. 22A-22C.
  • Step 45 Strip the remaining photoresist 4000 of Figures 22A-22C, as shown in Figures 23A-23C.
  • the manufacturing method of the FFS type TFT-LCD array substrate of Embodiment 1 of the present invention not only one patterning step is less than the existing five-time patterning process, but also a method of patterning the doped semiconductor layer and then patterning the semiconductor layer is employed.
  • the TFT channel is over-etched to avoid the production quality of the liquid crystal display.
  • Figure 24 is a flow chart showing a method of manufacturing an FFS type TFT-LCD array substrate according to Embodiment 2 of the present invention. As shown in FIG. 24, a method for manufacturing an FFS type TFT-LCD array substrate according to Embodiment 2 of the present invention includes:
  • Step 1 Forming a first transparent conductive film, a first metal film, and a doped semiconductor film on the transparent substrate, and patterning the first transparent conductive film, the first metal film, and the doped semiconductor film to form a source including a pattern of electrodes, drain electrodes, data lines, and pixel electrodes;
  • Step 2 depositing a semiconductor film, patterning the semiconductor film and the doped semiconductor film, forming a pattern of the doped semiconductor layer and a pattern of the semiconductor layer including the TFT channel;
  • Step 3' depositing an insulating film and a second metal film, patterning the insulating film and the second metal film, and then depositing a second transparent conductive film, performing a ground stripping process and an etching process to form The pattern of the PAD area data line connection hole, the gate line, the gate electrode, and the common electrode line.
  • the FFS type TFT-LCD array substrate of the present embodiment is manufactured by the three patterning process, and the number of processes is further reduced compared with the embodiment 1, the cost is greatly saved, and the market is improved. Competing.
  • a third patterning process of the method of fabricating the FFS type TFT-LCD array substrate according to Embodiment 2 of the present invention will be described in detail with reference to Figs. 25A to 33C.
  • the third patterning process includes the following steps:
  • Step 3 An insulating film 500 and a second metal film 600 are sequentially deposited on the structures obtained in Figs. 13A to 13C, as shown in Figs. 25A to 25C.
  • Step 32 ′ coating a photoresist 3000 on the second metal film 600 of FIGS. 25A to 25C , and exposing and developing the photoresist 3000 ′ through a pre-made mask to make the photoresist
  • the 3000' includes a non-exposed area, a first partial exposed area, a second partially exposed area, and a fully exposed area, wherein the photoresist of the second partial exposed area after development is thicker than the photoresist of the first partially exposed area.
  • the fully exposed area corresponds to the area of the data line 2 of the PAD area of the array substrate, the first partial exposed area corresponds to the area of the common electrode 50 of the array substrate, and the second partial exposed area corresponds to the grid of the array substrate Line 1, the area of the gate electrode 12, the unexposed area corresponding to the remaining area of the array substrate, as shown in Figures 26A-26C.
  • the mask used in this step is a three-tone mask having a complete light leakage region, a first portion of the light leakage region, a second portion of the light leakage region, and a non-light leakage region. The four regions are divided by the intensity or degree of light leakage, and the first portion is light leakage. The light transmitted through the area is stronger than the light transmitted through the second part of the light leakage area.
  • Step 33 ′ performing an etching process on the structure of FIGS. 26A to 26C , removing the insulating film 500 and the second metal film 600 in the fully exposed region, and forming a pattern including the PAD region data line connection hole and the gate insulating layer 13 . 27A-27C.
  • the etching process of this step is etched in two steps, the second metal film 600 is etched first, and then the insulating film 500 is etched.
  • Step 34' For the photoresist 3000 of FIGS. 27A to 27C, an ashing process is performed to expose the second metal film 600 of the first partial exposed region, and the second portion of the exposed region and the unexposed region are respectively retained. A certain thickness of photoresist, as shown in Figures 28A-28C.
  • Step 35' performing an etching process on the structure of FIG. 28A to FIG. 28C, removing the first partial exposure
  • the second metal film 600 of the light region is as shown in Figs. 29A-29C.
  • Step 36 ′ performing the ashing process on the photoresist 3000 of FIGS. 29A to 29C to expose the second metal film 600 of the second partial exposed region, and leaving a certain thickness of the photoresist in the unexposed region, See Figures 30A-30C.
  • Step 37 depositing a second transparent conductive film 700 on the structure of Figs. 30A- 30C, as shown in the figure
  • Step 38' performing a ground lift-off process on the structure of FIGS. 31A-31C, removing the photoresist 3000 of the non-exposed area, and the second transparent conductive film deposited on the photoresist 3000
  • Step 39' An etching process is performed on the structures of Figs. 32A to 32C, and the second metal thin film 600 of the unexposed regions is removed to form a pattern including the gate lines 1 and the gate electrodes 12.
  • the FFS type TFT-LCD array substrate of the present embodiment is manufactured by the three patterning process, and the number of processes is further reduced compared with the embodiment 1, the cost is greatly saved, and the market is improved. Competing.
  • Figure 34 is a flow chart showing a method of manufacturing an FFS type TFT-LCD array substrate according to Embodiment 3 of the present invention. As shown in FIG. 34, a method for manufacturing an FFS type TFT-LCD array substrate according to Embodiment 3 of the present invention includes:
  • Step 100 sequentially forming a semiconductor film and a doped semiconductor film on the transparent substrate, patterning the semiconductor film and the doped semiconductor film, and forming a pattern including the semiconductor layer and the doped semiconductor layer;
  • Step 200 forming a first transparent conductive film and a first metal film, patterning a stack of the first transparent conductive film and the first metal film, forming a source electrode, a drain electrode, a doped semiconductor layer, a TFT channel, and a data a pattern of lines and pixel electrodes;
  • Step 300 forming an insulating film, patterning the insulating film, and forming a pattern including a data line connecting hole in the PAD region;
  • Step 400 Forming a second transparent conductive film and a second metal film, patterning the stack of the second transparent conductive film and the second metal film to form a pattern including a gate line, a gate electrode, and a common electrode.
  • an FFS type TFT-LCD array substrate is manufactured by four patterning processes, which reduces the number of processes and greatly saves cost and improves the cost compared with the prior art.
  • the market is competitive.
  • a method of fabricating an FFS type TFT-LCD array substrate according to Embodiment 3 of the present invention will be described in detail below with reference to FIGS. 35A to 55C.
  • the first patterning process includes the following steps:
  • Step 1100 sequentially depositing a semiconductor film 300 and a doped semiconductor film 400 on the transparent substrate 11, as shown in FIGS. 35A-35C.
  • Step 1200 Applying a photoresist 5000 on the doped semiconductor film of FIGS. 35A-35C, exposing and developing the photoresist 5000 through a pre-made mask, so that the photoresist includes an unexposed area. Fully exposed area. The non-exposed areas correspond to areas of the semiconductor layer 14 of the array substrate, and the fully exposed areas correspond to the remaining areas of the array substrate, as shown in Figures 36A-36C.
  • Step 1300 An etching process is performed on the structures of FIGS. 36A-36C, and the doped semiconductor film 400 and the semiconductor film 300 of the fully exposed region are removed to form a pattern including the semiconductor layer 14, as shown in FIGS. 37A-37C.
  • Step 1400 Stripping the remaining photoresist 5000 in FIGS. 37A-37C, as shown in FIG. 38A-38C.
  • an insulating film may be deposited first, and together with the semiconductor layer. The pattern is patterned to obtain a pattern of forming an insulating layer under the semiconductor layer.
  • the insulating layer can prevent parasitic capacitance between the semiconductor layer and the backlight module and hinder signal transmission.
  • the insulating film is preferably made of an opaque material such as silicon nitride and carbon black. The mixture (making a black matrix material), etc.
  • the insulating film can simultaneously function as a black matrix.
  • the second patterning process includes the following steps:
  • Step 2100 On the structure obtained in FIGS. 38A to 38C, the first transparent conductive film 100 and the first metal film 200 are sequentially deposited, as shown in FIGS. 39A to 39C.
  • Step 2200 Applying a photoresist 6000 on the first metal film of FIG. 39A to FIG. 39C, exposing and developing the photoresist 6000 through a pre-made mask, so that the photoresist 6000 includes no exposure.
  • Area, partially exposed area, and fully exposed area corresponds to the area of the data line 2, the source electrode 16 and the drain electrode 17 of the array substrate, the partially exposed area corresponds to the area of the pixel electrode 4 of the array substrate, and the fully exposed area corresponds to the array substrate The rest of the area, as shown in Figures 40A-40C.
  • Step 2300 performing an etching process on the structures of FIGS. 40A-40C to remove the complete exposure
  • the first metal thin film 200 of the region and the first transparent conductive film 100 form a pattern including the data line 2 and the pixel electrode 4, as shown in FIGS. 41A to 41C.
  • Step 2400 performing an ashing process on the photoresist 6000 of FIGS. 41A-41C, exposing the first metal film 200 of the partially exposed region, and leaving a portion of the photoresist in the unexposed region, as shown in the figure. 42A - Figure 42C.
  • Step 2500 performing an etching process on the structure of FIGS. 42A-42C, removing the first metal thin film 200 and the doped semiconductor thin film 400 of the partially exposed region, forming a channel including the TFT channel 19, the source electrode 16, and the drain electrode 17. Graphics, as shown in Figures 43A-44C.
  • Step 2600 Stripping the remaining photoresist 6000 in Figures 44A-44C, as shown in Figures 45A-45C.
  • a third patterning process of the method of manufacturing the FFS type TFT-LCD array substrate of the second embodiment of the present invention will be described in detail with reference to Figs. 46A to 49C.
  • the third patterning process includes the following steps:
  • Step 3100 On the structure obtained in Figs. 45A-45C, an insulating film 500 is deposited, as shown in Figs. 46A-46C.
  • Step 3200 Applying a photoresist 7000 on the insulating film 500 of FIGS. 46A-46C, exposing and developing the photoresist 7000 through a pre-made mask, so that the photoresist 7000 includes an unexposed area.
  • Fully exposed area The fully exposed area corresponds to the area of the data line 2 of the PAD area of the array substrate, and the unexposed area corresponds to the remaining area of the array substrate, as shown in Figs. 47A-47C.
  • Step 3300 etching the structure of FIGS. 47A-47C, removing the insulating film 500 of the fully exposed region, and forming a pattern including the gate insulating layer 13, as shown in FIGS. 48A-48C.
  • Step 3400 Strip the remaining photoresist 7000 in Figures 48A-48C, as shown in Figures 49A-49C.
  • a fourth patterning process of the method of manufacturing the FFS type TFT-LCD array substrate of the second embodiment of the present invention will be described in detail with reference to Figs. 50A to 55C.
  • the third patterning process includes the following steps:
  • Step 4100 On the structure of FIGS. 49A to 49C, a second transparent conductive film 700 and a second metal film 600 are deposited, as shown in FIGS. 50A to 50C.
  • Step 4200 coating a photoresist 8000 on the second metal film 600 of FIG. 50A to FIG. 50C, exposing and developing the photoresist 8000 through a prefabricated mask, so that the photoresist includes an unexposed area, Partially exposed area and fully exposed area.
  • the non-exposed area corresponds to a region of the gate electrode 12 of the array substrate, the gate line 1, the common electrode line 5, and the data line 2 of the PAD region, and the partially exposed region corresponds to a region of the common electrode 50 of the array substrate, Full exposure area corresponding
  • the remaining area of the array substrate is as shown in Figs. 51A-51C.
  • Step 4300 performing an etching process on the structure of FIGS. 51A-51C, removing the second metal film 600 and the second transparent conductive film 700 in the fully exposed region, forming the gate line 1, the gate electrode 12, the common electrode line 5, and the common
  • the pattern of electrode 50 is shown in Figures 52A-52C.
  • Step 4400 performing an ashing process on the photoresist 8000 of FIGS. 52A-52C, exposing the second metal film 600 of the partially exposed region, and leaving a portion of the photoresist in the unexposed region, Figure 53A-53C.
  • Step 4500 An etching process is performed on the structure of Figs. 53A-53C, and the second metal film 600 of the partially exposed region is removed to expose the common electrode 50, as shown in Figs. 54A-54C.
  • Step 4600 Stripping the remaining photoresist of Figures 54A-54C, as shown in Figures 55A-55C.
  • embodiments of the present invention are not limited to positive photoresists. For example, if a negative photoresist is used, the photoresist in the fully exposed region of the photoresist after development is completely retained, rather than the light in the exposed region. The photoresist is completely removed, and the photoresist in the partially exposed areas is still partially retained.

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Description

FFS型 TFT-LCD阵列 的制造方法 技术领域
本发明涉及一种 FFS型 TFT-LCD阵列基板的制造方法。 背景技术
薄膜晶体管液晶显示装置 ( Thin Film Transistor Liquid Crystal Display, 简称 TFT-LCD )是一种主要的平板显示装置（ Flat Panel Display,简称为 FPD )。
才艮据驱动液晶的电场方向， TFT-LCD分为垂直电场型和水平电场型。 垂 直电场型 TFT-LCD 需要在阵列基板上形成像素电极， 在彩膜基板形成公共 电极； 然而， 水平电场型 TFT-LCD 需要在阵列基板上同时形成像素电极和 公共电极。 因此， 制作水平电场型 TFT-LCD 的阵列基板时， 相对于垂直电 场型 TFT-LCD 的阵列基板， 需要额外增加一次形成公共电极的掩模工艺。 垂直电场型 TFT-LCD 包括： 扭曲向列 （ Twist Nematic , 简称为 TN ) 型 TFT-LCD;水平电场型 TFT-LCD包括：边缘电场切换（ Fringe Field Switching, 简称为 FFS )型 TFT-LCD, 共平面切换（In-Plane Switching, 简称为 IPS ) 型 TFT-LCD。 水平电场型 TFT-LCD, 尤其是 FFS型 TFT-LCD, 具有广视角、 开口率高等优点， 广泛应用于液晶显示器领域。
目前， FFS型 TFT-LCD阵列基板是通过多次构图工艺形成结构图形来完 成， 每一次构图工艺中又分别包括使用掩模对光刻胶曝光、 显影、 刻蚀和剥 离剩余的光刻胶等工艺。 刻蚀工艺包括干法刻蚀和湿法刻蚀。 所以构图工艺 的次数可以衡量制造 TFT-LCD 阵列基板的繁简程度， 减少构图工艺的次数 就意味着制造成本的降低。 现有技术的六次构图工艺包括： 公共电极构图、 栅线和栅电极构图、 有源层构图、 源电极 /漏电极构图、 过孔构图和像素电 极构图。
现有的五次构图工艺制造 FFS型 TFT-LCD阵列基板的方法如下： 步骤 1、 沉积第一透明导电薄膜， 通过普通掩模板（mask )形成板状的 公共电极的图形；
步骤 2、 沉积第一金属薄膜， 用普通掩模板形成栅线、 栅电极及公共电 极线的图形；
步骤 3、 依次沉积第一绝缘薄膜、 半导体薄膜、 掺杂半导体薄膜和第二 金属薄膜， 用双调掩模板 ( dual tone mask )形成有源层 （半导体层和掺杂半 导体层）、 TFT沟道、 源电极、 漏电极和数据线的图形；
步骤 4、沉积第二绝缘薄膜 ,用第二双调掩模板形成过孔的图形，在 PAD 区域的栅线区域、 PAD 区域的数据线区域及 PAD 区域的公共电极线区域形 成连接孔的图形；
步骤 5、 沉积第二透明导电薄膜， 通过普通掩模板（mask )形成具有狭 缝的像素电极的图形。 发明内容
本发明的一个实施例提供一种 FFS型 TFT-LCD阵列基板的制造方法， 包括： 步骤 1 : 在透明基板上依次形成第一透明导电薄膜、 第一金属薄膜及 掺杂半导体薄膜， 然后对所述第一透明导电薄膜、 所述第一金属薄膜及所述 摻杂半导体薄膜的叠层进行构图， 形成包括源电极、 漏电极、 数据线和像素 电极的图形； 步骤 2: 形成半导体薄膜， 对所述半导体薄膜进行构图， 形成 掺杂半导体层的图形及包括 TFT沟道的半导体层的图形； 步骤 3: 形成绝缘 薄膜和第二金属薄膜、对所述绝缘薄膜和所述第二金属薄膜的叠层进行构图， 形成包括 PAD区域数据线连接孔、 栅线、 栅电极以及公共电极线的图形； 步 骤 4、 形成第二透明导电薄膜， 对所述第二透明导电薄膜进行构图， 形成包 括公共电极的图形。
本发明的另一个实施例提供一种 FFS型 TFT-LCD阵列基板的制造方法， 包括： 步骤 1 : 在透明基板上依次形成第一透明导电薄膜、 第一金属薄膜及 掺杂半导体薄膜， 对所述第一透明导电薄膜、 所述第一金属薄膜及所述掺杂 半导体薄膜的叠层进行构图， 形成包括源电极、 漏电极、 数据线和像素电极 的图形； 步骤 2: 形成半导体薄膜， 对所述半导体薄膜进行构图， 形成掺杂 半导体层的图形及包括 TFT沟道的半导体层的图形； 步骤 3'： 形成绝缘薄 膜和第二金属薄膜、 对所述绝缘薄膜和所述第二金属薄膜进行构图， 然后形 成第二透明导电薄膜， 进行离地剥离工艺及刻蚀工艺， 形成 PAD区域数据线 连接孔、 栅线、 栅电极以及公共电极线的图形。 本发明的又一个实施例提供一种 FFS型 TFT-LCD阵列基板的制造方法， 包括： 步骤 100: 在透明基板上依次形成半导体薄膜及掺杂半导体薄膜， 对 所述半导体薄膜及所述掺杂半导体薄膜的叠层进行构图， 形成包括半导体层 和掺杂半导体层的图形； 步骤 200: 形成第一透明导电薄膜及第一金属薄膜， 对所述第一透明导电薄膜及所述第一金属薄膜的叠层进行构图， 形成包括源 电极、 漏电极、 掺杂半导体层、 TFT沟道、 数据线和像素电极的图形； 步骤 300: 形成绝缘薄膜、 对所述绝缘薄膜进行构图， 形成包括 PAD区域数据线 连接孔的图形； 步骤 400、 形成第二透明导电薄膜及第二金属薄膜， 对所述 第二透明导电薄膜及所述第二金属薄膜的叠层进行构图， 形成包括栅线、 栅 电极和公共电极的图形。 附图说明
图 1为一种 FFS型 TFT-LCD阵列基板的平面示意图；
图 2A为图 1的 A-A向剖面图， 显示了像素区域的剖面图， 图 2B为一 种 FFS型 TFT-LCD阵列基板的 PAD区域的数据线的剖面图； 图 2C为一种 FFS型 TFT-LCD阵列基板的 PAD区域的栅线的剖面图；
图 3为根据本发明实施例 1制造 FFS型 TFT-LCD阵列基板的流程图； 图 4A-图 4C为在透明基板上沉积第一透明导电薄膜、 第一金属薄膜及 掺杂半导体薄膜后的剖面图,其中图 4A所示为像素区域的截面图， 图 4B所 示为 PAD区域的栅线的截面图 , 图 4C所示为 PAD区域的数据线的截面图； 图 5A-图 5C为在图 4A-图 4C的结构上涂覆光刻胶后进行了曝光和显影 处理后的剖面图；
图 6A-图 6C为对图 5A-图 5C的结构进行刻蚀工艺后的剖面图； 图 7 A-图 7C为对图 6A-图 6C的光刻胶进行灰化工艺后的剖面图； 图 8A-图 8C为对图 7A-图 7C的结构进行刻蚀工艺后的剖面图； 图 9A-图 9C为剥离图 8A-图 8C的光刻胶后的剖面图；
图 10A-图 10C为在图 9A-图 9C的结构上沉积半导体薄膜后的剖面图； 图 11A-图 11C为对图 10A-图 10C的结构上涂覆光刻胶后进行曝光和显 影处理后的剖面图；
图 12A-图 12C为对图 11A-图 11C的结构进行刻蚀工艺后的剖面图； 图 13A-图 13C为剥离图 12A-图 12C的光刻胶后的剖面图；
图 14A-图 14C为对图 13A-图 13C的结构沉积绝缘薄膜和第二金属薄膜 后的剖面图；
图 15A-图 15C为在图 14A-图 14C的结构上涂覆光刻胶并进行曝光和显 影处理后的剖面图；
图 16A-图 16C为在图 15A-图 15C的结构上进行刻蚀工艺后的剖面图； 图 17A-图 17C为对图 16A-图 16C的光刻胶进行灰化工艺后的剖面图； 图 18A-图 18C对图 17A-图 17C的光刻胶进行刻蚀工艺后的剖面图； 图 19A-图 19C为剥离图 18A-图 18C的光刻胶后的剖面图；
图 20A-图 20C为在图 19A-图 19C的结构上沉积第二透明导电薄膜后的 剖面图；
图 21A-图 21C为在图 20A-图 20C的结构上涂覆光刻胶并进行曝光和显 影处理后的剖面图；
图 22A-图 22C为在图 21A-图 21C的结构进行刻蚀工艺后的剖面图； 图 23 A-图 23C为剥离图 22A-图 22C的光刻胶后的剖面图；
图 24为根据本发明实施例 2的制造 FFS型 TFT-LCD阵列基板的流程图； 图 25A-图 25C为在图 13A-图 13C的结构上沉积绝缘薄膜及第二金属薄 膜后的剖面图；
图 26A-图 26C为在图 25A-图 25C的结构上涂覆光刻胶后进行曝光和显 影处理后的剖面图；
图 27A-图 27C为对图 26A-图 26C的结构进行刻蚀工艺后的剖面图； 图 28A-图 28C为对图 27 A-图 27C的光刻胶进行灰化工艺后的剖面图； 图 29A-图 29C为对图 28A-图 28C的结构进行刻蚀工艺后的剖面图； 图 30A-图 30C为对图 29A-图 29C的结构进行灰化工艺后的剖面图； 图 31 A-图 31 C为在图 30A-图 30C的结构上沉积第二透明导电薄膜后的 剖面图；
图 32A-图 32C为在图 31A-图 31C的结构上进行离地剥离工艺后的剖面 图；
图 33A-图 33C为对图 32A-图 32C的结构进行刻蚀工艺后的剖面图； 图 34为根据本发明实施例 3的制造 FFS型 TFT-LCD阵列基板的流程图； 图 35A-图 35C为在透明基板上沉积半导体薄膜及摻杂半导体薄膜后的 剖面图,其中图 35A所示为像素区域的截面图， 图 35B所示为 PAD区域的栅 线的截面图， 图 35C所示为 PAD区域的数据线的截面图；
图 36A-图 36C为在图 35A-图 35C的结构上涂覆光刻胶后进行曝光和显 影处理后的剖面图；
图 37A-图 37C为对图 36A-图 36C的结构进行刻蚀工艺后的剖面图； 图 38A-图 38C为剥离图 37A-图 37C的光刻胶后的剖面图；
图 39A-图 39C为在图 38A-图 38C的结构上沉积第一透明导电薄膜及第 一金属薄膜后的剖面图；
图 40A-图 40C为在图 39A-图 39C的结构上涂覆光刻胶后进行曝光和显 影处理后的剖面图；
图 41A-图 41C为对图 40A-图 40C的结构进行刻蚀工艺后的剖面图； 图 42A-图 42C为对图 41A-图 41C的光刻胶进行灰化工艺后的剖面图； 图 43A-图 43C对图 42A-图 42C的第一金属薄膜进行刻蚀工艺后的剖面 图；
图 44A-图 44C对图 43A-图 43C的掺杂半导体薄膜进行刻蚀工艺后的剖 面图；
图 45 A-图 45C为剥离图 44 A-图 44C的光刻胶后的剖面图；
图 46A-图 46C为在图 45A-图 45C的结构上沉积绝缘薄膜后的剖面图； 图 47A-图 47C为在图 46A-图 46C的结构上涂覆光刻胶并进行曝光和显 影处理后的剖面图；
图 48A-图 48C为对图 47A-图 47C的结构进行刻蚀工艺后的剖面图； 图 49A-图 49C为剥离图 48A-图 48C的光刻胶后的剖面图；
图 50A-图 50C为在图 49 A-图 49C的结构上沉积第二透明导电薄膜和第 二金属薄膜后的剖面图；
图 51A-图 51C为在图 50A-图 50C的结构上涂覆光刻胶后进行曝光和显 影处理后的剖面图；
图 52A-图 52C为对图 50A-图 50C的结构进行刻蚀工艺后的剖面图； 图 53 A-图 53C为对图 52A-图 52C的光刻胶进行灰化工艺后的剖面图； 图 54A-图 54C对图 53A-图 53C的结构进行刻蚀工艺后的剖面图； 图 55A-图 55C为剥离图 54A-图 54C的光刻胶后的剖面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。 基于 本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
为了更好地描述根据本发明实施例的制造 FFS型 TFT-LCD阵列基板的 方法， 首先结合图 1及图 2A至 2C描述 FFS型 TFT-LCD的基本构造。
图 1为一种 FFS型 TFT-LCD阵列基板的平面示意图。 如图 1所示， 阵 列基板（Array Substrate ) 包括： 栅线 1、 数据线 2、 薄膜晶体管 （ Thm Firm Transistor, 简称为 TFT ) 3、 像素电极 4、 公共电极 50以及公共电极线 5。 栅线 1横向设置在透明基板上， 数据线 2纵向设置在透明基板之上， 栅线 1 与数据线 2的交叉处设置有 TFT3。 TFT3为有源开关元件。 像素电极 4为狭 缝电极。 公共电极 50位于像素电极 4的下方， 且大部分重叠， 公共电极 50 与像素电极形成用于驱动液晶的电场。公共电极线 5与公共电极 50连接。值 得一提的是， 图 1中， 附图标记 "50" 所指并非是长条状的狭缝， 而是狭缝 的下方的板状公共电极。
图 2A-2C为一种 FFS型 TFT-LCD阵列基板的剖面图。 其中， 图 2A为 图 1的 A-A向剖面图，示出了阵列基板像素部分的剖面结构。如图 2A所示， 阵列基板具体还包括： 透明基板 11、 公共电极 50、 栅电极 12、 栅绝缘层 13、 半导体层 14、 掺杂半导体层 15、 源电极 16、 漏电极 17、 钝化层 18。 栅电极 12与栅线 1一体成型， 源电极 16与数据线 2一体成型， 漏电极 17与像素电 极 4一般通过飩化层过孔 180 ( via hole )连接。 当栅线 1中输入导通信号时， 有源层 (半导体层 14和掺杂半导体层 15 )导电， 数据线 2的数据信号可从 源电极 16经 TFT沟道（channel ) 19到达漏电极 17， 最终输入至像素电极 4。 像素电极 4得到信号后与板状的公共电极 50形成用于驱动液晶转动的电场。 由于像素电极 4具有狭缝 49， 因此与公共电极 50形成水平电场。
图 2B为一种 FFS型 TFT-LCD P车列基板的 PAD区域的数据线的剖面图； 图 2C为一种 FFS型 TFT-LCD阵列基板的 PAD区域的栅线的剖面图。 PAD 区域即为压接区域， 是将栅线、 数据线及公共电极线等信号线与外部的驱动 电路板的引线压接的区域。 PAD区域位于阵列基板的 4个边中的其中一个或 相邻的两个边上。 为了将引线和信号线电连接， PAD 区域的信号线上方必须 没有绝缘层覆盖。 从图 2B及 2C中可以看出 , PAD区域的数据线 2和栅线 1 上方皆开设有连接孔 181、 182, 附图标记 700所指的结构是通过刻蚀透明导 电薄膜形成像素电极时同时形成的透明导电层， 可导电， 图 2B中的附图标记 300和 400是刻蚀掺杂半导体薄膜和半导体薄膜时形成的结构，不影响数据线 2的通信。如此可以将外部引线直接焊接在图 2B及 2C的透明导电层 700上， 实现阵列基板与驱动电路板的连接。 同理， 公共电极线上方也同样开设有连 接孔， 用于与外部的引线连接， 其结构与图 2C大体相同， 图略。
但是， 在上述的 FFS型 TFT-LCD阵列基板的制造方法中， 需要 5次构 图工艺， 成本较高， 市场竟争力低下； 而且， 上述步骤 3中， 为了形成 TFT 沟道、 源电极及漏电极， 需要对整个基板进行两次刻蚀， 一般采用湿法刻蚀 进行， 即将基板浸泡于刻蚀液中， 去掉没有被光刻胶所覆盖且可被该刻蚀液 侵蚀的部分。 TFT沟道被湿法刻蚀时， 需要严格控制刻蚀参数， 通常用控制 刻蚀时间的方法进行。 但是由于工艺误差存在， 经常会发生 TFT沟道被过度 刻蚀 （Over Etch )。 对于阵列基板具有重大意义的 TFT沟道， 这种过度刻蚀 会产生不可忽视的缺陷， 会引起 TFT沟道变宽或直接破坏 TFT沟道， 对液 晶显示器的整体性能及产品合格率产生极大的负面影响。 因此， 需要进行一 定的改进。
图 3为根据本发明实施例 1的 FFS型 TFT-LCD阵列基板的制造方法的 流程图。 如图 3所示， 本发明实施例 1的 FFS型 TFT-LCD阵列基板的制造 方法， 包括：
步骤 1: 在透明基板上依次形成第一透明导电薄膜、 第一金属薄膜及掺 杂半导体薄膜， 然后第一透明导电薄膜、 第一金属薄膜及掺杂半导体薄膜的 叠层进行构图， 形成包括源电极、 漏电极、 数据线和像素电极的图形；
步骤 2: 形成半导体薄膜， 对所述半导体薄膜进行构图， 形成摻杂半导 体层的图形及包括 TFT沟道的半导体层的图形；
步骤 3: 沉积绝缘薄膜和第二金属薄膜、 对绝缘薄膜和第二金属薄膜进 行构图， 形成包括 PAD区域数据线连接孔、栅线、 栅电极以及公共电极线的 图形；
步骤 4、 形成第二透明导电薄膜， 对第二透明导电薄膜进行构图， 形成包 括公共电极的图形。
本发明实施例的 FFS型 TFT-LCD阵列基板的制造方法，通过四次构图工 艺制造了 FFS型 TFT-LCD阵列基板， 相比现有技术， 减少了工艺数， 极大地 节省了成本， 提高了市场竟争力。
下面结合图 4A-图 23C详细说明根据本发明实施例 1的 FFS型 TFT-LCD 阵列基板的制造方法。
首先根据图 4A-图 9C详细说明根据本发明实施例 1的 FFS型 TFT-LCD 阵列基板的制造方法的第一构图工艺。 如图 4A-图 9C所示， 根据本发明的实 施例 1的 FFS型 TFT-LCD阵列基板的制造方法的第一构图工艺包括如下步 骤：
步骤 11 : 在所述透明基板 11上依次沉积第一透明导电薄膜 100、 第一金 属薄膜 200及掺杂半导体薄膜 400, 如图 4A-图 4C。
可采用等离子体增强化学气相沉积 （PECVD )、 磁控溅射、 热蒸发或其 它成膜方法， 在透明基板 11 (如玻璃基板或石英基板）上依次沉积第一透明 导电薄膜 100、第一金属薄膜 200及掺杂半导体薄膜 400; 第一透明导电薄膜 100可以为 ITO、 ΙΖΟ等透明导电材料。 第一金属薄膜 200可以是钼、 铝、 铝钕合金、 钨、 铬、 铜等金属形成的单层薄膜， 也可以是以上金属多层沉积 形成的多层薄膜。
步骤 12: 在图 4Α-图 4C 的结构的掺杂半导体薄膜 400上涂敷光刻胶 1000, 通过预制的掩模板对所述光刻胶进行曝光及显影处理。 此步骤中釆用 的掩模板为双色调掩模板 (例如半色调掩模板或灰色调掩模板）。双色调掩模 板根据光的透过程度或强度， 可分为完全漏光区域、 部分漏光区域及不漏光 区域。 通过此掩模板进行曝光处理后， 光刻胶 100形成不曝光区域、 部分曝 光区域及完全曝光区域， 然后经显影处理， 完全曝光区域的光刻胶被药剂洗 去； 部分曝光区域的光刻胶中， 上层被曝光而洗去， 留下下层光刻胶， 由此 光刻胶层的厚度降低； 不曝光区域的光刻胶厚度保持不变。 本步骤的光刻胶 1000中， 其不曝光区域对应阵列基板的数据线 2 (参阅图 1 )、 源电极及漏电 极的区域， 所述部分曝光区域对应所述阵列基板的像素电极 4 (参阅图 1 )的 区域， 所述完全曝光区域对应所述阵列基板的其余区域， 如图 5A-图 5C。
步骤 13: 对图 5A-图 5C的结构进行刻蚀工艺， 去掉所述完全曝光区域 的掺杂半导体薄膜 400、第一金属薄膜 200和第一透明导电薄膜 100，形成包 括数据线 2及像素电极 4的图形。 本步骤的刻蚀工艺包括三步刻蚀。 第一步 是采用掺杂半导体材料的刻蚀液， 对掺杂半导体薄膜 400进行刻蚀， 第二步 是采用金属材料刻蚀液（例如磷酸和硝酸的混合物）对第一金属薄膜 200进 行刻蚀， 得到了数据线 2的图形， 第三步是用 ITO或 IZO的刻蚀液， 去掉第 一透明导电薄膜 100, 形成了像素电极 4的图形， 如图 6A-图 6C。 实际生产 中， 刻蚀大面积图形可以采用湿法刻蚀。 所谓湿法刻蚀是将被刻蚀物投入刻 蚀液中， 使得刻蚀液腐蚀掉暴露出的被刻蚀物。 金属材料刻蚀液仅能刻蚀掉 金属材料， 即第一金属薄膜。 被光刻胶覆盖的区域， 也就是部分曝光区域及 不曝光区域的薄膜， 由于有光刻胶保护而没有被腐蚀。完全曝光区域的薄膜， 由于直接与刻蚀液接触而被刻蚀掉。 残留的薄膜形成所要的图形。
步骤 14: 对图 6A-图 6C的光刻胶 100进行灰化工艺， 暴露出所述部分 曝光区域的掺杂半导体薄膜 400, 如图 7A-图 7C。 灰化工艺的作用为去掉一 定厚度的光刻胶。此步骤中，去掉的光刻胶厚度与步骤 12中部分曝光区域所 保留的光刻胶厚度相同， 即灰化工艺后， 光刻胶仅在不曝光区域还有保留， 其他区域无光刻胶剩余。
步骤 15: 对图 7A-图 7C的结构进行刻蚀工艺， 去掉部分曝光区域的摻 杂半导体薄膜 400和第一金属薄膜 200， 形成包括源电极 16及漏电极 17的 图形， 如图 8A-图 8C。 此步骤的刻蚀工艺包括两步刻蚀。 先刻蚀掺杂半导体 薄膜 400， 然后刻蚀第一金属薄膜 200， 从而形成了源电极 16和漏电极 17， 并且暴露出了像素电极 4。
步骤 16: 剥离图 8A-图 8C中剩余的光刻胶 1000， 如图 9A-图 9C。
下面根据图 10A-图 13C 详细说明根据本发明的实施例 1 的 FFS 型 TFT-LCD阵列基板的制造方法的第二构图工艺。 该第二构图工艺包括如下步 骤：
步骤 21 : 在图 9A-图 9C的结构上， 沉积半导体薄膜 300, 如图 10A-图 步骤 22: 在图 10A-图 10C的半导体薄膜 300上涂覆光刻胶 2000, 通过 预制的掩模板对所述光刻胶进行曝光和显影处理，使得所述光刻胶 2000包括 完全曝光区域及不曝光区域。 所述不曝光区域对应所述阵列基板的半导体层 14 (参阅图 2 )的区域， 所述完全曝光区域对应其余区域， 如图 11A-图 11C。 本步骤采用的掩模板为普通掩模板， 具有完全漏光的区域和不漏光的区域。
步骤 23: 对图 11A-图 11C进行刻蚀工艺， 去掉所述完全曝光区域的半 导体薄膜 300， 形成了半导体层 14和掺杂半导体层 15, 如图 12A-图 12C。 在此步骤中， 对半导体层薄膜 300进行蚀刻的同时也可以一并对掺杂半导体 层 400进行蚀刻。 本步骤中， TFT沟道自然形成， 无需刻蚀。 因此， 可以避 免如现有技术中 ,刻蚀摻杂半导体薄膜形成 TFT沟道时会产生过刻蚀的缺陷 的问题。
步骤 24: 剥离图 12A-图 12C剩余的光刻胶 2000, 如图 13A-图 13C。 下面根据图 14A-图 19C 详细说明根据本发明的实施例 1 的 FFS 型 TFT-LCD阵列基板的制造方法的第三构图工艺。 该第三构图工艺包括如下步 骤：
步骤 31: 在图 13A-图 13C的结构上， 依次沉积绝缘薄膜 500和第二金 属薄膜 600， 如图 14A-图 14C;
步骤 32: 在图 14A-图 14C中的第二金属薄膜上涂覆光刻胶 3000, 通过 预制的掩模板对光刻胶 300进行曝光和显影处理， 使得所述光刻胶 300包括 不曝光区域、 部分曝光区域及完全曝光区域。 所述不曝光区域对应阵列基板 的栅电极 12、 栅线 1及公共电极线 5的区域， 所述完全曝光区域对应所述阵 列基板的 PAD区域的数据线 2的区域，所述部分曝光区域对应所述阵列基板 的其余区域， 如图 15A-图 15C。
步骤 33: 对 15A-图 15C的结构进行刻蚀工艺， 去掉完全曝光区域的第 二金属薄膜 600和绝缘薄膜 500， 形成包括 PAD区域数据线连接孔及栅绝缘 层 13的图形， 如图 16A-图 16C。
步骤 34: 对图 16A-图 16C的光刻胶 3000进行灰化工艺， 暴露出所述部 分曝光区域的所述第二金属薄膜 600, 并且在不曝光区域还保留一定厚度的 光刻胶， 如图 17A-图 17C。
步骤 35: 对图 17A-图 17C的结构进行刻蚀工艺， 去掉所述部分曝光区 域的第二金属薄膜 600, 形成包括公共电极线 5 (参阅图 1 )、 栅电极 12及栅 线 1的图形， 如图 18A-图 18C。
步骤 36: 剥离图 18A-图 18C的剩余光刻胶 3000, 如图 19A-图 19C。 下面才艮据图 20A-图 23C详细说明根据本发明实施例 1的 FFS型 TFT-LCD 阵列基板的制造方法的第四构图工艺。 该第四构图工艺包括如下步骤：
步骤 41 : 在图 19A-图 19C的结构上， 沉积第二透明导电薄膜 700, 如图
20 A-图 20C。
步骤 42:在图 20A-图 20C的第二透明导电薄膜 700上涂覆光刻胶 4000, 通过预制的掩模板对光刻胶 4000进行曝光和显影处理，使得所述光刻胶 4000 形成完全曝光区域及不曝光区域。 所述不曝光区域对应所述阵列基板的公共 电极 50 (参阅图 1 )、 PAD区域的数据线 2以及 PAD区域的栅线 1的区域， 所述完全曝光区域对应其余区域， 如图 21A-图 21C。
步骤 44: 对图 21A-图 21C的结构进行刻蚀工艺， 去掉所述完全曝光区 域的所述第二透明导电薄膜 700 , 形成包括公共电极 50的图形， 如图 22A- 图 22C。
步骤 45: 剥离图 22A-图 22C的剩余光刻胶 4000, 如图 23 A-图 23C。 根据本发明实施例 1的 FFS型 TFT-LCD阵列基板的制造方法，不仅比现 有的五次构图工艺少了一个构图步骤， 还采用了先构图掺杂半导体层， 然后 构图半导体层的方法， 避免了 TFT沟道被过刻蚀， 保障了液晶显示器的生产 品质。
图 24为根据本发明实施例 2的 FFS型 TFT-LCD阵列基板的制造方法的 流程图。 如图 24所示， 本发明的实施例 2的 FFS型 TFT-LCD阵列基板的制 造方法， 包括：
步骤 1: 在透明基板上依次形成第一透明导电薄膜、 第一金属薄膜及掺 杂半导体薄膜， 对第一透明导电薄膜、 第一金属薄膜及掺杂半导体薄膜的叠 层进行构图， 形成包括源电极、 漏电极、 数据线和像素电极的图形；
步骤 2: 沉积半导体薄膜， 对半导体薄膜和掺杂半导体薄膜进行构图， 形成摻杂半导体层的图形及包括 TFT沟道的半导体层的图形；
步骤 3'： 沉积绝缘薄膜和第二金属薄膜、 对绝缘薄膜和第二金属薄膜进 行构图， 然后沉积第二透明导电薄膜， 进行离地剥离工艺及刻蚀工艺， 形成 PAD区域数据线连接孔、 栅线、 栅电极以及公共电极线的图形。
本实施例的 FFS型 TFT-LCD阵列基板的制造方法，通过三次构图工艺制 造了 FFS型 TFT-LCD阵列基板， 相比实施例 1 , 进一步减少了工艺数， 极大 地节省了成本， 提高了市场竟争力。
下面结合图 25A-图 33C详细说明根据本发明实施例 1的 FFS型 TFT-LCD 阵列基板的制造方法。 由于实施例 的第一构图工艺和第二构图工艺与实施 例 1相同， 因此不再赘述。
根据图 25A-图 33C详细说明根据本发明实施例 2的 FFS型 TFT-LCD阵 列基板的制造方法的第三构图工艺。 该第三构图工艺包括如下步骤：
步骤 3Γ： 在图 13A-图 13C得到的结构上依次沉积绝缘薄膜 500及第二 金属薄膜 600, 如图 25A-图 25C。
步骤 32'： 在图 25A-图 25C的第二金属薄膜 600上涂敷光刻胶 3000，， 通过预制的掩模板对所述光刻胶 3000'进行曝光及显影处理， 使得所述光刻 胶 3000'包括不曝光区域、 第一部分曝光区域、 第二部分曝光区域及完全曝 光区域， 其中显影后所述第二部分曝光区域的光刻胶比所述第一部分曝光区 域的光刻胶厚。所述完全曝光区域对应阵列基板的 PAD区域的数据线 2的区 域， 所述第一部分曝光区域对应所述阵列基板的公共电极 50的区域，所述第 二部分曝光区域对应所述阵列基板的栅线 1、 栅电极 12的区域， 所述不曝光 区域对应所述阵列基板的其余区域， 如图 26A-图 26C。 本步骤中采用的掩模 板为三色调掩模板， 具有完全漏光区域、 第一部分漏光区域、 第二部分漏光 区域及不漏光区域， 这 4个区域是漏光的强度或程度来划分的， 第一部分漏 光区域透过的光强大于第二部分漏光区域透过的光强。
步骤 33'： 对图 26A-图 26C的结构进行刻蚀工艺， 去掉所述完全曝光区 域的绝缘薄膜 500及第二金属薄膜 600， 形成包括 PAD区域数据线连接孔及 栅绝缘层 13的图形， 如图 27A-图 27C。 本步骤的刻蚀工艺分两步刻蚀， 先 刻蚀掉第二金属薄膜 600， 然后在刻蚀绝缘薄膜 500。
步骤 34' : 对图 27 A-图 27C的光刻胶 3000， 进行灰化工艺， 暴露出所述 第一部分曝光区域的第二金属薄膜 600, 并且第二部分曝光区域和不曝光区 域还分别保留一定厚度的光刻胶， 如图 28A-图 28C。
步骤 35'： 对图 28A-图 28C的结构进行刻蚀工艺， 去掉所述第一部分曝 光区域的第二金属薄膜 600, 如图 29A-图 29C。
步骤 36' : 对图 29A-图 29C的光刻胶 3000， 进行灰化工艺， 暴露出所述 第二部分曝光区域的第二金属薄膜 600,并且不曝光区域还保留一定厚度的光 刻胶， 如图 30A-图 30C。
步骤 37，： 在图 30A-图 30C的结构上沉积第二透明导电薄膜 700, 如图
31A-图 31C。
步骤 38' : 对图 31A-图 31C的结构进行离地剥离工艺， 去掉所述不曝光 区域的光刻胶 3000， 及沉积在所述光刻胶 3000， 上的所述第二透明导电薄膜
700, 形成包括公共电极 50的图形， 图 32A-图 32C。
步骤 39' : 对图 32A-图 32C的结构进行刻蚀工艺， 去掉所述不曝光区域 的第二金属薄膜 600 , 形成包括栅线 1及栅电极 12的图形。
本实施例的 FFS型 TFT-LCD阵列基板的制造方法，通过三次构图工艺制 造了 FFS型 TFT-LCD阵列基板， 相比实施例 1 , 进一步减少了工艺数， 极大 地节省了成本， 提高了市场竟争力。
图 34为根据本发明实施例 3的 FFS型 TFT-LCD阵列基板的制造方法的 流程图。 如图 34所示， 本发明实施例 3的 FFS型 TFT-LCD阵列基板的制造 方法， 包括：
步骤 100: 在透明基板上依次形成半导体薄膜及掺杂半导体薄膜， 对半 导体薄膜及掺杂半导体薄膜的叠层进行构图， 形成包括半导体层和掺杂半导 体层的图形；
步骤 200: 形成第一透明导电薄膜及第一金属薄膜， 对第一透明导电薄 膜及第一金属薄膜的叠层进行构图， 形成包括源电极、 漏电极、 掺杂半导体 层、 TFT沟道、 数据线和像素电极的图形；
步骤 300: 形成绝缘薄膜、 对绝缘薄膜进行构图， 形成包括 PAD区域数 据线连接孔的图形；
步骤 400、形成第二透明导电薄膜及第二金属薄膜，对第二透明导电薄膜 及第二金属薄膜的叠层进行构图， 形成包括栅线、 栅电极和公共电极的图形。
本发明实施例 3的 FFS型 TFT-LCD阵列基板的制造方法，通过四次构图 工艺制造了 FFS型 TFT-LCD阵列基板， 相比现有技术， 减少了工艺数， 极大 地节省了成本， 提高了市场竟争力。 下面结合图 35A-图 55C详细说明根据本发明实施例 3的 FFS型 TFT-LCD 阵列基板的制造方法。
首先根据图 35A-图 38C详细说明本发明实施例 3的 FFS型 TFT-LCD阵 列基板的制造方法的第一构图工艺。 该第一构图工艺包括如下步骤：
步骤 1100: 在所述透明基板 11上依次沉积半导体薄膜 300及掺杂半导 体薄膜 400， 如图 35A-图 35C。
步骤 1200: 在图 35A-图 35C的掺杂半导体薄膜上涂敷光刻胶 5000, 通 过预制的掩模板对所述光刻胶 5000进行曝光及显影处理，使得所述光刻胶包 括不曝光区域完全曝光区域。 所述不曝光区域对应阵列基板的半导体层 14 的区域，所述完全曝光区域对应所述阵列基板的其余区域，如图 36A-图 36C。
步骤 1300: 对图 36A-图 36C的结构进行刻蚀工艺， 去掉所述完全曝光 区域的掺杂半导体薄膜 400和半导体薄膜 300,形成包括半导体层 14的图形， 如图 37 A-图 37C。
步骤 1400: 剥离图 37A-图 37C中剩余光刻胶 5000, 如图 38A-图 38C„ 本实施例的第一次构图工艺的步骤 100 中， 还可以首先沉积绝缘薄膜， 并在与半导体层一同被构图， 得到半导体层下面形成绝缘层的图形。 该绝缘 层能够防止半导体层和背光模组之间形成寄生电容， 阻碍信号传输。 该绝缘 薄膜优选采用不透明的材料， 例如氮化硅和炭黑的混合物 （制作黑矩阵的材 料）等。 该绝缘薄膜同时能够起到黑矩阵的作用。
下面才艮据图 39A-图 45C详细说明本发明实施例 3的 FFS型 TFT-LCD阵 列基板的制造方法的第二构图工艺。 该第二构图工艺包括如下步骤：
步骤 2100: 在图 38A-图 38C得到的结构上， 依次沉积第一透明导电薄 膜 100及第一金属薄膜 200， 如图 39A-图 39C。
步骤 2200: 在图 39A-图 39C的第一金属薄膜上涂敷光刻胶 6000， 通过 预制的掩模板对所述光刻胶 6000进行曝光及显影处理，使得所述光刻胶 6000 包括不曝光区域、 部分曝光区域及完全曝光区域。 所述不曝光区域对应阵列 基板的数据线 2、 源电极 16及漏电极 17的区域， 所述部分曝光区域对应所 述阵列基板的像素电极 4的区域， 所述完全曝光区域对应所述阵列基板的其 余区域， 如图 40A-图 40C。
步骤 2300: 对图 40A-图 40C的结构进行刻蚀工艺， 去掉所述完全曝光 区域的第一金属薄膜 200和第一透明导电薄膜 100 , 形成包括数据线 2及像 素电极 4的图形， 如图 41A-图 41C。
步骤 2400: 对图 41A-图 41C的光刻胶 6000进行灰化工艺， 暴露出所述 部分曝光区域的第一金属薄膜 200, 并且在不曝光区域还保留有部分厚度的 光刻胶， 如图 42A-图 42C。
步骤 2500: 对图 42A-图 42C的结构进行刻蚀工艺， 去掉所述部分曝光 区域的第一金属薄膜 200和掺杂半导体薄膜 400 , 形成包括 TFT沟道 19、 源 电极 16及漏电极 17的图形， 如图 43A-图 44C。
步骤 2600: 剥离图 44A-图 44C中剩余光刻胶 6000, 如图 45A-图 45C。 下面根据图 46A-图 49C详细说明本发明实施例 2的 FFS型 TFT-LCD阵 列基板的制造方法的第三构图工艺。 该第三构图工艺包括如下步骤：
步骤 3100: 在图 45 A-图 45C得到的结构上， 沉积绝缘薄膜 500, 如图 46 A-图 46C。
步骤 3200: 在图 46A-图 46C的绝缘薄膜 500上涂敷光刻胶 7000, 通过 预制的掩模板对所述光刻胶 7000进行曝光及显影处理，使得所述光刻胶 7000 包括不曝光区域完全曝光区域。所述完全曝光区域对应阵列基板的 PAD区域 的数据线 2的区域，所述不曝光区域对应所述阵列基板的其余区域,如图 47 A- 图 47C。
步骤 3300: 对图 47 A-图 47C的结构进行刻蚀工艺， 去掉所述完全曝光 区域的绝缘薄膜 500 , 形成包括栅绝缘层 13的图形， 如图 48A-图 48C。
步驟 3400: 剥离图 48A-图 48C中剩余光刻胶 7000， 如图 49A-图 49C。 下面才 据图 50A-图 55C详细说明本发明实施例 2的 FFS型 TFT-LCD阵 列基板的制造方法的第四构图工艺。 该第三构图工艺包括如下步骤：
步骤 4100: 在图 49A-图 49C的结构上， 沉积第二透明导电薄膜 700和 第二金属薄膜 600， 如图 50A-图 50C。
步骤 4200: 在图 50A-图 50C的第二金属薄膜 600上涂覆光刻胶 8000 , 通过预制的掩模板对光刻胶 8000进行曝光和显影处理，使得所述光刻胶包括 不曝光区域、 部分曝光区域及完全曝光区域。 所述不曝光区域对应阵列基板 的栅电极 12、栅线 1、公共电极线 5及 PAD区域的数据线 2的区域， 所述部 分曝光区域对应所述阵列基板的公共电极 50的区域，所述完全曝光区域对应 所述阵列基板的其余区域， 如图 51A-图 51C。
步骤 4300: 对图 51A-图 51C的结构进行刻蚀工艺， 去掉完全曝光区域 的第二金属薄膜 600和第二透明导电薄膜 700， 形成包括栅线 1、 栅电极 12、 公共电极线 5及公共电极 50的图形， 如图 52A-图 52C。
步骤 4400： 对图 52A-图 52C的光刻胶 8000进行灰化工艺， 暴露出所述 部分曝光区域的所述第二金属薄膜 600, 并且在不曝光区域还保留有部分厚 度的光刻胶， 如图 53A-图 53C。
步骤 4500: 对图 53 A-图 53C的结构进行刻蚀工艺， 去掉所述部分曝光 区域的第二金属薄膜 600, 暴露出公共电极 50, 如图 54A-图 54C。
步骤 4600: 剥离图 54A-图 54C剩余光刻胶， 如图 55A-图 55C。
根据实施例 2的启示，本领域技术人员可以很容易对实施例 3的步骤 300 和 400进行合并而仅进行一次构图工艺， 进一步减少工艺数， 节省成本， 提 高市场竟争力。
以上以正性光刻胶为例进行了描述， 显影之后不曝光区域的光刻胶是完 全保留的， 完全曝光区域的光刻胶被全部去除， 而部分曝光区域的曝光区域 的光刻胶是部分保留的。 但本发明的实施例不限于正性光刻胶， 如杲采用负 性光刻胶， 则显影之后光刻胶的完全曝光区域中的光刻胶是完全保留的， 而 非曝光区域中的光刻胶被全部去除， 而部分曝光区域中的光刻胶仍然是部分 保留的。 最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对其 限制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通技术 人员应当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或 者对其中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技 术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、 一种 FFS型 TFT-LCD阵列基板的制造方法， 包括：
步骤 1: 在透明基板上依次形成第一透明导电薄膜、 第一金属薄膜及掺 杂半导体薄膜， 然后对所述第一透明导电薄膜、 所述第一金属薄膜及所述掺 杂半导体薄膜的叠层进行构图， 形成包括源电极、 漏电极、 数据线和像素电 极的图形；
步骤 2: 形成半导体薄膜， 对所述半导体薄膜进行构图， 形成掺杂半导 体层的图形及包括 TFT沟道的半导体层的图形；
步骤 3: 形成绝缘薄膜和第二金属薄膜、 对所述绝缘薄膜和所述第二金 属薄膜的叠层进行构图， 形成包括 PAD区域数据线连接孔、 栅线、 栅电极以 及公共电极线的图形；
步骤 4、 形成第二透明导电薄膜， 对所述第二透明导电薄膜进行构图， 形成包括公共电极的图形。
2、 根据权利要求 1所述的 FFS型 TFT-LCD阵列基板的制造方法， 所述 步骤 1包括：
步骤 11 : 在所述透明基板上依次沉积所述第一透明导电薄膜、 所述第一 金属薄膜及所述摻杂半导体薄膜；
步骤 12: 在所述掺杂半导体薄膜上涂敷第一光刻胶， 通过预制的掩模板 对所述光刻胶进行曝光及显影处理， 使得所述光刻胶包括光刻胶完全保留区 域、 光刻胶部分保留区域及光刻胶完全去除区域， 其中所述光刻胶完全保留 区域对应阵列基板的数据线、 源电极及漏电极的区域， 所述光刻胶部分保留 区域对应所述阵列基板的像素电极的区域， 所述光刻胶完全去除区域对应所 述阵列基板的其余区域；
步骤 13: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述掺杂半导 体薄膜、 所述第一金属薄膜和所述第一透明导电薄膜， 形成包括数据线及像 素电极的图形；
步骤 14: 对所述第一光刻胶进行灰化工艺， 暴露出所述光刻胶部分保留 区域的掺杂半导体薄膜， 并且在所述光刻胶完全保留区域保留有部分厚度的 第一光刻胶； 步骤 15: 进行刻蚀工艺， 去掉所述光刻胶部分保留区域的所述摻杂半导 体薄膜和所述第一金属薄膜， 形成包括源电极及漏电极的图形；
步骤 16: 剥离剩余的第一光刻胶。
3、 根据权利要求 1所述的 FFS型 TFT-LCD阵列基板的制造方法， 所述 步骤 2包括：
步骤 21 : 在通过步骤 1得到的结构上， 沉积所述半导体薄膜； 步骤 22: 在所述半导体薄膜上涂覆第二光刻胶， 通过预制的掩模板对所 述第二光刻胶进行曝光和显影处理， 使得所述第二光刻胶包括光刻胶完全去 除区域及光刻胶完全保留区域， 其中所述光刻胶完全保留区域对应所述阵列 基板的半导体层的区域， 所述光刻胶完全去除区域对应其余区域；
步骤 23: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述半导体薄 膜；
步骤 24: 剥离剩余的第二光刻胶。
4、 根据权利要求 1所述的 FFS型 TFT-LCD阵列基板的制造方法， 所述 步骤 3包括：
步骤 31 : 在通过步骤 2得到的结构上， 沉积所述绝缘薄膜和所述第二金 属薄膜；
步驟 32: 在所述第二金属薄膜上涂覆第三光刻胶， 通过预制的掩模板对 光刻胶进行曝光和显影处理， 使得所述光刻胶包括光刻胶完全保留区域、 光 刻胶部分保留区域及光刻胶完全去除区域， 其中所述光刻胶完全保留区域对 应阵列基板的栅电极、 栅线及公共电极线的区域， 所述光刻胶完全去除区域 对应所述阵列基板的 PAD区域的数据线的区域，所述光刻胶部分保留区域对 应所述阵列基板的其余区域；
步骤 33: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述第二金属 薄膜和所述绝缘薄膜， 形成包括 PAD区域数据线连接孔及栅绝缘层的图形； 步骤 34: 对所述第三光刻胶进行灰化工艺， 暴露出所述光刻胶部分保留 区域的所述第二金属薄膜， 并在所述光刻胶完全保留区域保留有部分厚度的 第三光刻胶；
步骤 35: 进行刻蚀工艺， 去掉所述光刻胶部分保留区域的所述第二金属 薄膜， 形成包括公共电极线、 栅电极及栅线的图形； 步骤 36: 剥离剩余的第三光刻胶。
5、 根据权利要求 1所述的 FFS型 TFT-LCD阵列基板的制造方法， 所述 步骤 4包括：
步骤 41 : 在通过步骤 3得到的结构上， 沉积所述第二透明导电薄膜； 步骤 42: 在所述第二透明导电薄膜上涂覆第四光刻胶， 通过预制的掩模 板对所述第四光刻胶进行了曝光和显影处理， 使得所述第四光刻胶包括光刻 胶完全去除区域及光刻胶完全保留区域， 其中所述光刻胶完全保留区域对应 所述阵列基板的公共电极、 PAD区域的数据线以及 PAD区域的栅线的区域， 所述光刻胶完全去除区域对应其余区域；
步骤 43: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述第二透明 导电薄膜， 形成包括公共电极的图形；
步骤 44: 剥离剩余的第四光刻胶。
6、 一种 FFS型 TFT-LCD阵列基板的制造方法， 包括：
步骤 1: 在透明基板上依次形成第一透明导电薄膜、 第一金属薄膜及掺 杂半导体薄膜， 对所述第一透明导电薄膜、 所述第一金属薄膜及所述摻杂半 导体薄膜的叠层进行构图， 形成包括源电极、 漏电极、 数据线和像素电极的 图形；
步骤 2: 形成半导体薄膜， 对所述半导体薄膜进行构图， 形成掺杂半导 体层的图形及包括 TFT沟道的半导体层的图形；
步骤 3，： 形成绝缘薄膜和第二金属薄膜、 对所述绝缘薄膜和所述第二金 属薄膜进行构图， 然后形成第二透明导电薄膜， 进行离地剥离工艺及刻蚀工 艺， 形成 PAD区域数据线连接孔、 栅线、 栅电极以及公共电极线的图形。
7、 根据权利要求 6所述的 FFS型 TFT-LCD阵列基板的制造方法， 所述 步骤 1包括：
步骤 11 : 在所述透明基板上依次沉积所述第一透明导电薄膜、 所述第一 金属薄膜及所述掺杂半导体薄膜；
步骤 12: 在所述掺杂半导体薄膜上涂敷第一光刻胶， 通过预制的掩模板 对所述第一光刻胶进行曝光及显影处理， 使得所述第一光刻胶包括光刻胶完 全保留区域、 光刻胶部分保留区域及光刻胶完全去除区域， 其中所述光刻胶 完全保留区域对应阵列基板的数据线、 源电极及漏电极的区域， 所述光刻胶 部分保留区域对应所述阵列基板的像素电极的区域， 所述光刻胶完全去除区 域对应所述阵列基板的其余区域；
步骤 13: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述掺杂半导 体薄膜、 所述第一金属薄膜和所述透明导电薄膜， 形成包括数据线及像素电 极的图形；
步骤 14: 对所述第一光刻胶进行灰化工艺， 暴露出所述光刻胶部分保留 区域的掺杂半导体薄膜， 并且所述光刻胶完全保留区域保留有部分厚度的第 一光刻胶；
步骤 15: 进行刻蚀工艺， 去掉所述光刻胶部分保留区域的所述掺杂半导 体薄膜和所述第一金属薄膜， 形成包括源电极及漏电极的图形；
步骤 16: 剥离剩余的第一光刻胶。
8、 根据权利要求 6所述的 FFS型 TFT-LCD阵列基板的制造方法， 所述 步骤 2包括：
步骤 21 : 在通过步骤 1得到的结构上， 沉积所述半导体薄膜； 步骤 22: 在所述半导体薄膜上涂覆第二光刻胶， 通过预制的掩模板对所 述第二光刻胶进行曝光和显影处理， 使得所述第二光刻胶包括光刻胶完全去 除区域及光刻胶完全保留区域， 其中所述光刻胶完全保留区域对应所述阵列 基板的半导体层的区域， 所述光刻胶完全去除区域对应其余区域；
步 23： 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的半导体薄膜， 形成所述掺杂半导体层的图形及包括 TFT沟道的半导体层的图形；
步驟 24: 剥离剩余的第二光刻胶。
9、 根据权利要求 6所述的 FFS型 TFT-LCD阵列基板的制造方法， 所述 步骤 3' 具体包括：
步骤 31，： 在通过步骤 2得到的结构上依次沉积所述绝缘薄膜及所述第 二金属薄膜；
步骤 32，： 在所述第二金属薄膜上涂敷第三光刻胶， 通过预制的掩模板 对所述光刻胶进行曝光及显影处理， 使得所述第三光刻胶包括光刻胶完全保 留区域、 第一光刻胶部分保留区域、 第二光刻胶部分保留区域及光刻胶完全 去除区域， 其中显影之后所述第二光刻胶部分保留区域的光刻胶比所述第二 光刻胶部分保留区域的光刻胶厚， 所述光刻胶完全去除区域对应阵列基板的 PAD区域的数据线的区域， 所述第一光刻胶部分保留区域对应所述阵列基板 的公共电极的区域，所述第二光刻胶部分保留区域对应所述阵列基板的栅线、 栅电极的区域， 所述光刻胶完全保留区域对应所述阵列基板的其余区域； 步骤 33，： 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述绝缘薄 膜及所述第二金属薄膜， 形成包括 PAD 区域数据线连接孔及栅绝缘层的图 形；
步骤 34，： 对所述第三光刻胶进行灰化工艺， 暴露出所述第一光刻胶部 分保留区域的第二金属薄膜， 并且在所述第二光刻胶部分保留区域和所述光 刻胶完全保留区域还保留部分厚度的第三光刻胶；
步骤 35，： 进行刻蚀工艺， 去掉所述第一光刻胶部分保留区域的第二金 属薄膜；
步骤 36，： 对步骤 35， 的所述光刻胶进行灰化工艺， 暴露出所述第二光 刻胶部分保留区域的第二金属薄膜， 并且在所述光刻胶完全保留区域还保留 部分厚度的第三光刻胶；
步骤 37' : 沉积所述第二透明导电薄膜；
步骤 38' : 进行离地剥离工艺， 去掉所述光刻胶完全保留区域的第三光刻 胶及沉积在所述第三光刻胶上的所述第二透明导电薄膜， 形成包括公共电极 的图形；
步骤 39' : 进行刻蚀工艺， 去掉所述光刻胶完全保留区域的所述第二金属 薄膜， 形成包括栅线及栅电极的图形。
10、 一种 FFS型 TFT-LCD阵列基板的制造方法， 包括：
步骤 100: 在透明基板上依次形成半导体薄膜及掺杂半导体薄膜， 对所 述半导体薄膜及所述掺杂半导体薄膜的叠层进行构图， 形成包括半导体层和 掺杂半导体层的图形；
步骤 200: 形成第一透明导电薄膜及第一金属薄膜， 对所述第一透明导 电薄膜及所述第一金属薄膜的叠层进行构图， 形成包括源电极、 漏电极、 掺 杂半导体层、 TFT沟道、 数据线和像素电极的图形；
步骤 300: 形成绝缘薄膜、 对所述绝缘薄膜进行构图， 形成包括 PAD区 域数据线连接孔的图形；
步骤 400、形成第二透明导电薄膜及第二金属薄膜，对所述第二透明导电 薄膜及所述第二金属薄膜的叠层进行构图， 形成包括栅线、 栅电极和公共电 极的图形。
11、 根据权利要求 10所述的 FFS型 TFT-LCD阵列基板的制造方法， 所 述步骤 100包括：
步骤 1100: 在所述透明基板上依次沉积所述半导体薄膜及所述掺杂半导 体薄膜；
步骤 1200: 在所述掺杂半导体薄膜上涂敷第一光刻胶， 通过预制的掩模 板对所述第一光刻胶进行曝光及显影处理， 使得所述第一光刻胶包括光刻胶 完全保留区域光刻胶完全去除区域， 其中所述光刻胶完全保留区域对应所述 阵列基板的半导体层的区域， 所述光刻胶完全去除区域对应所述阵列基板的 其余区域；
步骤 1300: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述掺杂半 导体薄膜和所述半导体薄膜， 形成包括半导体层的图形；
步骤 1400: 剥离剩余的第一光刻胶。
12、 根据权利要求 10所述的 FFS型 TFT-LCD阵列基板的制造方法， 所 述步骤 200包括：
步骤 2100: 在步骤 100得到的结构上， 依次沉积所述第一透明导电薄膜 及所述第一金属薄膜；
步骤 2200: 在所述第一金属薄膜上涂敷第二光刻胶， 通过预制的掩模板 对所述第二光刻胶进行曝光及显影处理， 使得所述第二光刻胶包括光刻胶完 全保留区域、 光刻胶部分保留区域及光刻胶完全去除区域， 其中所述光刻胶 完全保留区域对应所述阵列基板的数据线、 源电极及漏电极的区域， 所述光 刻胶部分保留区域对应所述阵列基板的像素电极的区域， 所述光刻胶完全去 除区域对应所述阵列基板的其余区域；
步骤 2300: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述第一金 属薄膜和所述第一透明导电薄膜， 形成包括数据线及像素电极的图形；
步骤 2400: 对所述第二光刻胶进行灰化工艺， 暴露出所述光刻胶部分保 留区域的第一金属薄膜， 并且在所述光刻胶完全保留区域保留有部分厚度的 第二光刻胶；
步骤 2500: 进行刻蚀工艺， 去掉所述光刻胶部分保留区域的所述第一金 属薄膜和所述掺杂半导体薄膜，形成包括 TFT沟道、源电极及漏电极的图形； 步骤 2600: 剥离剩余的第二光刻胶。
13、 根据权利要求 10所述的 FFS型 TFT-LCD阵列基板的制造方法， 所 述步骤 300包括：
步骤 3100: 在步骤 200得到的结构上， 沉积所述绝缘薄膜；
步骤 3200: 在所述绝缘薄膜上涂敷第三光刻胶， 通过预制的掩模板对所 述第三光刻胶进行曝光及显影处理 , 使得所述第三光刻胶包括光刻胶完全保 留区域光刻胶完全去除区域， 其中所述光刻胶完全去除区域对应所述阵列基 板的 PAD区域的数据线的区域，所述光刻胶完全保留区域对应所述阵列基板 的其余区域；
步骤 3300: 进行刻蚀工艺， 去掉所述光刻胶完全去除区域的所述绝缘薄 膜， 形成包括栅绝缘层的图形；
步骤 3400： 剥离剩余第三光刻胶。
14、 根据权利要求 10所述的 FFS型 TFT-LCD阵列基板的制造方法， 所 述步骤 400包括：
步骤 4100： 在通过步骤 300得到的结构上， 沉积所述第二透明导电薄膜 和所述第二金属薄膜；
步驟 4200: 在所述第二金属薄膜上涂覆第四光刻胶， 通过预制的掩模板 对所述第四光刻胶进行曝光和显影处理， 使得所述第四光刻胶包括光刻胶完 全保留区域、 光刻胶部分保留区域及光刻胶完全去除区域， 其中所述光刻胶 完全保留区域对应所述阵列基板的栅电极、栅线、公共电极线及 PAD区域的 数据线的区域， 所述光刻胶部分保留区域对应所述阵列基板的公共电极的区 域， 所述光刻胶完全去除区域对应所述阵列基板的其余区域；
步骤 4300: 进行刻蚀工艺， 去掉光刻胶完全去除区域的所述第二金属薄 膜和所述第二透明导电薄膜， 形成包括栅线、 栅电极、 公共电极线及公共电 极的图形；
步骤 4400: 对所述第四光刻胶进行灰化工艺， 暴露出所述光刻胶部分保 留区域的所述第二金属薄膜， 并且在所述光刻胶完全保留区域保留有部分厚 度的第四光刻胶；
步骤 4500: 进行刻蚀工艺， 去掉所述光刻胶部分保留区域的第二金属薄 膜， 暴露出公共电极；
步骤 4600: 剥离剩余的第四光刻胶。
15、 根据权利要求 10所述的 FFS型 TFT-LCD阵列基板的制造方法， 在 所述步骤 100 中在沉积所述半导体薄膜之间形成绝缘薄膜， 并且所述绝缘薄 膜与所述半导体薄膜被一同构图。
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