CN103915380A - 一种阵列基板的制作方法、阵列基板及显示装置 - Google Patents

一种阵列基板的制作方法、阵列基板及显示装置 Download PDF

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Publication number
CN103915380A
CN103915380A CN201410126488.2A CN201410126488A CN103915380A CN 103915380 A CN103915380 A CN 103915380A CN 201410126488 A CN201410126488 A CN 201410126488A CN 103915380 A CN103915380 A CN 103915380A
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Prior art keywords
drain electrode
source electrode
layer
electrode
gate
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CN201410126488.2A
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张金中
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to CN201410126488.2A priority Critical patent/CN103915380A/zh
Publication of CN103915380A publication Critical patent/CN103915380A/zh
Priority to US14/488,029 priority patent/US9466620B2/en
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Abstract

本发明涉及液晶显示领域，尤其涉及一种阵列基板的制作方法、阵列基板及显示装置；本发明实施例提供了一种阵列基板，该阵列基板的源极和漏极与栅极图形之间的栅极绝缘层的厚度大于有源层与栅极图形之间的栅极绝缘层的厚度；由于源极和漏极与栅极图形之间的栅极绝缘层的厚度较厚，使源极和漏极与栅极之间的电容减小，降低了源极、漏极与栅极对应的电容，减少了像素负载，降低了整个显示器件的功耗，减少了不必要的功耗，同时不影响阵列基板的显示效果。

Description

一种阵列基板的制作方法、阵列基板及显示装置
技术领域
本发明涉及液晶显示领域，尤其涉及一种阵列基板的制作方法、阵列基板及显示装置。
背景技术
目前液晶显示器（Liquid Crystal Display，LCD）的主要结构包括液晶面板，液晶面板包括薄膜晶体管（Thin Film Transistor，TFT）阵列基板、彩膜基板，以及位于两基板之间的液晶等材料，其中TFT阵列基板是目前主流的阵列基板。TFT阵列基板一般包括栅极层、栅极绝缘层，有源层、源漏电极层、绝缘保护层、像素电极层等多层结构。非金属层材料的沉积一般采用等离子增强化学沉积方法进行。液晶显示器的重要的改进方向是提高开口率和降低功耗，为了实现具有高开口率，通常TFT阵列基板上具有两层氧化铟锡ITO和多层布线，源极和漏极与栅极之间的电容较大，增加了TFT的负载，使得液晶显示屏功耗很大，由于现在手机电池可使用时间普遍不高，需要降低功耗。现有技术中对于降低源极和漏极与栅极之间的电容方案较少，同时受到有源层自由电子迁移率低的影响，栅极绝缘层电容不能降低太多，否则将会导致充电困难。
因此，现有技术中由于源极和漏极与栅极间的电容较大，增加了TFT的负载，导致像素负载增加，增加整个显示器件的功耗，造成了较高的功耗。
发明内容
本发明实施例提供一种低功耗的阵列基板的制作方法，用以解决现有技术中由于源极和漏极与栅极间的电容较大，增加了TFT的负载，导致像素负载增加，增加整个显示器件的功耗，造成了较高的功耗。
本发明实施例提供了一种低功耗的阵列基板的制作方法，该方法包括：
采用一次构图工艺对源极和漏极之间区域的栅极绝缘层进行部分刻蚀处理；
通过一次构图工艺形成有源层，所述有源层覆盖所述栅极绝缘层部分刻蚀区域；
通过一次构图工艺形成栅极图形，所述栅极图形覆盖栅极绝缘层部分刻蚀区域，及源极和漏极对应的栅极绝缘层区域；
其中，所述栅极图形和所述有源层位于栅极绝缘层不同侧，且所述源极和漏极与所述栅极图形之间的栅极绝缘层的厚度大于所述源极和漏极之间所述有源层与所述栅极图形之间的栅极绝缘层的厚度。
上述实施例中该阵列基板的源极和漏极与栅极图形之间的栅极绝缘层的厚度大于有源层与栅极图形之间的栅极绝缘层的厚度；由于源极和漏极与栅极图形之间的栅极绝缘层的厚度较厚，使源极和漏极与栅极之间的电容减小，并且有源层和栅极图形之间的电容大小没有发生改变，降低了源极和漏极分别对应的Cgs和Cgd电容，减少了像素负载，降低了整个显示器件的功耗，减少了不必要的功耗，同时不影响阵列基板的显示效果。
本发明实施例中采用一次构图工艺对源极和漏极之间区域的栅绝缘层部分刻蚀，具体包括：
通过半曝光工艺对源极和漏极之间区域的栅绝缘层进行部分刻蚀处理，对栅极绝缘层的过孔区域进行全曝光处理，形成栅绝缘层过孔。
上述实施例中通过一次构图工艺形成源极和漏极之间的区域，以及过孔区域，减少了一次构图工艺，简化了制作工艺。
本发明实施例中当所述栅极图形位于靠近衬底基板一侧时，所述方法包括：
在衬底基板上形成栅极图形；
在形成栅极图形的基板上形成栅极绝缘层；
在栅绝缘层上形成有源层；
在有源层上形成源极、漏极、像素电极层；
在源极、漏极、像素电极层上分别形成钝化层和狭缝状公共电极层，所述像素电极与漏极电连接。
当所述栅极图形位于远离衬底基板一侧时，所述方法包括：
在衬底基板上形成有源层；
在有源层上形成源极、漏极和像素电极层；
在源极、漏极和像素电极层上方形成栅极绝缘层；
在栅极绝缘层上方形成栅极图形；
在栅极图形上方分别形成钝化层、狭缝状公共电极层。
上述实施例中栅极绝缘层和有源层分开沉积，对源极和漏极之间的栅极绝缘层进行半曝光模式曝光，将源极和漏极之间的栅极绝缘层部分刻蚀，使有源层与栅极之间的电容基本保持不变；增加了源极漏极和栅极图形之间的栅极绝缘层的厚度，减小了源极漏极和栅极图形之间的电容；并且将过孔构图工艺顺序安排在有源层之前，使整个制作工艺的构图工艺次数保持不变。
本发明实施例中所述栅极绝缘层除源极和漏极之间区域，其他区域的厚度为
上述实施例中源极和漏极与栅极之间的绝缘介质层的厚度较厚，源极和漏极分别与栅极形成的电容也就较小，损耗的电能也就越小，因此大大降低了能量的损耗。
本发明实施例中栅极绝缘层的源极和漏极之间区域的厚度为3000
上述实施例中有源层与栅极形成的电容，用于接收到电流后形成沟道，因此电容不能过小，否则通过的电流较小，容易导致像素单元中激发的色彩暗淡，形成显示不良；本发明实施例中有源层与栅极之间的栅极绝缘层的厚度较小，形成的电容Cga大小不变；即保证了Cga电容的容量。
本发明实施例提供了一种阵列基板，该阵列基板包括：
栅极绝缘层；
覆盖在所述栅极绝缘层一侧的有源层，源极和漏极；
覆盖在所述栅极绝缘层另一侧的栅极图形；
其中所述源极和漏极与所述栅极图形之间的栅极绝缘层的厚度大于所述源极和漏极之间有源层与所述栅极图形之间的栅极绝缘层的厚度。
上述实施例中该阵列基板的源极和漏极与栅极图形之间的栅极绝缘层的厚度大于有源层与栅极图形之间的栅极绝缘层的厚度；由于源极和漏极与栅极图形之间的栅极绝缘层的厚度较厚，使源极和漏极与栅极之间的电容减小，并且有源层和栅极图形之间的电容大小没有发生改变，降低了源极和漏极分别对应的Cgs和Cgd电容，减少了像素负载，降低了整个显示器件的功耗，减少了不必要的功耗，同时不影响阵列基板的显示效果。
本发明实施例中当所述栅极图形位于靠近衬底基板一侧时，所述阵列基板还包括：
形成于衬底基板上的栅极图形；
形成于栅极图形以及衬底基板上的栅极绝缘层；
形成于栅极绝缘层上的有源层；
形成于有源层上的源极、漏极、像素电极层；
形成于源极、漏极、像素电极层上的钝化层和狭缝状公共电极层，所述像素电极与漏极电连接。
当所述栅极图形位于远离衬底基板一侧时，所述阵列基板还包括：
形成于衬底基板上的有源层；
形成于有源层上的源极、漏极和像素电极层；
形成于源极、漏极和像素电极层上方的栅极绝缘层；
形成于栅极绝缘层上方的栅极图形；
形成于栅极图形上方的钝化层、狭缝状公共电极层。
上述实施例中栅极绝缘层和有源层分开沉积，对源极和漏极之间的栅极绝缘层进行半曝光模式曝光，将源极和漏极之间的栅极绝缘层部分刻蚀，使有源层与栅极之间的电容基本保持不变；增加了源极漏极和栅极图形之间的栅极绝缘层的厚度，减小了源极漏极和栅极图形之间的电容；并且将过孔构图工艺顺序安排在有源层之前，使整个制作工艺的构图工艺次数保持不变。
本发明实施例中所述阵列基板上栅极绝缘层除源极和漏极之间区域，其他区域的厚度为
上述实施例中源极和漏极与栅极之间的绝缘介质层的厚度较厚，源极和漏极分别与栅极形成的电容也就较小，损耗的电能也就越小，因此大大降低了能量的损耗。
本发明实施例中所述阵列基板中栅极绝缘层的源极和漏极之间区域的厚度为
上述实施例中有源层与栅极形成的电容，用于接收到电流后形成沟道，因此电容不能过小，否则通过的电流较小，容易导致像素单元中激发的色彩暗淡，形成显示不良；本发明实施例中有源层与栅极之间的栅极绝缘层的厚度较小，形成的电容Cga大小不变；即保证了Cga电容的容量。
本发明实施例提供了一种显示装置，该显示装置含有本发明实施例中任一一种阵列基板。
上述实施例中阵列基板的源极和漏极与栅极图形之间的栅极绝缘层的厚度大于有源层与栅极图形之间的栅极绝缘层的厚度；由于源极和漏极与栅极图形之间的栅极绝缘层的厚度较厚，使源极和漏极与栅极之间的电容减小，并且有源层和栅极图形之间的电容大小没有发生改变，降低了源极和漏极分别对应的Cgs和Cgd电容，减少了像素负载，降低了整个显示器件的功耗，减少了不必要的功耗，同时不影响阵列基板的显示效果。
本发明实施例提供了一种阵列基板，该阵列基板的源极和漏极与栅极图形之间的栅极绝缘层的厚度大于有源层与栅极图形之间的栅极绝缘层的厚度；由于源极和漏极与栅极图形之间的栅极绝缘层的厚度较厚，使源极和漏极与栅极之间的电容减小，并且有源层和栅极图形之间栅极绝缘层的厚度较小，使有源层和栅极图形之间的电容大小没有发生改变，降低了源极、漏极与栅极对应的电容，减少了像素负载，降低了整个显示器件的功耗，减少了不必要的功耗，同时不影响阵列基板的显示效果。
附图说明
图1为本发明实施例中一种阵列基板的制作方法的流程示意图；
图2为本发明实施例中栅极图形位于靠近衬底基板一侧的阵列基板的制作方法的流程示意图；
图3为本发明实施例中一种栅极图形位于靠近衬底基板一侧的阵列基板的具体制作方法的流程示意图；
图4为本发明实施例中形成栅极图形的基板的示意图；
图5为本发明实施例中沉积栅极绝缘层后的基板的示意图；
图6为本发明实施例中涂覆光刻胶并进行曝光处理的基板的示意图；
图7为本发明实施例中去除曝光后的光刻胶的基板的示意图；
图8为本发明实施例中形成过孔图形的基板的示意图；
图9为本发明实施例中灰化工艺处理后的基板的示意图；
图10为本发明实施例中去除源极与漏极之间的区域设定厚度的栅极绝缘层的基板的示意图；
图11为本发明实施例中形成有源层后的基板的示意图；
图12为本发明实施例中形成有源极和漏极的基板的示意图；
图13为本发明实施例中形成像素电极图形的基板的示意图；
图14为本发明实施例中沉积钝化层的基板的示意图；
图15为本发明实施例中形成的阵列基板的示意图；
图16为本发明实施例中形成的阵列基板的钝化层后过孔处的剖面图；
图17为本发明实施例中栅极图形位于远离衬底基板一侧的阵列基板的制作方法的流程示意图；
图18为本发明实施例中栅极图形位于远离衬底基板一侧的阵列基板的具体制作方法的流程示意图；
图19为本发明实施例中另一种形成有源层的基板的示意图；
图20为本发明实施例中另一种沉积源极和漏极后的基板的示意图；
图21为本发明实施例中另一种形成像素电极图形的基板的示意图；
图22为本发明实施例中另一种沉积栅极绝缘层后的基板的示意图；
图23为本发明实施例中另一种形成过孔图形和去除源极和漏极之间区域的设定厚度栅极绝缘层的基板的示意图；
图24为本发明实施例中另一种形成栅极图形的基板的示意图；
图25为本发明实施例中另一种沉积钝化层的基板的示意图；
图26为本发明实施例中另一种形成的阵列基板的示意图；
图27为本发明实施例中当阵列基板的源极和漏极之间的区域处于开态时像素单元电路结构示意图；
图28为本发明实施例中当阵列基板的源极和漏极之间的区域处于关态时像素单元电路结构示意图；
图29为本发明实施例中栅极图形位于靠近衬底基板一侧的阵列基板的示意图；
图30为本发明实施例中栅极图形位于远离衬底基板一侧的阵列基板的示意图。
具体实施方式
本发明实施例提供了一种低功耗的阵列基板，该阵列基板源极和漏极与栅极图形之间的栅极绝缘层的厚度大于源极和漏极之间有源层与栅极图形之间的栅极绝缘层的厚度；由于源极和漏极与栅极图形之间栅极绝缘层的厚度较厚，使源极和漏极与栅极之间的电容减小，降低了源极和漏极与栅极之间的电容，减少了像素负载，降低了整个显示器件的功耗，减少了不必要的功耗。
下面结合说明书附图对本发明实施例进行进一步说明。
如图1所示，为本发明实施例中一种阵列基板的制作方法，该方法包括：
步骤101：采用一次构图工艺对源极和漏极之间区域的栅极绝缘层进行部分刻蚀处理；
步骤102：通过一次构图工艺形成有源层，有源层覆盖栅极绝缘层部分刻蚀区域；
步骤103：通过一次构图工艺形成栅极图形，栅极图形覆盖栅极绝缘层部分刻蚀区域，及源极和漏极对应的栅极绝缘层区域；
其中，栅极图形和有源层位于栅极绝缘层不同侧，且源极和漏极与栅极图形之间的栅极绝缘层的厚度大于源极和漏极之间有源层与栅极图形之间的栅极绝缘层的厚度。
步骤101中，采用一次构图工艺对源极和漏极之间区域的栅绝缘层部分刻蚀，具体包括：通过半曝光工艺对源极和漏极之间区域的栅绝缘层进行部分刻蚀处理，对栅极绝缘层的过孔区域进行全曝光处理，形成栅绝缘层过孔。在栅极绝缘层上涂覆一层光刻胶，对栅极图形对应的源极和漏极之间的区域的光刻胶通过半透膜或光栅进行半曝光处理，对栅极图形对应的过孔区域的光刻胶进行全曝光处理，通过曝光显影处理，去除过孔区域全部的光刻胶以及源极和漏极之间的区域被曝光厚度的光刻胶。
本发明实施例中栅极绝缘层除源极和漏极之间区域，其他区域的厚度为栅极绝缘层的源极和漏极之间区域的厚度为
传统的阵列基板的制作方法中，源极和漏极之间的区域在通电情况下形成沟道；传统的TFT的电容包括栅极与源极间的电容Cgs，栅极与有源层之间的电容Cga，栅极与漏极之间的电容Cgd；其中影响TFT特性的电子分布主要与Cga相关，电流通过Cga电容形成沟道，使电子定向迁移至像素电极；通过电流控制像素电极时，电流需要先通过源极，再通过沟道区域，然后通过漏极，最后通过与漏极搭接的第一ITO层，将电流传输至像素电极；当电流通过源极和漏极时，由于存在电容Cgs和电容Cgd，导致电流通过源极和漏极时需要较大的电流强度才能打破Cgs和Cgd的能量势垒，形成大的电流强度就需要较大的电压，电压越高转化成其他能量的能耗就越高，形成不必要的功耗。
有源层与栅极形成的电容，用于接收到电流后形成沟道，因此电容不能过小，否则通过的电流较小，容易导致像素单元中激发的色彩暗淡，形成显示不良；本发明实施例中有源层与栅极之间的栅极绝缘层的厚度在与现有技术中的有源层与栅极之间的栅极绝缘层之间的厚度基本一致，形成的电容Cga大小不变；即保证了Cga电容的容量。
根据本发明实施例中阵列基板的制作方法可以制作两种不同的阵列基板，下面对这两种情况分别进行描述。
实施例一、如图2所示，为本发明实施例中栅极图形位于靠近衬底基板一侧的阵列基板的制作方法，该方法包括：
步骤201：在衬底基板上形成栅极图形；
步骤202：在形成栅极图形的基板上形成栅极绝缘层；
步骤203：在栅绝缘层上形成有源层；
步骤204：在有源层上形成源极、漏极、像素电极层；
步骤205：在源极、漏极、像素电极层上分别形成钝化层和狭缝状公共电极层，像素电极与漏极电连接。
其中，步骤201中在衬底基板上形成栅极图形具体包括：在衬底基板上通过一次构图工艺形成栅极图形。
步骤202中在形成栅极图形的基板上形成栅极绝缘层；在形成栅极图形的基板上形成的栅极绝缘层的厚度约为现有技术中栅极绝缘层厚度的2倍，约
步骤203中在栅绝缘层上形成有源层，具体包括：在栅极绝缘层上涂覆一层光刻胶，并通过曝光显影工艺对栅极图形对应的源极和漏极之间的区域的光刻胶进行半曝光处理，对栅极图形对应的过孔区域的光刻胶进行全曝光处理；通过曝光显影处理，去除过孔区域全部的光刻胶以及源极和漏极之间的区域被曝光厚度的光刻胶；通过刻蚀工艺去除过孔区域对应的全部栅极绝缘层，形成过孔图形；通过灰化工艺去除源极和漏极之间的区域剩余的光刻胶，再通过刻蚀工艺去除源极和漏极之间的区域设定厚度的栅极绝缘层，使源极和漏极之间的区域剩余的栅极绝缘层的厚度与现有技术中栅极绝缘层的厚度基本一致，剩余的栅极绝缘层的厚度约为步骤203中通过一次构图工艺形成过孔图形和源极和漏极之间的区域图形，现有技术中通过两次构图工艺分别形成过孔图形和源极和漏极之间的区域图形。
在形成过孔图形和源极和漏极之间的区域图形的基板上涂覆一层光刻胶，通过曝光和显影工艺去除源极和漏极之间的区域图形对应的光刻胶；再对源极和漏极之间的区域图形表面进行氢气等离子处理，然后通过一次构图工艺在源极和漏极之间的区域图形上分别沉积一层A-Si:H，一层N+Si:H；形成有源层。有源层中N+Si:H为半导体材料，可以产生电子，当电流通过时，降低源极和漏极的能量势垒。
步骤204中在有源层上形成源极、漏极、像素电极层，具体包括：通过一次构图工艺在形成有源层的基板上形成源极和漏极；并在过孔图形上也沉积一层源极和漏极材料；通过一次构图工艺采用湿法刻蚀去除沟道区域图形处沉积的源极和漏极材料，再通过干法刻蚀去除沟道区域图形沉积的N+Si:H。形成源极和漏极的材料包括但不限于：Mo，或Mo/Al/Mo等。在形成源极和漏极的基板上形成第一氧化铟锡ITO层，作为像素电极，形成像素电极图形，与漏极搭接。
步骤205中在源极、漏极、像素电极层上分别形成钝化层和狭缝状公共电极层，具体包括：在形成第一ITO层的基板上沉积钝化层，通过一次构图工艺形成钝化层过孔；在形成钝化层的基板上沉积第二ITO层，并通过一次构图工艺将第二ITO层刻蚀形成条状结构，形成狭缝状公共电极图形；将信号通过第二ITO层以及钝化层的过孔导入源极和漏极，以及栅极。
如图3所示，为本发明实施例中一种栅极图形位于靠近衬底基板一侧的阵列基板的具体制作方法，该方法包括：
步骤301：在衬底基板上通过一次构图工艺形成栅极图形；如图4所示为形成栅极图形的基板的示意图，其中401为衬底基板，402为栅极图形；
步骤302：在形成栅极图形的基板上沉积一层厚度为的SiNx，形成栅极绝缘层；如图5所示，为沉积栅极绝缘层后的基板的示意图，其中501为栅极绝缘层；
步骤303：在栅极绝缘层上涂覆一层光刻胶，对栅极图形对应的源极与漏极之间的区域的光刻胶通过半透膜或光栅进行半曝光处理，对栅极图形对应的过孔区域的光刻胶进行全曝光处理；如图6所示，为涂覆光刻胶并进行曝光处理的基板的示意图，其中601为光刻胶层，602为半曝光处理的源极与漏极之间的区域的光刻胶，603为全曝光处理的过孔区域的光刻胶；
步骤304：通过曝光显影处理，去除过孔区域全部的光刻胶以及源极与漏极之间的区域被曝光厚度的光刻胶；如图7所示，为去除曝光后的光刻胶的基板的示意图；
步骤305：通过刻蚀工艺去除过孔区域对应的全部栅极绝缘层，形成过孔图形；如图8所示，为本发明实施例中形成过孔图形的基板的示意图，其中801为过孔图形；
步骤306：通过灰化工艺去除源极与漏极之间的区域剩余的光刻胶；如图9所示，为灰化工艺处理后的基板的示意图；
步骤307：通过刻蚀工艺去除源极与漏极之间的区域设定厚度的栅极绝缘层，剩余的栅极绝缘层的厚度约为如图10所示，为去除源极与漏极之间的区域设定厚度的栅极绝缘层的基板的示意图，其中1001为源极与漏极之间的区域图形；
步骤308：通过一次构图工艺在栅极图形对应的源极与漏极之间的区域图形上分别沉积一层A-Si:H，和一层N+Si:H；形成有源层；如图11所示，为形成有源层后的基板的示意图，其中1101为有源层中的A-Si:H层，1102为有源层中的N+Si:H层；
步骤309：通过一次构图工艺在形成有源层图形和过孔图形的基板上形成源极和漏极图形；如图12所示，为形成有源极和漏极的基板的示意图，其中1201为漏极，1202为源极；
步骤310：通过一次构图工艺在形成源极和漏极的基板上形成第一氧化铟锡ITO层，形成像素电极图形；如图13所示，为形成像素电极图形的基板的示意图，其中1301为第一ITO层；
步骤311：在形成像素电极图形的基板上沉积钝化层，沉积的钝化层的厚度为如图14所示，为沉积钝化层的基板的示意图，其中1401为钝化层；
步骤312：通过一次构图工艺在形成的钝化层上形成过孔，使信号通过过孔传输至源极和漏极，以及栅极；
步骤313：在形成钝化层的基板上沉积第二ITO层，并通过一次构图工艺将第二ITO层刻蚀形成条状结构，形成狭缝状公共电极图形，形成阵列基板；如图15所示，为形成的阵列基板的示意图，其中1501为第二ITO层；如图16所示，为形成的阵列基板的钝化层后过孔处的剖面图，其中1501为第二ITO层，1601为钝化层过孔。
实施例二、如图17所示，为本发明实施例中栅极图形位于远离衬底基板一侧的阵列基板的制作方法，该方法包括：
步骤1701：在衬底基板上形成有源层；
步骤1702：在有源层上形成源极、漏极和像素电极层；
步骤1703：在源极、漏极和像素电极层上方形成栅极绝缘层；
步骤1704：在栅极绝缘层上方形成栅极图形；
步骤1705：在栅极图形上方分别形成钝化层、狭缝状公共电极层。
其中，步骤1701中在衬底基板上形成有源层，具体包括：通过一次构图工艺在衬底基板上分别沉积一层A-Si:H，一层N+Si:H；形成有源层。有源层中N+Si:H为半导体材料，可以产生电子，当电流通过时，降低源极和漏极的能量势垒。
步骤1702中在有源层上形成源极、漏极和像素电极层，具体包括：通过一次构图工艺在形成有源层的基板上形成源极和漏极；并在过孔图形对应的位置上也沉积一层源极和漏极材料；通过一次构图工艺采用湿法刻蚀去除源极和漏极之间区域图形处沉积的源极和漏极材料，再通过干法刻蚀去除源极和漏极之间区域图形沉积的N+Si:H。形成源极和漏极的材料包括但不限于：Mo，或Mo/Al/Mo等。在形成源极和漏极的基板上形成第一氧化铟锡ITO层，作为像素电极，形成像素电极图形，与漏极搭接。
步骤1703中在源极、漏极和像素电极层上方形成栅极绝缘层，具体包括：在形成源极和漏极图形以及有源层图形的基板上形成的栅极绝缘层的厚度约为现有技术中栅极绝缘层厚度的2倍，约
在栅极绝缘层上涂覆一层光刻胶，并通过曝光显影工艺对源极和漏极之间的区域的光刻胶进行半曝光处理，对过孔区域位置的光刻胶进行全曝光处理；通过曝光显影处理，去除过孔区域位置全部的光刻胶以及源极和漏极之间的区域被曝光厚度的光刻胶；通过刻蚀工艺去除过孔区域位置对应的全部栅极绝缘层，形成过孔图形；通过灰化工艺去源极和漏极之间的区域剩余的光刻胶，再通过刻蚀工艺去除源极和漏极之间的区域设定厚度的栅极绝缘层，使源极和漏极之间的区域剩余的栅极绝缘层的厚度与现有技术中栅极绝缘层的厚度基本一致，剩余的栅极绝缘层的厚度约为
步骤1704中在栅极绝缘层上方形成栅极图形，具体包括：在形成栅极绝缘层的基板上形成栅极图形，其中源极和漏极与栅极图形之间的栅极绝缘层的厚度约为有源层与栅极图形之间的栅极绝缘层的厚度为3000
步骤1705中在栅极图形上方分别形成钝化层、狭缝状公共电极层，具体包括：在形成栅极图形的基板上沉积钝化层，通过一次构图工艺形成钝化层过孔；在形成钝化层的基板上沉积第二ITO层，并通过一次构图工艺将第二ITO层刻蚀形成条状结构，形成狭缝状公共电极图形；将信号通过第二ITO层以及钝化层的过孔导入源极和漏极，以及栅极。
如图18所示，为本发明实施例中栅极图形位于远离衬底基板一侧的阵列基板的具体制作方法，该方法包括：
步骤1801：在衬底基板上通过一次构图工艺形成有源层；如图19所示为形成有源层的基板的示意图，其中1901为衬底基板，1902为有源层图形；
步骤1802：通过一次构图工艺在形成有源层的基板上形成源极和漏极，并在过孔图形对应的位置处也沉积一层源极和漏极材料；如图20所示，为沉积源极和漏极后的基板的示意图，其中2001为漏极，2002为源极；
步骤1803：通过一次构图工艺在形成源极和漏极的基板上形成第一氧化铟锡ITO层，形成像素电极图形；如图21所示，为形成像素电极图形的基板的示意图，其中2101为第一ITO层；
步骤1804：在源极、漏极和像素电极层上沉积一层厚度为的SiNx，形成栅极绝缘层；如图22所示，为沉积栅极绝缘层后的基板的示意图，其中2201为栅极绝缘层；
步骤1805：通过一次构图工艺形成过孔图形，并去除源极和漏极之间区域的设定厚度栅极绝缘层，剩余的栅极绝缘层的厚度约为如图23所示，为形成过孔图形和去除源极和漏极之间区域的设定厚度栅极绝缘层的基板的示意图，其中2301为源极与漏极之间的区域图形，2302为过孔图形；
步骤1806：通过一次构图工艺在栅极绝缘层上形成栅极图形；如图24所示为形成栅极图形的基板的示意图，其中2401为栅极图形；
步骤1807：在形成栅极图形的基板上沉积钝化层，沉积的钝化层的厚度为如图25所示，为沉积钝化层的基板的示意图，其中2501为钝化层；
步骤1808：通过一次构图工艺在形成的钝化层上形成过孔，使信号通过过孔传输至源极和漏极，以及栅极；
步骤1809：在形成钝化层的基板上沉积第二ITO层，并通过一次构图工艺将第二ITO层刻蚀形成条状结构，形成狭缝状公共电极图形，形成阵列基板；如图26所示，为形成的阵列基板的示意图，其中2601为第二ITO层。
如图27所示，为本发明实施例中当阵列基板的源极和漏极之间的区域处于开态时像素单元电路结构示意图，该阵列基板中源极与栅极形成电容Cgs，漏极与栅极形成电容Cgd，有源层与栅极形成电容Cga；当阵列基板的源极和漏极之间的区域处于开态时，电流通过源极，经过源极和漏极之间的区域形成沟道，再经过漏极传输至像素电极，控制像素电极打开或关闭；有源层与栅极形成的电容Cga位于源极和漏极之间的区域，用于接收到电流后形成沟道，因此电容不能过小，否则通过的电流较小，容易导致像素单元中激发的色彩暗淡，形成显示不良；而源极和漏极分别与栅极形成的电容，在电流的传输过程中，会阻碍电流的传输，电流通过这两个电容时，需要较大的电压强度才能突破这两个电容的能量势垒，导致大量的电能装化为了热能或其他能量，造成了能量损耗；因此源极和漏极分别与栅极形成的电容需要较小的电容。根据现有技术可知，当源极和漏极与栅极之间的绝缘介质层的厚度越厚时，源极和漏极分别与栅极形成的电容也就越小，损耗的电能也就越小，因此本发明实施例中源极和漏极与栅极之间的绝缘层厚度为普通绝缘层厚度的2倍，大大降低了能量的损耗。有源层与栅极之间的栅极绝缘层的厚度较小，形成的电容Cga大小不变；即保证了Cga电容的大小，又降低了Cgs和Cgd的电容。根据式1-1可以看出，当所需电压强度降低，电流强度就随之下降，因此阵列基板的能耗也就降低了。
Ids＝Ion＝μeff(εins0/tins)(W/L)(Vgs-Vth)Vds       (1-1)
其中，Ids为源极漏极电流，Ion为沟道的开态电流，μeff为等效载流子迁移率，εins为栅极绝缘层的介电常数，ε0为真空介电常数，tins源极和漏极之间的区域的栅极绝缘层的厚度，εinsε0/tins为单位面积的栅极绝缘层的电容值；W为源极和漏极之间的区域宽度，L为源极和漏极之间的区域长度；Vgs为栅极/源极电压，Vds为栅极/漏极电压，Vth为阈值电压。由于单位面积的电容降低，栅极/源极电压和栅极/漏极电压不变，保证了在降低功耗的同时，Ion维持现有水平。
如图28所示，为本发明实施例中当阵列基板的源极和漏极之间的区域处于关态时像素单元电路结构示意图，源极与栅极形成电容Cgs，漏极与栅极形成电容Cgd；其中Gate line为栅极线，data line为数据线，由于电容Cgd和电容Cgs减小，消耗的电量降低，降低了阵列基板的能耗。
基于同一发明构思，本发明实施例还提供了一种阵列基板，由于该阵列基板的解决问题的原理与本发明实施例一种阵列基板的制作方法相似，因此该阵列基板的实施可以参见方法的实施，重复之处不再赘述。
本发明实施例提供了一种阵列基板，该阵列基板包括：栅极绝缘层；覆盖在栅极绝缘层一侧的有源层，源极和漏极；覆盖在栅极绝缘层另一侧的栅极图形；其中，源极和漏极与栅极图形之间的栅极绝缘层的厚度大于有源层与栅极图形之间的栅极绝缘层的厚度。
如图29所示，为本发明实施例中栅极图形位于靠近衬底基板一侧的阵列基板，该阵列基板包括：衬底基板2901，形成于衬底基板2901上的栅极2902；形成于栅极以及未被栅极覆盖的沉积基板上的栅极绝缘层2903；形成于栅极图形上的有源层2904；形成于有源层上的源极和漏极2905，以及像素电极2907；其中有源层与栅极图形之间的栅极绝缘层的厚度为源极和漏极与栅极图形之间的栅极绝缘层的厚度为形成于栅极绝缘层上与栅极图形连接的过孔图形2906，且过孔图形上覆盖有形成源极和漏极材料；形成于栅极绝缘层上的第一ITO层2907，第一ITO层与漏极搭接；覆盖在源极和漏极，第一ITO层，以及过孔图形上的钝化层2908，钝化层的厚度约为形成于在钝化层上的过孔（图中未示出）；形成于钝化层上的第二ITO层2909，信号通过第二ITO层以及钝化层的过孔导入源极和漏极，以及栅极。
如图30所示，为本发明实施例中栅极图形位于远离衬底基板一侧的阵列基板，该阵列基板包括：衬底基板3001，形成于衬底基板上的有源层3002；形成于有源层上的源极和漏极3003，以及像素电极层3004，像素电极层与漏极搭接；形成于沉积衬底基板上的源极和漏极图形3005；覆盖在源极、漏极和像素电极层上方，以及未被有源层覆盖的衬底基板上方的栅极绝缘层3006；形成于栅极绝缘层上方的栅极图形3007；其中栅极图形3007通过过孔图形与衬底基板上的源极和漏极图形3005连接；有源层与栅极图形之间的栅极绝缘层的厚度为源极和漏极与栅极图形之间的栅极绝缘层的厚度为覆盖在栅极绝缘层3006和栅极图形3007上的钝化层3008，钝化层的厚度约为形成于在钝化层上的过孔（图中未示出）；形成于钝化层上的第二ITO层3009，信号通过第二ITO层以及钝化层的过孔导入源极和漏极，以及栅极。
本发明实施例中的阵列基板中源极与栅极形成电容Cgs，漏极与栅极形成电容Cgd，有源层与栅极形成电容Cga；当阵列基板的源极和漏极之间的区域处于开态时，电流通过源极，经过源极和漏极之间的区域形成沟道，再经过漏极传输至像素电极，控制像素电极打开或关闭；有源层与栅极形成的电容Cga位于源极和漏极之间的区域，用于接收到电流后形成沟道，因此电容不能过小，否则通过的电流较小，容易导致像素单元中激发的色彩暗淡，形成显示不良；而源极和漏极分别与栅极形成的电容，在电流的传输过程中，会阻碍电流的传输，电流通过这两个电容时，需要较大的电压强度才能突破这两个电容的能量势垒，导致大量的电能装化为了热能或其他能量，造成了能量损耗；因此源极和漏极分别与栅极形成的电容需要较小的电容。根据现有技术可知，当源极和漏极与栅极之间的绝缘介质层的厚度越厚时，源极和漏极分别与栅极形成的电容也就越小，损耗的电能也就越小，因此本发明实施例中源极和漏极与栅极之间的绝缘层厚度为普通绝缘层厚度的2倍，大大降低了能量的损耗。有源层与栅极之间的栅极绝缘层的厚度较小，形成的电容Cga大小不变；即保证了Cga电容的大小，又降低了Cgs和Cgd的电容。
当阵列基板的源极和漏极之间的区域处于关态时，源极与栅极形成电容Cgs，漏极与栅极形成电容Cgd；由于电容Cgd和电容Cgs减小，消耗的电量降低，降低了阵列基板的能耗。
本发明实施例还提供了一种显示装置，该显示装置包括本发明实施例中任意一种阵列基板。
本领域内的技术人员应明白，尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

1.一种阵列基板的制作方法，其特征在于，该方法包括：
采用一次构图工艺对源极和漏极之间区域的栅极绝缘层进行部分刻蚀处理；
通过一次构图工艺形成有源层，所述有源层覆盖所述栅极绝缘层部分刻蚀区域；
通过一次构图工艺形成栅极图形，所述栅极图形覆盖栅极绝缘层部分刻蚀区域，及源极和漏极对应的栅极绝缘层区域；
其中，所述栅极图形和所述有源层位于栅极绝缘层不同侧，且所述源极和漏极与所述栅极图形之间的栅极绝缘层的厚度大于所述源极和漏极之间有源层与所述栅极图形之间的栅极绝缘层的厚度。
2.如权利要求1所述的方法，其特征在于，采用一次构图工艺对源极和漏极之间区域的栅绝缘层部分刻蚀，具体包括：
通过半曝光工艺对源极和漏极之间区域的栅绝缘层进行部分刻蚀处理，对栅极绝缘层的过孔区域进行全曝光处理，形成栅绝缘层过孔。
3.如权利要求1所述的方法，其特征在于，当所述栅极图形位于靠近衬底基板一侧时，所述方法包括：
在衬底基板上形成栅极图形；
在形成栅极图形的基板上形成栅极绝缘层；
在栅绝缘层上形成有源层；
在有源层上形成源极、漏极、像素电极层；
在源极、漏极、像素电极层上分别形成钝化层和狭缝状公共电极层，所述像素电极与漏极电连接。
4.如权利要求1所述的方法，其特征在于，当所述栅极图形位于远离衬底基板一侧时，所述方法包括：
在衬底基板上形成有源层；
在有源层上形成源极、漏极和像素电极层；
在源极、漏极和像素电极层上方形成栅极绝缘层；
在栅极绝缘层上方形成栅极图形；
在栅极图形上方分别形成钝化层、狭缝状公共电极层。
5.如权利要求1～4任一所述的方法，其特征在于，所述栅极绝缘层除源极和漏极之间区域，其他区域的厚度为
6.如权利要求5所述的方法，其特征在于，所述栅极绝缘层的源极和漏极之间区域的厚度为
7.一种阵列基板，其特征在于，该阵列基板包括：
栅极绝缘层；
覆盖在所述栅极绝缘层一侧的有源层，源极和漏极；
覆盖在所述栅极绝缘层另一侧的栅极图形；
其中所述源极和漏极与所述栅极图形之间的栅极绝缘层的厚度大于所述源极和漏极之间有源层与所述栅极图形之间的栅极绝缘层的厚度。
8.如权利要求7所述的阵列基板，其特征在于，当所述栅极图形位于靠近衬底基板一侧时，所述阵列基板还包括：
形成于衬底基板上的栅极图形；
形成于栅极图形以及衬底基板上的栅极绝缘层；
形成于栅极绝缘层上的有源层；
形成于有源层上的源极、漏极、像素电极层；
形成于源极、漏极、像素电极层上的钝化层和狭缝状公共电极层，所述像素电极与漏极电连接。
9.如权利要求7所述的阵列基板，其特征在于，当所述栅极图形位于远离衬底基板一侧时，所述阵列基板还包括：
形成于衬底基板上的有源层；
形成于有源层上的源极、漏极和像素电极层；
形成于源极、漏极和像素电极层上方的栅极绝缘层；
形成于栅极绝缘层上方的栅极图形；
形成于栅极图形上方的钝化层、狭缝状公共电极层。
10.如权利要求7～9任一所述的阵列基板，其特征在于，所述阵列基板上栅极绝缘层除源极和漏极之间区域，其他区域的厚度为
11.如权利要求10所述的阵列基板，其特征在于，所述阵列基板中栅极绝缘层的源极和漏极之间区域的厚度为
12.一种显示装置，其特征在于，该显示装置含有权利要求7～11任一一种阵列基板。
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