CN105655408A - 薄膜晶体管、阵列基板及其制作和驱动方法、显示装置 - Google Patents

薄膜晶体管、阵列基板及其制作和驱动方法、显示装置 Download PDF

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CN105655408A
CN105655408A CN201610144790.XA CN201610144790A CN105655408A CN 105655408 A CN105655408 A CN 105655408A CN 201610144790 A CN201610144790 A CN 201610144790A CN 105655408 A CN105655408 A CN 105655408A
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grid
active layer
layer
thin film
film transistor
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张淼
孙静
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to CN201610144790.XA priority Critical patent/CN105655408A/zh
Priority to US15/531,111 priority patent/US20180151749A1/en
Priority to PCT/CN2016/083905 priority patent/WO2017156885A1/zh
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Abstract

本发明提供了一种薄膜晶体管、阵列基板及其制作和驱动方法、显示装置，该薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。本发明提供的氧化物薄膜晶体管，其栅极包括位于有源层下方的第一栅极以及位于有源层上方的第二栅极，通过对第一栅极和第二栅极交替进行控制，能够抑制氧化物薄膜晶体管的Vth电学特性漂移，提高氧化物薄膜晶体管开关特性的稳定性。

Description

薄膜晶体管、阵列基板及其制作和驱动方法、显示装置
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管、阵列基板及其制作和驱动方法、显示装置。
背景技术
随着液晶显示器技术的更新，高迁移率的氧化物TFT(ThinFilmTransistor,薄膜晶体管)等技术不断得到应用，成为发展的一个新方向。非晶硅薄晶体管的迁移率一般在0.5cm2/Vs左右，当LCD分辨率与驱动频率较高时，现有非晶硅的迁移率已很难满足要求，低温多晶硅虽然迁移率较高，但与现有的非晶硅产线不兼容，而氧化物TFT迁移率高，且制作工艺与现有产线兼容性好，可以更好地满足日益增长的显示需求。
然而，在显示面板工作时，由于其中的氧化物TFT的栅极持续被施加高低电平信号，导致内部电子吸引或排斥，进而容易造成薄膜晶体管的Vth(阈值电压)漂移，而Vth的漂移可能会导致众多的显示不良。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是：如何解决在显示面板工作时，由于其中氧化物TFT的栅极持续被施加高低电平信号从而容易造成Vth(阈值电压)漂移的问题。
(二)技术方案
为解决上述技术问题，本发明的技术方案提供了一种薄膜晶体管，包括有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
优选地，所述第一栅极设置在所述有源层的正下方，所述第二栅极设置在所述有源层的正上方。
优选地，所述有源层的材料包括铟镓锌氧化物。
为解决上述技术问题，本发明还提供了一种阵列基板，包括上述的薄膜晶体管。
优选地，所述阵列基板还包括：
与所述第一栅极电连接的第一栅线、与所述第二栅极电连接的第二栅线；
将所述第一栅极与所述有源层绝缘的栅绝缘层；
将所述有源层与所述第二栅极绝缘的钝化层；
设置在所述钝化层上方用作公共电极层或像素电极层的透明导电层。
优选地，所述第二栅极与所述透明导电层为相同材料且同层设置。
优选地，所述第一栅极、所述第一栅线、所述第二栅线为相同材料且同层设置。
为解决上述技术问题，本发明还提供了一种显示装置，包括上述的阵列基板。
为解决上述技术问题，本发明还提供了一种阵列基板的制作方法，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，形成所述栅极包括：
形成位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
优选地，还包括：
形成与所述第一栅极电连接的第一栅线以及与所述第二栅极电连接的第二栅线；
形成将所述第一栅极与所述有源层绝缘的栅绝缘层；
形成将所述有源层与所述第二栅极绝缘的钝化层；
在所述钝化层上方形成用作公共电极层或像素电极层的透明导电层。
优选地，所述第二栅极与所述透明导电层在一次构图工艺中同时形成。
优选地，所述第一栅极、所述第一栅线、所述第二栅线在一次构图工艺中同时形成。
为解决上述技术问题，本发明还提供了一种阵列基板的驱动方法，用于驱动上述的阵列基板，所述驱动方法包括：
在显示第n帧图像时向所述薄膜晶体管的第一栅极施加栅信号，第二栅极悬空，n为非零的自然数；
在显示第n+1帧图像时向所述薄膜晶体管的第二栅极施加栅信号，第一栅极悬空。
(三)有益效果
本发明提供的氧化物薄膜晶体管，其栅极包括位于有源层下方的第一栅极以及位于有源层上方的第二栅极，通过对第一栅极和第二栅极交替进行控制，能够抑制氧化物薄膜晶体管的Vth电学特性漂移，提高氧化物薄膜晶体管开关特性的稳定性。
附图说明
图1是本发明实施方式提供的一种薄膜晶体管的示意图；
图2是本发明实施方式提供的一种阵列基板的示意图；
图3～8是本发明实施方式提供的一种制作阵列基板的示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
本发明实施方式提供了一种薄膜晶体管，该薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
本发明实施方式提供的氧化物薄膜晶体管，其栅极包括位于有源层下方的第一栅极以及位于有源层上方的第二栅极，通过对第一栅极和第二栅极交替进行控制，能够抑制氧化物薄膜晶体管的Vth电学特性漂移，提高氧化物薄膜晶体管开关特性的稳定性。
参见图1，图1是本发明实施方式提供的一种薄膜晶体管的示意图，该薄膜晶体管包括设置在衬底基板100上的第一栅极110、由氧化物半导体材料形成的有源层130、源极151、漏极152和第二栅极170，源极151和漏极152通过刻蚀阻挡层140上的过孔与有源层130接触；
其中，第一栅极110设置在有源层130的正下方，第一栅极110与有源层130之间设置有将两者绝缘的栅绝缘层120，第二栅极170设置在有源层130的正上方，第二栅极170与第一栅极110呈上下对称设置，有源层130与第二栅极170之间设置有将两者绝缘的钝化层160；
例如，有源层130的材料可以包括铟镓锌氧化物(IGZO)。
此外，本发明实施方式还提供了一种阵列基板，包括薄膜晶体管，该薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
例如，上述阵列基板可以为显示模式为水平电场模式的显示面板(如ADS模式、IPS模式或FFS模式的显示面板)的阵列基板，除上述的薄膜晶体管外，其还包括与薄膜晶体管的第一栅极电连接的第一栅线、与薄膜晶体管的第二栅极电连接的第二栅线、将所述第一栅极与所述有源层绝缘的栅绝缘层、将所述有源层与所述第二栅极绝缘的钝化层、设置在所述钝化层上方用作公共电极层或像素电极层的透明导电层；
优选地，为减少阵列基板的构图工艺次数，所述第二栅极与所述透明导电层为相同材料且同层设置。
优选地，为减少阵列基板的构图工艺次数，所述第一栅极、所述第一栅线、所述第二栅线为相同材料且同层设置。
参见图2，图2是本发明实施方式提供的一种阵列基板的示意图，该阵列基板包括衬底基板100，衬底基板100上设置有薄膜晶体管，该薄膜晶体管包括第一栅极110、由氧化物半导体材料形成的有源层130、源极151、漏极152和第二栅极170；
其中，源极151和漏极152通过刻蚀阻挡层140上的过孔与有源层130接触，第一栅极110设置在有源层130的正下方，第一栅极110与有源层130之间设置有将两者绝缘的栅绝缘层120，第二栅极170设置在有源层130的正上方，有源层130与第二栅极170之间设置有将两者绝缘的钝化层160；
此外，该阵列基板还包括与第一栅极110电连接的第一栅线、与第二栅极170电连接的第二栅线111、由透明导电材料(如ITO)形成的公共电极层112、由透明导电材料形成的像素电极层171；
其中，公共电极层112、第一栅极110、第一栅线、第二栅线111设置在栅绝缘层120的下方，像素电极层171、第二栅极170设置在钝化层160的上方，第二栅极170通过栅绝缘层120、刻蚀阻挡层140、钝化层160上的过孔与第二栅线111电连接；
此外，公共电极层112、第一栅极110、第一栅线、第二栅线111的材料可以均为透明导电材料，在制作时，公共电极层112、第一栅极110、第一栅线、第二栅线111可以在一次构图工艺中同时形成；
此外，像素电极层171、第二栅极170的材料也可以均为透明导电材料，在制作时，像素电极层171、第二栅极170可以在一次构图工艺中同时形成。
本发明实施方式还提供了一种显示装置，包括上述的阵列基板。其中，本发明实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本发明实施方式还提供了一种阵列基板的制作方法，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，形成所述栅极包括：
形成位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
例如，上述阵列基板可以为显示模式为水平电场模式的显示面板(如ADS模式、HADS模式、IPS模式或FFS模式的显示面板)的阵列基板，除制作上述的薄膜晶体管外，阵列基板的制作方法还包括：
形成与所述第一栅极电连接的第一栅线以及与所述第二栅极电连接的第二栅线；
形成将所述第一栅极与所述有源层绝缘的栅绝缘层；
形成将所述有源层与所述第二栅极绝缘的钝化层；
在所述钝化层上方形成用作公共电极层或像素电极层的透明导电层。
例如，上述的阵列基板的制作方法可以包括：
S1：制作公共电极层，例如，在衬底基板(玻璃基板)上溅射ITO薄膜，然后涂覆光刻胶，使用制作公共电极层的掩膜版(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，形成公共电极层的图案；
S2：制作第一栅极、第一栅线、第二栅线，例如，可以使第一栅极、第一栅线、第二栅线在一次构图工艺中同时形成，具体地，首先进行金属溅射工艺，然后涂覆光刻胶，并使用制作栅层的掩膜版(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，形成包括第一栅极、第一栅线和第二栅线的图案，其结构如图3所示，公共电极层112、第一栅极110、第一栅线、第二栅线111设置在衬底基板100上；
S3：制作栅绝缘层(GateInsulator)，例如，可以通过CVD方式沉积SiO2或SiONx，从而如图4所示形成栅绝缘层120；
S4：制作有源层(Activelayer)，例如，可以采用IGZO或其他氧化物半导体材料通过溅射方式形成氧化物半导体膜层，然后涂覆光刻胶，使用制作有源层的掩膜版(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，从而如图5所示形成有源层130的图案；
S5：制作刻蚀阻挡层(EtchStopLayer，ESL)，例如，可以通过CVD方式沉积SiO2，然后涂覆光刻胶，使用制作刻蚀阻挡层的掩膜版(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，从而如图6所示形成刻蚀阻挡层140的图案；
S6：制作源漏层(SD层)的图案，例如，通过溅射法沉积金属薄膜，然后涂覆光刻胶，使用制作源漏层的掩膜版(mask)对光刻胶进行曝光，在经过显影工艺和湿蚀工艺后剥离剩余的光刻胶，从而如图7所示，形成包括源极151、漏极152及数据线(Data线)的图案；
S7：制作钝化层(PVX层)，例如，通过CVD方式沉积SiO2或SiONx，然后涂覆光刻胶，使用钝化层的掩膜版(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，从而在栅绝缘层120、刻蚀阻挡层140、钝化层160上形成过孔，包括用于使后续制作的像素电极层与薄膜晶体管的漏极152连接的过孔以及用于使后续制作的第二栅极170与第二栅线111连接的过孔；
S8：制作像素电极层和第二栅极，例如，可以使第二栅极与像素电极层在一次构图工艺中同时形成，例如，首先通过溅射工艺形成一层透明导电薄膜，然后经过涂胶、曝光、显影、刻蚀和剥离工艺形成导电图案，包括狭缝(slit)型的像素电极层(PXL电极)以及第二栅极，并通过步骤S7中所形成的过孔，第二栅极与第二栅线电连接，像素电极层与漏极电连接，从而得到如图2所示的阵列基板。
优选地，公共电极层、第一栅极、第一栅线、第二栅线可以通过同一个HTMmask形成图案，从而使公共电极层、第一栅极、第一栅线、第二栅线在一次构图工艺中同时形成，从而减少构图工艺次数。
本发明实施方式提供的阵列基板的制作方法，能够有效抑制氧化物薄膜晶体管的Vth的漂移，并且在工艺上不增加新的掩膜(mask)，有效减少不良发生，提高产品良率。
此外，本发明实施方式还提供了一种阵列基板的驱动方法，用于上述的阵列基板，所述驱动方法包括：
在显示第n帧图像时向所述薄膜晶体管的第一栅极施加栅信号，第二栅极悬空，n为非零的自然数；
在显示第n+1帧图像时向所述薄膜晶体管的第二栅极施加栅信号，第一栅极悬空。
例如，在显示屏工作时，奇数帧时向第一栅线施加VGH/VGL信号，第二栅线悬空(floating)；偶数帧时向第二栅线施加VGH/VGL信号，第一栅线悬空(floating)；由于阵列基板的TFT为上下对称双栅极设计，且两个栅极位置相反，TFT的Vth漂移受到抑制，从而保证了TFT电学特性的稳定。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (13)

1.一种薄膜晶体管，包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其特征在于，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述第一栅极设置在所述有源层的正下方，所述第二栅极设置在所述有源层的正上方。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述氧化物半导体材料包括铟镓锌氧化物。
4.一种阵列基板，其特征在于，包括权利要求1-3任一所述的薄膜晶体管。
5.根据权利要求4所述的阵列基板，其特征在于，所述阵列基板还包括：
与所述第一栅极电连接的第一栅线、与所述第二栅极电连接的第二栅线；
将所述第一栅极与所述有源层绝缘的栅绝缘层；
将所述有源层与所述第二栅极绝缘的钝化层；
设置在所述钝化层上方用作公共电极层或像素电极层的透明导电层。
6.根据权利要求5所述的阵列基板，其特征在于，所述第二栅极与所述透明导电层为相同材料且同层设置。
7.根据权利要求5所述的阵列基板，其特征在于，所述第一栅极、所述第一栅线、所述第二栅线为相同材料且同层设置。
8.一种显示装置，其特征在于，包括权利要求4-7任一所述的阵列基板。
9.一种阵列基板的制作方法，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其特征在于，形成所述栅极包括：
形成位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
10.根据权利要求9所述的阵列基板的制作方法，其特征在于，还包括：
形成与所述第一栅极电连接的第一栅线以及与所述第二栅极电连接的第二栅线；
形成将所述第一栅极与所述有源层绝缘的栅绝缘层；
形成将所述有源层与所述第二栅极绝缘的钝化层；
在所述钝化层上方形成用作公共电极层或像素电极层的透明导电层。
11.根据权利要求10所述的阵列基板的制作方法，其特征在于，所述第二栅极与所述透明导电层在一次构图工艺中同时形成。
12.根据权利要求10所述的阵列基板的制作方法，其特征在于，所述第一栅极、所述第一栅线、所述第二栅线在一次构图工艺中同时形成。
13.一种阵列基板的驱动方法，其特征在于，用于驱动权利要求4-7任一所述的阵列基板，所述驱动方法包括：
在显示第n帧图像时向所述薄膜晶体管的第一栅极施加栅信号，第二栅极悬空，n为非零的自然数；
在显示第n+1帧图像时向所述薄膜晶体管的第二栅极施加栅信号，第一栅极悬空。
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