WO2010134511A1 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- WO2010134511A1 WO2010134511A1 PCT/JP2010/058331 JP2010058331W WO2010134511A1 WO 2010134511 A1 WO2010134511 A1 WO 2010134511A1 JP 2010058331 W JP2010058331 W JP 2010058331W WO 2010134511 A1 WO2010134511 A1 WO 2010134511A1
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Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof.
- the present invention relates to a semiconductor device in which a semiconductor element is built in a wiring board and a manufacturing method thereof.
- Patent Documents 1 to 3 describe a semiconductor element built-in substrate that incorporates a conventional semiconductor element.
- FIG. 19 is a cross-sectional view of a semiconductor element built-in substrate described in Patent Document 1.
- the semiconductor element-embedded substrate (electronic device 1) of FIG. 19 wiring layers 10a to 10c and electrical insulating layers 9a to 9d are stacked on a core substrate 2, and vertical conduction vias 7a provided in the electrical insulating layers 9a to 9d.
- Component built-in layers 5A and 5B are provided.
- Patent Document 1 only describes an example in which a wiring layer and an electrical insulating layer are mainly provided on one side of the core substrate 2, but the wiring layer, the electrical insulating layer, and the electronic component built-in layer are provided on both surfaces of the core substrate 2. It may be formed.
- a semiconductor element (chip) 30 is mounted on one side of a core substrate 121 described in Patent Document 2, and resin layers (insulating layers) 26a and 26b and wiring layers 27a and 27b are provided on both sides of the core substrate 121.
- 2 is a cross-sectional view of a provided semiconductor device 110.
- a wiring layer 33 connected to the electrode pad 31 of the chip 30 is previously provided on the chip 30 by using a wafer level packaging technique, and the wiring layer 33 and the upper wiring layer are formed by vias VH1. It is described that the wiring can be drawn out without increasing the wiring layer by connecting 27a.
- Patent Document 2 as a method of manufacturing the semiconductor device 110, the resin layers 26a and 26b are formed on both surfaces of the core substrate 121, the resin layers are formed on both surfaces, and the via holes VH1 and VH2 are formed on both surfaces. Then, a seed layer is formed by electroless Cu plating on the entire surface of each resin layer 26a, 26b including the inside of the via holes VH1, VH2, and after forming a register pattern thereon, the via holes VH1, VH2 are made conductive by electroplating. The front and back wiring layers 27a and 27b are formed at the same time.
- JP 2005-108937 A Japanese Patent Laid-Open No. 2005-311240 JP 2004-179288 A
- Patent Documents 1 to 3 are incorporated herein by reference. The following analysis is given by the present invention.
- a semiconductor element is built in one side of the core substrate and an insulating layer and a wiring layer are stacked only on one side as described in the example of Patent Document 1, the following warpage occurs. That is, when the core substrate is on the lower side, the entire semiconductor device has a concave warp, and a convex warp occurs around the semiconductor element. Therefore, problems arise in mounting other components and mounting the semiconductor device on the motherboard.
- the pitch of the electrode terminals of the built-in semiconductor element is becoming increasingly narrow, and at least the wiring pitch and shape of the connection part and wiring layer directly connected to the semiconductor element must be reduced.
- An attempt to miniaturize the shape causes an increase in cost and a decrease in yield.
- An object of the present invention is to provide a semiconductor device that can be manufactured at a high yield while suppressing overall warpage in a semiconductor device having a semiconductor element built in a substrate, and a method for manufacturing the same.
- a semiconductor device includes a core substrate, an insulating layer and a wiring layer provided on at least one layer on a first surface of the core substrate and a second surface opposite to the first surface, A via provided between the insulating layers and the core substrate and connecting the wiring layers; a semiconductor element mounted on the first surface of the core substrate with an electrode terminal formation surface facing; and the first surface A wiring layer penetrating through an insulating layer provided on the semiconductor element and directly connecting the electrode terminal of the semiconductor element and the wiring layer provided on the first surface; and a wiring layer directly connected to the connection portion
- the minimum wiring pitch is smaller than the minimum wiring pitch of any wiring layer provided on the second surface.
- a core wiring is provided on the surface of the first surface and the surface of the second surface opposite to the first surface, and further, the first surface and the first surface.
- the semiconductor device in which a semiconductor element is built in a substrate, it is possible to obtain a semiconductor device having a structure that can be manufactured at a high yield while suppressing overall warpage. Further, according to the method for manufacturing a semiconductor device of the present invention, the semiconductor device can be manufactured at a low cost and with a high yield.
- FIG. 6 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 1. It is sectional drawing of the semiconductor device by the modification 2 in each embodiment. It is sectional drawing of the semiconductor device by the modification 3 in each embodiment. It is sectional drawing of the semiconductor device by the modification 4 in each embodiment. It is sectional drawing of the semiconductor device by the modification 5 in each embodiment. It is sectional drawing of the semiconductor device by the modification 6 in each embodiment. It is sectional drawing of the semiconductor device by Embodiment 3 of this invention.
- FIG. 10 is a continuation of the process diagram according to Embodiment 4.
- FIG. 10 is a process diagram of a method for manufacturing a semiconductor device according to a modification of Embodiment 4.
- FIG. 10 is a continuation of the process diagram according to the modification of the fourth embodiment.
- FIG. 10 is a process diagram of a method for manufacturing a semiconductor device according to Embodiment 5.
- FIG. 10 is a continuation of the process diagram according to Embodiment 5.
- FIG. 10 is a process diagram of a method for manufacturing a semiconductor device according to Embodiment 6. It is sectional drawing of the conventional semiconductor device described in patent document 1.
- FIG. 10 is sectional drawing of the conventional semiconductor device described in patent document 2.
- the semiconductor element 14 mounted in a table, and the insulating layer 16 provided on the first surface, and the electrode terminal 14a of the semiconductor element 14 and the wiring layer 19a provided on the first surface are directly connected Part 15 and the minimum wiring pitch of the wiring layer 19a directly connected to the connecting part 15 is Any provided dihedral wiring layer (19c, 19d, 22) smaller than the minimum wiring pitch of the.
- the minimum wiring pitch is a distance from the center of
- the warp of the entire semiconductor device can be reduced by the effect of the insulating layer on the second surface (FIG. 10, (See FIG. 11).
- the insulating layer is also provided on the second surface opposite to the semiconductor element mounting surface, the warp of the entire semiconductor device can be reduced by the effect of the insulating layer on the second surface (FIG. 10, (See FIG. 11).
- BGA Bit Grid Array
- the minimum wiring pitch of the wiring layer 19a directly connected to the electrode terminal 14a is narrowed in accordance with the pitch of the electrode terminal 14a on the surface of the semiconductor element 14.
- the minimum wiring pitch of the wiring layer (19c, 19d, 22) on the second surface which is the surface opposite to the semiconductor element mounting surface, is made larger than this.
- each via 20 provided on the second surface is larger than the shape of the connection portion 15. That is, the connection portion 15 directly connected to the electrode terminal 14a of the semiconductor element 14 is formed into a small shape by fine processing, and the connection stability can be improved by forming each via on the second surface larger than this. At the same time, the semiconductor device 10 can be manufactured with a high yield.
- the top diameter, the bottom diameter, and the height of each via 20 provided on the second surface are larger than the top diameter, the bottom diameter, and the height of the connection portion 15, respectively. That is, the top diameter of each via 20 is larger than the top diameter of the connection portion 15, the bottom diameter of each via 20 is larger than the bottom diameter of the connection portion 15, and the height of each via 20 is the height of the connection portion 15. Higher than that. Further, the volume of each via 20 provided on the second surface is three times or more than the volume of one connection portion 15.
- the thickness of the wiring layer 19a directly connected to the connecting portion 15 is thinner than the thickness of any wiring layer (19c, 19d, 22) provided on the second surface.
- the wiring layer 19a thin it is easy to form fine wiring, and the wiring layers (19c, 19d, 22) on the second surface that do not require fine wiring are formed thick.
- the impedance of the wiring resistance can be reduced.
- the thickness of each wiring layer (19c, 19d, 22) provided on the second surface the minimum It is desirable to increase the wiring width and the minimum wiring interval by 1.5 times or more because an effect for improving the yield of the semiconductor device can be obtained.
- the material of the insulating layer 16 around the connecting portion 15 is different from the material of the insulating layers (18-1, 18-2) not including the connecting portion 15.
- the insulating layer 16 around the connection portion 15 may be formed of a photosensitive resin, and the resin layer provided on the second surface may be formed of a non-photosensitive resin.
- the connection portion 15 can employ a photo via formed by photolithography, and a finer via can be formed than a laser via formed by laser processing, so that a narrow pitch connection with the semiconductor element 14 can be supported.
- the via provided in the insulating layer on the second surface can be realized by reducing the cost of the entire semiconductor device by selecting to use a laser that is lower in cost than the photo via by a combination of materials and processes.
- non-photosensitive resins do not have a photosensitive function, so they have excellent mechanical properties, rupture strength, elastic modulus, elongation at break, etc. as resin materials, and are resistant to external stress.
- the long-term reliability of the semiconductor device can be increased.
- it is preferable that the connection part 15 does not contain a solder material or a resin component. By doing so, connection with a narrow pitch and connection with high reliability are possible.
- at least one insulating layer 18-2 and two wiring layers 22 on the second surface are provided.
- Each of the insulating layer and the wiring layer on the first surface may be one layer.
- the number of insulating layers and wiring layers on the first surface can also be determined as necessary. That is, the insulating layer (16, 18-1) and the wiring layer (19a, 19b, 21) on the first surface may be two or more layers. In that case, a narrow-pitch, multi-pin semiconductor element can be incorporated.
- the power supply and ground layers can be strengthened, so that the characteristic impedance can be improved.
- External electrodes (21, 22) are provided on the outermost wiring layers (21, 22) of the first surface and the second surface, respectively.
- the electronic component 24 connected to the external electrodes (21, 22) is further included. If the electronic component 24 is mounted on the same first surface as the semiconductor element 14 as shown in FIG. 4, a high-speed signal can be transmitted between the semiconductor element 14 and the electronic component 24. On the other hand, if the electronic component 24 is mounted on the second surface that does not incorporate the semiconductor element 14 as shown in FIG. 5, it can be mounted on the highly rigid core substrate 11 only through the single insulating layer 18-2. Therefore, mounting accuracy is improved.
- a recess is formed in the first surface of the core substrate 11, and the semiconductor element 14 can be mounted in the recess. In this case, it is possible to reduce the thickness of the entire semiconductor device 10 by reducing the height of the semiconductor element 14. Furthermore, a plurality of semiconductor elements 14 may be mounted on the first surface of the core substrate 11 with the element formation surface as the front. In addition, as shown in FIGS. 6, 7, and 8, a reinforcing material is provided in at least one of the plurality of insulating layers. By providing the reinforcing goods, it is possible to effectively reduce the warpage of the entire semiconductor device 10 and the chip.
- the method for manufacturing a semiconductor device has a core wiring 12 on the surface of the first surface and the surface of the second surface opposite to the first surface.
- a core substrate 11 provided with a through via 13 for connecting the core wiring 12 between the first surface and the second surface is used (see FIG. 12A, etc.).
- a step of mounting the semiconductor element 14 with the electrode terminal 14a formation surface as a front surface (FIG. 12B), and a first insulating layer covering the semiconductor element 14 on the first surface are formed.
- a second wiring formation step for forming two wiring layers.
- the step of forming the first insulating layer 16 and the step of forming the first wiring (19a, 21 in FIG. 17) include the step of forming the second insulating layer 18-2 and the second wiring (19c, 19d, 22) Implemented in a separate process from the forming process.
- the via 20 and the wiring provided on the second surface have the processing accuracy required for the connection portion 15 directly connected to the electrode terminal 14a of the semiconductor element 14 and the wiring 19a directly connected to the connection portion 15.
- the step of forming the first insulating layer 16 and the step of forming the first wiring 19a include the step of forming the second insulating layer 18-2 and the step of forming the second wiring 22 Is performed in a separate process.
- a fine wiring can be formed using an additive method
- a wiring can be formed at a low cost using a subtractive method.
- a step of mounting the semiconductor element 14 is performed.
- the semiconductor element 14 is often the most expensive component. Therefore, by mounting the semiconductor element 14 in the order of steps in which the frequency of occurrence of defects is reduced as much as possible, This is to prevent the non-defective semiconductor element 14 from being wasted due to a defect other than the element 14. That is, when a defect occurs in the insulating layer forming process or the wiring layer forming process after the semiconductor element 14 is mounted on the core substrate 11, repair of these itself is performed, or the semiconductor element 14 is peeled off from the core substrate 11. This is because it is often difficult to stably carry out the repairing process for replacing the core substrate 11.
- a step of mounting the semiconductor element 14 can be performed after the step of forming the second wiring 19c. That is, by forming the insulating layer and the wiring layer on the second surface first and then mounting the semiconductor element 14 on the first surface, a non-defective semiconductor element 14 is wasted due to a defect other than the semiconductor element 14. Can be prevented. Further, as shown in FIG. 18, after the second wiring 19c formation step, the insulating layer 18-2 and the wiring layer 19d are further stacked on the surface of the second wiring layer 19c on the second surface to form the second surface. The step of mounting the semiconductor element 14 can be performed after the formation of the multilayer wiring is completed.
- the first insulating layer 16 may be formed of a photosensitive resin, a fine via hole may be formed by photolithography, the second insulating resin may be formed of a non-photosensitive resin, and a via may be formed at low cost using a laser. Is possible.
- the semiconductor element 14 includes the metal post 15 provided on the surface of the electrode terminal 14a, and the surface of the metal post 15 is exposed in the first wiring formation step (for example, FIG. 13A). As described above, a step may be included in which a part of the first insulating layer 16 is removed and the connection portion 15 is formed by the metal post 15.
- the step of forming the first insulating layer 16 covering the semiconductor element 14 covers the outer peripheral portion of the semiconductor element 14 with the first insulating resin, and the surface of the semiconductor element 14 is the second.
- FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device 10 according to the first embodiment.
- a semiconductor device 10 in FIG. 1 includes a core substrate 11 in which front and back core wirings 12 are conducted through through vias 13, a semiconductor element 14 provided on the first surface of the core substrate 11, and a built-in semiconductor element 14.
- a wiring 19 a is provided on the surface of the layer 16 and the built-in layer 16.
- the electrode terminal 14a is provided in the surface of the semiconductor element 14, and the connection part 15 is connected to the electrode terminal 14a.
- the wiring 19 a and the electrode terminal 14 a of the semiconductor element 14 are connected via the connection portion 15.
- the wiring 19 a provided on the surface of the internal layer 16 and the core wiring 12 are connected via an internal layer via 17 provided in the internal layer 16.
- An insulating layer A (18-1) is provided on the upper surface of the built-in layer 16, and the first electrode 21 and the wiring 19 a are connected via the via 20.
- an insulating layer B (18-2) is provided on the second surface of the core substrate 11, which is the opposite surface provided with the built-in layer 16, and the second electrode 22 and the core wiring 12 are connected via the via 20. It is connected.
- solder resists 23 are provided on both surfaces of the semiconductor device 10 so as to open the first electrode 21 and the second electrode 22.
- the surface of the core substrate 11 on which the semiconductor element 14 is mounted is referred to as a first surface, and the opposite surface is referred to as a second surface.
- the face has no further meaning.
- wiring may be performed using the same conductive layer as the first electrode 21 and / or the same conductive layer as the second electrode 22.
- the same conductive layer as the first electrode 21 and / or the same conductive layer as the second electrode 22 also serves as a wiring layer.
- the insulating layer A (18-1) may have a plurality of layers. In that case, a narrow-pitch, multi-pin semiconductor element can be incorporated.
- the power supply and ground layers can be strengthened, so that the characteristic impedance can be improved.
- a reinforcing material 26 may be provided in the built-in layer 16 so as to surround the semiconductor element 14. In that case, warpage of the entire semiconductor device 10 and the chip can be effectively reduced.
- a reinforcing material 26 may be provided on the insulating layer A (18-1). In that case, the warpage of the entire semiconductor device 10 can be effectively reduced.
- a reinforcing material 26 may be provided on the insulating layer B (18-2). In that case, the warpage of the entire semiconductor device 10 can be effectively reduced.
- a semiconductor element built-in substrate using the core substrate 11 as a support will be considered.
- the semiconductor element 14 is built in one surface (first surface) of the core substrate 11 and the resin layer (insulating layer B18-2) is not provided on the opposite surface (second surface), as shown in FIG.
- the warpage of the entire device 10 and the periphery of the chip greatly warps unevenness due to the relationship between the thermal expansion coefficient and the elastic modulus of the constituent materials. Therefore, there are problems in mounting other components on the semiconductor device 10, mounting the semiconductor device 10 on a motherboard, and long-term reliability.
- the semiconductor element 14 may be embedded in the first surface of the core substrate 11. In that case, since the resin thickness of the built-in layer 16 can be reduced, warping of the semiconductor device 10 can be suppressed. Further, since the aspect ratio of the built-in layer via 17 can be reduced, the built-in layer via 17 can be manufactured with a high yield.
- the built-in layer 16, the insulating layer A (18-1), and the insulating layer B (18-2) may be made of different insulating materials.
- the warping of the entire semiconductor device 10 can be suppressed by making the insulating material of the insulating layer B (18-2) more elastic than the insulating material of the built-in layer 16 and the insulating layer A (18-1).
- the electronic component 24 can be mounted on the semiconductor device 10 via the connection material 25.
- the electronic component 24 may be mounted on either the first electrode 21 or the second electrode 22 of the semiconductor element 14, the distance between the built-in semiconductor element 14 and the electronic component 24 is made closer to the semiconductor element 14.
- the wiring shape of the two electrodes 22 is preferably larger than the wiring of the nearest layer from the electrode surface of the semiconductor element 14, the via shape of the connection portion 15 that is a via, and the wiring shape of the wiring layer 19 a. Further, in this embodiment, by limiting the insulating layer B (18-2) to a single layer, a high-yield manufacturing technique is ensured. As a result, the yield of the insulating layer B (18-2) and the yield of the semiconductor device 10 can be improved.
- the via shape indicates the top diameter, the bottom diameter, and the height of the via
- the wiring shape indicates a wiring width, a pitch between wirings, a so-called wiring rule, and a wiring thickness.
- the core substrate 11 for example, a resin substrate, silicon, ceramic, glass, glass-epoxy composite, or the like is used. In particular, an organic resin substrate, a glass-epoxy composite, or the like is desirable from the viewpoint of cost and warpage control.
- the core substrate 11 is made of a rigid glass-epoxy composite.
- the number of wiring layers of the core substrate 11 is not limited to two layers on both sides, and is preferably a multilayer. In the present embodiment, the number of wiring layers of the core substrate 11 is four. Further, in order to improve the yield of the semiconductor device 10, it is desirable that the manufactured core substrate 11 is subjected to a non-defective inspection before the semiconductor element 14 is mounted.
- the specifications of the core substrate 11, for example, the wiring rule (L / S), via pitch, and via size are Specs (L / S: 50 ⁇ m / 50 ⁇ m, via pitch: 1 mm, via size 100 ⁇ m) that can be applied to mass production and can be realized at a high yield may be used. Further, by using such a high yield core substrate, the cost of the semiconductor device can be reduced.
- the thickness of the semiconductor element 14 can be adjusted according to the thickness required for the entire semiconductor device 10. In the present embodiment, the thickness of the semiconductor element 14 is 50 ⁇ m. In FIG. 1, the number of semiconductor elements 14 is one, but a plurality of semiconductor elements 14 may be used. In the present embodiment, one semiconductor element 14 is built in the built-in layer 16.
- DAF die attachment film
- insulating paste insulating paste
- silver paste a silver paste is used as an adhesive layer between the semiconductor element 14 and the core substrate 11.
- DAF is used.
- the area where the semiconductor element 14 of the core substrate 11 is mounted is an area where the core wiring 12 is not provided in order to ensure adhesion.
- the built-in layer 16, the insulating layer A (18-1), and the insulating layer B (18-2) are made of, for example, a photosensitive or non-photosensitive organic material.
- the organic material include an epoxy resin and an epoxy Acrylic resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobutylene), PBO (polybenzoxazole), polynorbornene resin, etc., epoxy resin on woven fabric and non-woven fabric made of glass cloth, aramid fiber, etc., A material impregnated with epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (benzocyclobenzene), PBO (polybenzoxazole), polynorbornene resin, or the like is used.
- the built-in layer 16 may be made of a photosensitive resin
- the insulating layer B (18-2) may be made of a non-photosensitive resin.
- the connecting portion 15 formed in the built-in layer 16 is finely processed as a photo via, and the via 20 formed in the insulating layer B (18-2) is used with a laser such as a UV-YAG laser or a CO2 laser. And can be processed at low cost.
- the built-in layer 16, the insulating layer A (18-1), and the insulating layer B (18-2) are made of a non-photosensitive epoxy resin.
- the core wiring 12, the wiring 19, the first electrode 21, and the second electrode 22 are, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, and palladium, or these as a main component. Use an alloy. In particular, it is desirable to form with copper from the viewpoint of electrical resistance value and cost.
- the core wiring 12, the wiring 19, the first electrode 21, and the second electrode 22 are made of copper.
- the through via 13, the built-in layer via 17, and the via 20 are made of, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, and palladium, or an alloy containing these as a main component. In particular, it is desirable to form with copper from the viewpoint of electrical resistance value and cost.
- the through via 13, the built-in layer via 17, and the via 20 are made of copper.
- a capacitor that serves as a noise filter of the circuit may be provided at a desired position in each layer.
- the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al 2 O 3 , SiO 2 , ZrO 2 , HfO 2, or Nb 2 O 5 , BST (Ba x Sr 1-x TiO 3). ), in PZT (PbZr x Ti 1-x O 3) or PLZT (Pb 1-y La y Zr x Ti 1-x O 3) perovskite material or SrBi 2 Ta Bi-based layered compounds such as 2 O 9, such as Preferably there is. However, 0 ⁇ x ⁇ 1 and 0 ⁇ y ⁇ 1. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used. In addition to semiconductor elements and capacitors, discrete parts may be provided.
- a rigid core substrate is used as a support in a semiconductor element built-in substrate incorporating a semiconductor element, a high yield semiconductor device can be realized.
- a single insulating layer is provided on the opposite surface of the built-in layer, the semiconductor device can be reduced in warpage.
- FIG. 2 is a partial sectional view showing the semiconductor device 10 according to the second embodiment.
- the semiconductor device 10 according to the first embodiment is different from the semiconductor device 10 according to the first embodiment in that the first surface of the core substrate 11 does not require the insulating layer A (18-1) and is configured only by the built-in layer 16.
- the reinforcing material is not provided in the insulating material of the built-in layer 16 and the insulating layer B (18-2) in FIG. 2, but a reinforcing material may be provided as shown in FIGS.
- the semiconductor The warp of the device 10 can be further reduced.
- the number of wiring layers other than the core substrate 11 is one on the front and back, the factor of reducing the yield is reduced, and the semiconductor device 10 can be manufactured with a high yield.
- the rigid core substrate 11 is used as the support in the semiconductor element built-in substrate in which the semiconductor element 14 is built, a high yield semiconductor device can be realized.
- one insulating layer and one wiring layer are provided on both surfaces of the core substrate 11, the yield and the warpage of the semiconductor device can be significantly improved.
- FIG. 9 is a cross-sectional view of a main part of the semiconductor device according to the third embodiment.
- the semiconductor device 10 according to the third embodiment is different from that according to the first embodiment in which the multilayer insulating layer B (18-2) and the multilayer wiring layers 19c and 19d are provided on the second surface which is the opposite surface of the semiconductor element 14 mounting surface. Is different. Of the wiring layers on the second surface, the lowermost wiring layer is 19c, and the wiring layer above 19c is 19d. According to the third embodiment, since the second surface, which is the opposite surface of the semiconductor element 14 mounting surface, is also provided with the multilayer wiring, a wiring having a higher degree of freedom is formed even when the number of terminals of the semiconductor element 14 is larger. can do.
- the semiconductor element 14 can be shielded from noise by strengthening the power source and the ground layer and providing a shield layer.
- the semiconductor device 10 of the third embodiment can be manufactured with a high yield after the semiconductor element 14 is mounted on the core substrate 11.
- the solder resist 23 is not provided on the second electrode 22 formation surface of the second surface, but if necessary, the solder resist is also formed on the outermost layer of the second surface as in the first embodiment. 23 can also be provided.
- FIGS. 13 (a) and 13 (b) are cross-sectional views illustrating the method of manufacturing the semiconductor device 10 according to the fourth embodiment in the order of steps.
- FIGS. 13 (a) and 13 (b) are processes following (a) to (c) of FIG.
- the semiconductor device 10 of Embodiment 1 FIG. 1
- a core substrate 11 is prepared in which core wirings 12 on the front and back sides are connected via through vias 13.
- the core substrate is desirably a highly rigid material. Moreover, it is desirable that the non-defective product inspection has been completed.
- a position mark for mounting the semiconductor element 14 is preferably provided on the core substrate 11. As long as the position mark can be recognized with high accuracy and functions as a position mark, a metal may be deposited on the core substrate 11 or a recess may be provided by wet etching or machining. In this embodiment, a glass-epoxy composite having a core substrate thickness of 0.8 mm and four wiring layers is used, and the position mark is the core wiring 12.
- the semiconductor element 14 is mounted on the core substrate 11 provided with the position mark so that the surface of the electrode terminal 14a of the semiconductor element 14 is the front.
- an adhesive layer is preferably provided between the core substrate 11 and the semiconductor element 14, but the resin surface of the uncured core substrate 11 may be handled as an adhesive surface.
- the terminal surface (electrode terminal 14 a) and the side surface of the semiconductor element 14 are laminated with the built-in layer 16.
- a film-like insulating material may be laminated so that the terminal surface and side surface of the semiconductor element 14 are collectively covered, or the terminal surface and side surface of the semiconductor element 14 may be separately laminated.
- the film-like insulating resin there is no limitation to the film-like insulating resin, and it may be liquid.
- the insulating material used for the built-in layer 16 is formed of, for example, a photosensitive or non-photosensitive organic material.
- the organic material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, and polyimide.
- the lamination method is provided by a transfer molding method, a compression molding method, a printing method, a vacuum press, a vacuum lamination, a spin coating method, a die coating method, a curtain coating method, or the like.
- an epoxy resin is used as the insulating resin, and the terminal surface and the side surface of the semiconductor element 14 are laminated together by vacuum lamination.
- connection portion 15 is formed on the electrode terminal 14 a on the semiconductor element 14, the built-in layer via 17 is formed on the core substrate 11, and the connection portion 15 and the built-in layer via is formed on the built-in layer 16.
- a wiring 19 a is formed to connect 17.
- a hole to be a connection portion 15 and a built-in layer via 17 is formed in the built-in layer 16. The holes are formed by photolithography when the built-in layer 16 uses a photosensitive material. If a photosensitive material having a high pattern resolution is used, fine holes can be processed.
- the hole is formed by a laser processing method, a dry etching method, or a blast method.
- a laser processing method is used.
- the hole 15 is filled with, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, and palladium, or an alloy containing these as a main component, and the connection portion 15 and the built-in via Layer 17 is formed.
- the filling method is performed by electrolytic plating, electroless plating, printing method, molten metal suction method, or the like.
- the connecting portion 15 and the built-in via layer 17 are provided with a metal post for energization in advance on the semiconductor element 14 or on the core substrate 11, and after the built-in layer 16 is formed, the surface of the insulating resin is polished by polishing or the like. A method of forming a via by shaving to expose the surface of the metal post may be used.
- the wiring 19a is formed by a method such as a subtractive method, a semi-additive method, or a full additive method.
- the subtractive method is a method in which a resist having a desired pattern is formed on a copper foil provided on a substrate, an unnecessary copper foil is etched, and then the resist is removed to obtain a desired pattern.
- a power supply layer is formed by an electroless plating method, a sputtering method, a CVD (chemical vapor deposition) method, etc., a resist having an opening in a desired pattern is formed, and a metal by electrolytic plating is formed in the resist opening. Is deposited, and after removing the resist, the power feeding layer is etched to obtain a desired wiring pattern.
- a pattern is formed with a resist, and the catalyst is activated while leaving the resist as an insulating film.
- a desired wiring pattern is obtained by depositing metal.
- the wiring 19a for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, aluminum, and palladium, or an alloy containing these as a main component is used. In particular, it is desirable to form with copper from the viewpoint of electrical resistance value and cost.
- the insulating layer A (18-1), the first electrode 21, and the via 20 are formed on the upper surface of the built-in layer 16, and the second surface, which is the opposite surface of the built-in layer 16, is formed.
- the insulating layer B (18-2), the second electrode 22, and the via 20 are formed.
- the number of wiring layers of the insulating layer A (18-1) may be increased by the desired number of layers, but in this embodiment of the manufacturing method, the insulating layer B (18-2) is a single-layer wiring.
- a wiring connecting the via 20 and the second electrode 22 may be provided in the same conductive layer as the second electrode 22.
- the insulating layer B (18-2) may be formed before the semiconductor element 14 is mounted.
- the semiconductor device 10 which is a substrate with a built-in semiconductor element is efficiently manufactured. Further, according to the present embodiment, since the rigid core substrate 11 is used as a support, the semiconductor device 10 with a high yield can be realized. In addition, since the single insulating layer is provided on the opposite surface of the built-in layer 16, the semiconductor device 10 can be reduced in warpage. In particular, the formation of the wiring layer 19a directly connected to the built-in layer 16 on the first surface of the core substrate 11 which is the semiconductor element mounting surface and the connecting portion 15 thereon, and the insulating layer B (18-2) on the second surface The wiring layer (second electrode) 22 including the vias 20 is formed in a separate process.
- connection portion 15 directly connected to the electrode terminal 14a of the semiconductor element 14 and the wiring 19a are processed using a process capable of fine processing, and the formation of the insulating layer, via, and wiring layer on the second surface is low in cost.
- a process capable of high-yield processing can be used.
- the internal layer 16 is made of a high-resolution photosensitive material that can be finely processed, and the connection portion 15 is formed with high precision by photolithography, and the insulating layer B (18-2) is not exposed to light.
- a hole that becomes a via hole may be formed at a low cost using a UV-YAG laser or a CO2 laser.
- the entire wiring formation can be made at low cost.
- FIG. 17 are partial cross-sectional views illustrating the method of manufacturing the semiconductor device according to the fifth embodiment in the order of steps.
- the semiconductor device 10 of the second embodiment shown in FIG. 2 can be manufactured.
- the manufacturing method according to the fifth embodiment is different from the manufacturing method according to the fourth embodiment in that the insulating layer on the first surface (the surface on which the semiconductor element 14 is mounted) of the core substrate 11 is composed of only the built-in layer 16 and the insulating layer A (18 The difference is that -1) is not formed.
- parts different from the manufacturing method according to the fourth embodiment will be described. Parts that are not particularly described are the same as those in the manufacturing method according to the fourth embodiment.
- a core substrate 11 is prepared in which core wirings 12 on the front and back sides are connected through through vias 13.
- the semiconductor element 14 is mounted on the core substrate 11 provided with the position marks with the terminal surface of the semiconductor element 14 being on the upper surface.
- the terminal surface and the side surface of the semiconductor element 14 are stacked with the built-in layer 16.
- the connection portion 15 is connected to the electrode terminal 14 a of the semiconductor element 14, the internal layer via 17 is connected to the core substrate 11, and the connection portion 15 and the internal layer via 17 are connected to the internal layer 16.
- the first electrode 21 to be formed is formed.
- the insulating layer B (18-2), the second electrode 22, and the via 20 are formed on the opposite surface of the built-in layer 16.
- a wiring (corresponding to 19a in FIG. 13A) may be provided in the same conductive layer as the first electrode 21, and the connecting portion 15 and the first electrode 21 may be connected by this wiring.
- the semiconductor device 10 which is a substrate with a built-in semiconductor element is efficiently manufactured.
- the rigid core substrate 11 is used as a support, a semiconductor device with a high yield can be realized.
- the single insulating layer 18-2 is provided on the opposite surface of the built-in layer 16, it is possible to reduce the warpage of the semiconductor device.
- one insulating layer and one wiring layer are provided on both surfaces of the core substrate 11, the yield and the warpage of the semiconductor device can be significantly improved.
- FIG. 18A and 18B are cross-sectional views of the main part of the intermediate process showing the method for manufacturing the semiconductor device 10 of the sixth embodiment.
- a multilayer insulating layer and a wiring layer are formed on the second surface of the core substrate 11 opposite to the semiconductor element mounting surface.
- the second electrode 22 is first formed in the outermost wiring layer.
- a test is performed before mounting the semiconductor element 14 to confirm that the core substrate 11 and the pattern on the second surface are free from defects.
- FIG. 18B the semiconductor element 14 is mounted on a support substrate on which it has been confirmed that the wiring pattern on the second surface is free from defects. Thereafter, only the step of processing the first surface among the steps of the fourth and fifth embodiments is performed to complete the semiconductor device 10 shown in FIG.
- the formation of the built-in layer 16, the connection portion 15, and the wiring 19a on the first surface, and the formation of the insulating layer 18-2, the via 20, and the wirings 19c and 19d on the second surface are performed in separate steps. Therefore, it is possible to finely process the connection portion 15 and the wiring layer 21 on the first surface, and to manufacture the via 20 and the wiring layer 22 on the second surface at a low cost and with a high yield.
- the semiconductor element 14 is mounted on the core substrate 11 after the formation and testing of the wiring pattern on the second surface is completed. Therefore, the process of mounting the semiconductor element 14 on the core substrate 11 can be as late as possible. Therefore, the yield in the process after mounting the semiconductor element 14 on the core substrate can be particularly increased, and the probability that the semiconductor device 10 including the semiconductor element 14 must be discarded due to a defect other than the semiconductor element 14 is reduced. be able to.
- each via provided on the second surface is larger than the shape of the connection portion.
- the top diameter, the bottom diameter, and the height of each via provided on the second surface are larger than the top diameter, the bottom diameter, and the height of the connection portion, respectively.
- the volume of each via provided on the second surface is three times or more the volume of the connection portion.
- the thickness of the wiring layer directly connected to the connection portion is thinner than the thickness of any wiring layer provided on the second surface.
- the thickness, minimum wiring width, and minimum wiring interval of each wiring layer provided on the second surface are 1 with respect to the thickness, minimum wiring width, and minimum wiring interval of the wiring layer directly connected to the connection portion. It is preferably 5 times larger.
- the material of the insulating layer around the connecting portion is different from the material of the insulating layer not including the connecting portion.
- the insulating layer around the connection portion is formed of a photosensitive resin, and the insulating layer provided on the second surface is formed of a non-photosensitive resin.
- the elastic modulus of the insulating layer around the connecting portion is lower than the elastic modulus of the insulating layer not including the connecting portion.
- the connecting portion does not contain a solder material or a resin component.
- the insulating layer and the wiring layer on the second surface are each one layer.
- the insulating layer and the wiring layer on the first surface are each one layer.
- external electrodes are provided on the outermost wiring layers of the first surface and the second surface, respectively.
- the minimum pitch of the connection portions is narrower than the minimum pitch of the external electrodes.
- Form 15 It is preferable to further include an electronic component connected to the external electrode.
- Form 16 It is preferable that a recess is formed in the first surface of the core substrate, and the semiconductor element is mounted in the recess.
- a plurality of semiconductor elements are mounted on the first surface of the core substrate with an element formation surface as a front.
- a reinforcing material is provided on at least one of the plurality of insulating layers.
- Form 19 As stated in the second aspect.
- Form 20 In the first wiring formation step, it is preferable to form a wiring using an additive method, and in the second wiring formation step, a wiring is formed using a subtractive method.
- a step of mounting the semiconductor element is performed after the step of forming the second insulating layer.
- a step of mounting the semiconductor element is performed after the second wiring formation step.
- an insulating layer and a wiring layer are further stacked on the surface of the second wiring layer on the second surface, and after the formation of the multilayer wiring on the second surface is completed, the semiconductor It is preferable to carry out the step of mounting the element.
- a via hole reaching the electrode terminal of the semiconductor element from the surface of the first insulating layer and a via hole reaching the core wiring provided on the first surface are formed, and the via hole is formed. Is preferably filled with a conductive layer to form the connection portion and the via.
- Form 25 Forming the first insulating layer with a photosensitive resin, forming the via hole reaching the electrode terminal of the semiconductor element by photolithography, forming the second insulating layer with a non-photosensitive resin, And forming a via in the second insulating layer using a laser.
- the semiconductor element is a semiconductor element having a metal post provided on the surface of the electrode terminal, wherein the first wiring forming step forms a part of the first insulating layer so that the surface of the metal post is exposed. It is preferable to include a step of removing and forming the connection portion by the metal post.
- the step of forming the first insulating layer covering the semiconductor element includes a step of covering an outer peripheral portion of the semiconductor element with a first insulating resin, and a step of covering the surface of the semiconductor element with a second insulating resin. Is preferred.
- the present invention is not limited only to the configurations of the above embodiments, and of course includes various modifications and corrections that can be made by those skilled in the art within the scope of the present invention. It is. In other words, within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.
Abstract
Description
本願は、先の日本特許出願2009-122209号(2009年5月20日出願)の優先権を主張するものであり、前記先の出願の全記載内容は、本書に引用をもって繰込み記載されているものとみなされる。
本発明は、半導体装置及びその製造方法に関する。特に、半導体素子を配線基板に内蔵した半導体装置及びその製造方法に関する。
以下の分析は本発明により与えられる。特許文献1の実施例に記載されているようにコア基板の片側に半導体素子を内蔵し、その片側のみに絶縁層と配線層を積層すると、以下の反りが発生する。すなわち、コア基板を下側にした場合に、半導体装置全体は凹の反りとなり、半導体素子周辺では凸の反りが生じる。したがって、他の部品の搭載や、半導体装置のマザーボードへの搭載に問題が生じる。
図1は、実施形態1の半導体装置10の構造を示す断面図である。図1の半導体装置10は、貫通ビア13を介し表裏のコア配線12が導通されたコア基板11と、コア基板11の第1面に設けられた半導体素子14と、半導体素子14を内蔵する内蔵層16と、内蔵層16の表面に配線19aが設けられている。また、半導体素子14の表面には、電極端子14aが設けられ、電極端子14aには、接続部15が接続されている。配線19aと半導体素子14の電極端子14aは、その接続部15を介して接続されている。また、内蔵層16の表面に設けられた配線19aとコア配線12は、内蔵層16内に設けられた内蔵層ビア17を介して接続されている。また、内蔵層16の上面には、絶縁層A(18-1)が設けられ、第1電極21と配線19aは、ビア20を介して接続されている。さらに、コア基板11の内蔵層16が設けられた反対面である第2面には、絶縁層B(18-2)が設けられ、第2電極22とコア配線12は、ビア20を介して接続されている。さらに、半導体装置10の両面には第1電極21と第2電極22を開口させるようにソルダーレジスト23が設けられている。なお、この明細書において、コア基板11の半導体素子14が搭載された方の面を第1面と呼び、その反対面を第2面と呼ぶが、本明細書において、第1面、第2面には、それ以上の意味はない。また、図1には図示していないが、第1電極21と同一の導電層、及び/または、第2電極22と同一の導電層、で配線を施してもよい。この場合、第1電極21と同一の導電層、及び/または、第2電極22と同一の導電層、はそれぞれ配線層ともなる。
次に、本発明の実施形態2の半導体装置について説明する。図2は実施形態2による半導体装置10を示す部分断面図である。実施形態1に係る半導体装置10とは、コア基板11の第1面には、絶縁層A(18-1)は必要とせず、内蔵層16のみで構成されている点が異なっている。以下に、実施形態1による半導体装置10と異なる部分について説明を行う。特に記載のない部分については、実施形態1に係る半導体装置10と同じである。また、図2の内蔵層16、絶縁層B(18-2)の絶縁材料には補強材を設けていないが、図6、8のように補強材を設けても構わない。
図9は、実施形態3による半導体装置の主要部の断面図である。実施形態3による半導体装置10は、半導体素子14搭載面の反対面である第2面に、多層の絶縁層B(18-2)と多層の配線層19c、19dを設けている実施形態1と異なっている。なお、第2面の配線層のうち、最下層の配線層を19c、19cより上層の配線層を19dとしている。実施形態3によれば、半導体素子14搭載面の反対面である第2面にも、多層配線を施しているので、半導体素子14の端子数がより多い場合でもより自由度の高い配線を形成することができる。また、第2面においても、電源やグランド層を強化することや、シールド層を設けることにより半導体素子14をノイズから遮蔽することもできる。なお、実施形態3の半導体装置10も後で述べる製造方法によれば、半導体素子14をコア基板11に搭載した後の歩留まりを高歩留まりに製造することができる。また、図9では、第2面の第2電極22形成面には、ソルダーレジスト23を設けていないが、必要に応じて、実施形態1と同様に、第2面の最外層にもソルダーレジスト23を設けることもできる。
次に、半導体装置10の製造方法の実施形態について説明する。図12の(a)から(c)と図13の(a)、(b)は、実施形態4による半導体装置10の製造方法を工程順に示す断面図である。図13の(a)、(b)は、図12の(a)から(c)に続く工程である。本実施形態の製造方法によれば、実施形態1(図1)の半導体装置10を製造することができる。
図16の(a)から(c)と図17は、実施形態5による半導体装置の製造方法を工程順に示す部分断面図である。実施形態5の半導体装置10の製造方法によれば、図2に示す実施形態2の半導体装置10を製造することができる。実施形態5による製造方法は、実施形態4による製造方法とは、コア基板11の第1面(半導体素子14搭載面)の絶縁層が内蔵層16のみで構成されており、絶縁層A(18-1)を形成していない点が異なっている。以下に、実施形態4に係る製造方法と異なる部分について説明を行う。特に記載のない部分については、実施形態4に係る製造方法と同じである。
図18(a)、(b)は、実施形態6の半導体装置10の製造方法を示す途中工程の主要部断面図である。本実施形態においては、図18(a)に示すようにコア基板11の半導体素子搭載面の反対面である第2面に多層の絶縁層と配線層を形成する。さらに、最外層の配線層には、第2電極22を先に形成しておく。ここまで第2面の配線パターンが完成した段階で半導体素子14の搭載前に試験を行い、コア基板11及び第2面のパターンに欠陥がないことを確認しておく。次に、図18(b)に示すように第2面の配線パターンに欠陥がないことが確認された支持基板に半導体素子14を搭載する。この後は、実施形態4、実施形態5の工程のうち、第1面を加工する工程のみを実施して図9に示す半導体装置10を完成させる。
(形態1)
第1の側面に既述のとおり。
(形態2)
前記第2面に設けられた各ビアの形状が、前記接続部の形状よりいずれも大きいことが好ましい。
(形態3)
前記第2面に設けられた各ビアのトップ径、ボトム径、高さがそれぞれ前記接続部のトップ径、ボトム径、高さより大きいことが好ましい。
(形態4)
前記第2面に設けられた各ビアの体積が、前記接続部の体積の3倍以上あることが好ましい。
(形態5)
前記接続部に直接接続される配線層の厚さが前記第2面に設けられたいずれの配線層の厚さより薄いことが好ましい。
(形態6)
前記接続部に直接接続される配線層の厚さ、最小配線幅、最小配線間隔に対して、前記第2面に設けられた各配線層の厚さ、最小配線幅、最小配線間隔がそれぞれ1.5倍以上大きいことが好ましい。
(形態7)
前記接続部周辺の絶縁層の材質が前記接続部を含まない絶縁層の材質と異なることが好ましい。
(形態8)
前記接続部周辺の絶縁層が感光性樹脂で形成され、前記第2面に設けられた絶縁層が非感光性樹脂で形成されていることが好ましい。
(形態9)
前記接続部周辺の絶縁層の弾性率が前記接続部を含まない絶縁層の弾性率より低いことが好ましい。
(形態10)
前記接続部がハンダ材料や樹脂成分を含まないことが好ましい。
(形態11)
前記第2面の絶縁層及び配線層がそれぞれ1層であることが好ましい。
(形態12)
前記第1面の絶縁層及び配線層がそれぞれ1層であることが好ましい。
(形態13)
前記第1面と第2面の最外層の配線層には、それぞれ外部電極が設けられていることが好ましい。
(形態14)
前記接続部の最小ピッチは、前記外部電極の最小ピッチより狭いことが好ましい。
(形態15)
前記外部電極に接続された電子部品をさらに含むことが好ましい。
(形態16)
前記コア基板の前記第1面に凹部が形成され、前記凹部内に前記半導体素子が搭載されていることが好ましい。
(形態17)
前記コア基板の前記第1面に素子形成面を表にして搭載された半導体素子が複数であることが好ましい。
(形態18)
前記複数の絶縁層のうち、少なくとも一つの絶縁層に補強材を設けたことが好ましい。
(形態19)
第2の側面に既述のとおり。
(形態20)
前記第1配線形成工程では、アディティブ法を用いて配線を形成し、前記第2配線形成工程では、サブトラクティブ法を用いて配線を形成することが好ましい。
(形態21)
前記第2絶縁層を形成する工程の後に、前記半導体素子を搭載する工程を実施することが好ましい。
(形態22)
前記第2配線形成工程の後に、前記半導体素子を搭載する工程を実施することが好ましい。
(形態23)
前記第2配線形成工程の後に前記第2面の第2配線層の表面にさらに、積層して絶縁層と配線層を形成し、前記第2面の多層配線の形成が完了してから前記半導体素子を搭載する工程を実施することが好ましい。
(形態24)
前記第1絶縁層を形成する工程の後、前記第1絶縁層の表面から前記半導体素子の電極端子に達するビアホールと前記第1面に設けられたコア配線に達するビアホールとを形成し、前記ビアホールを導電層で埋めて前記接続部と前記ビアとを形成することが好ましい。
(形態25)
前記第1絶縁層を感光性樹脂で形成する工程と、半導体素子の電極端子に達する前記ビアホールをフォトリソグラフィーにより形成する工程と、前記第2絶縁層を非感光性樹脂で形成する工程と、前記第2絶縁層にレーザーを用いてビアを形成する工程と、を含むことが好ましい。
(形態26)
前記半導体素子が前記電極端子の表面に設けられた金属ポストを有する半導体素子であって、前記第1配線形成工程が、前記金属ポストの表面が露出するように前記第1絶縁層の一部を除去し、前記金属ポストにより前記接続部を形成する工程を含むことが好ましい。
(形態27)
前記半導体素子を覆う第1絶縁層を形成する工程が、前記半導体素子の外周部を第1の絶縁樹脂により覆う工程と、前記半導体素子の表面を第2の絶縁樹脂により覆う工程とを備えることが好ましい。
以上、実施例について説明したが、本発明は上記実施例の構成にのみ制限されるものでなく、本発明の範囲内で当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
すなわち、本発明の全開示(請求の範囲を含む)の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
11:コア基板
12:コア配線
13:貫通ビア
14:半導体素子
14a:電極端子
15:接続部(金属ポスト)
16:内蔵層(絶縁層)
17:内蔵層ビア
18-1:絶縁層A
18-2:絶縁層B
19:配線層及び配線層に形成された配線
19a:接続部15に直接接続する配線が形成される配線層及びその配線層に形成された配線
19b:コア基板11の第1面側に設けられた配線層(配線)で19a以外の配線層及びその配線層に形成された配線
19c:コア基板11の第2面側の下層配線層及びその配線層に形成された配線
19d:コア基板11の第2面側の上層配線層及びその配線層に形成された配線
20:ビア
21:第1電極(配線層)
22:第2電極(配線層)
23:ソルダーレジスト
24:電子部品
25:接続材料
26:補強材
Claims (27)
- コア基板と、
前記コア基板の第1面と前記第1面の反対面である第2面に少なくとも1層ずつ設けられた絶縁層及び配線層と、
前記各絶縁層と前記コア基板に設けられ、前記配線層間を接続するビアと、
前記コア基板の前記第1面に電極端子形成面を表にして搭載された半導体素子と、
前記第1面に設けられた絶縁層を貫通し、前記半導体素子の電極端子と前記第1面に設けられた配線層とを直接接続する接続部と、が設けられ、
前記接続部に直接接続される配線層の最小配線ピッチは、前記第2面に設けられたいずれの配線層の最小配線ピッチよりも小さいことを特徴とする半導体装置。 - 前記第2面に設けられた各ビアの形状が、前記接続部の形状よりいずれも大きいことを特徴とする請求項1記載の半導体装置。
- 前記第2面に設けられた各ビアのトップ径、ボトム径、高さがそれぞれ前記接続部のトップ径、ボトム径、高さより大きいことを特徴とする請求項1又は2記載の半導体装置。
- 前記第2面に設けられた各ビアの体積が、前記接続部の体積の3倍以上あることを特徴とする請求項1乃至3いずれか1項記載の半導体装置。
- 前記接続部に直接接続される配線層の厚さが前記第2面に設けられたいずれの配線層の厚さより薄いことを特徴とする請求項1乃至4いずれか1項記載の半導体装置。
- 前記接続部に直接接続される配線層の厚さ、最小配線幅、最小配線間隔に対して、前記第2面に設けられた各配線層の厚さ、最小配線幅、最小配線間隔がそれぞれ1.5倍以上大きいことを特徴とする請求項1乃至5いずれか1項記載の半導体装置。
- 前記接続部周辺の絶縁層の材質が前記接続部を含まない絶縁層の材質と異なることを特徴とする請求項1乃至6いずれか1項記載の半導体装置。
- 前記接続部周辺の絶縁層が感光性樹脂で形成され、前記第2面に設けられた絶縁層が非感光性樹脂で形成されていることを特徴とする請求項1乃至7いずれか1項記載の半導体装置。
- 前記接続部周辺の絶縁層の弾性率が前記接続部を含まない絶縁層の弾性率より低いことを特徴とする請求項1乃至8いずれか1項記載の半導体装置。
- 前記接続部がハンダ材料や樹脂成分を含まないことを特徴とする請求項1乃至9いずれか1項記載の半導体装置。
- 前記第2面の絶縁層及び配線層がそれぞれ1層であることを特徴とする請求項1乃至10いずれか1項記載の半導体装置。
- 前記第1面の絶縁層及び配線層がそれぞれ1層であることを特徴とする請求項1乃至11いずれか1項記載の半導体装置。
- 前記第1面と第2面の最外層の配線層には、それぞれ外部電極が設けられていることを特徴とする請求項1乃至12いずれか1項記載の半導体装置。
- 前記接続部の最小ピッチは、前記外部電極の最小ピッチより狭いことを特徴とする請求項13記載の半導体装置。
- 前記外部電極に接続された電子部品をさらに含むことを特徴とする請求項13又は14記載の半導体装置。
- 前記コア基板の前記第1面に凹部が形成され、前記凹部内に前記半導体素子が搭載されていることを特徴とする請求項1乃至15いずれか1項記載の半導体装置。
- 前記コア基板の前記第1面に素子形成面を表にして搭載された半導体素子が複数であることを特徴とする請求項1乃至16いずれか1項記載の半導体装置。
- 前記複数の絶縁層のうち、少なくとも一つの絶縁層に補強材を設けたことを特徴とする請求項1乃至17いずれか1項記載の半導体装置。
- 第1面の表面と前記第1面の反対面である第2面の表面とにコア配線が設けられ、さらに前記第1面と第2面とのコア配線とを接続する貫通ビアが設けられたコア基板の第1面に、電極端子形成面を表にして半導体素子を搭載する工程と、
前記第1面に前記半導体素子を覆う第1絶縁層を形成する工程と、
前記第1絶縁層の表面に第1配線層を形成し、前記半導体素子の電極端子と接続部を介して接続された配線と、前記第1面に設けられた前記コア配線とビアを介して接続された配線と、を前記第1配線層に形成する第1配線形成工程と、
前記第2面に第2絶縁層を形成する工程と、
前記第2絶縁層の表面に第2配線層を形成し、前記第2面に設けられた前記コア配線とビアを介して接続された配線を前記第2配線層に形成する第2配線形成工程と、
を備えた半導体装置の製造方法であって、
前記第1絶縁層を形成する工程及び前記第1配線形成工程は、前記第2絶縁層を形成する工程及び第2配線形成工程とは、別工程で実施されることを特徴とする半導体装置の製造方法。 - 前記第1配線形成工程では、アディティブ法を用いて配線を形成し、前記第2配線形成工程では、サブトラクティブ法を用いて配線を形成することを特徴とする請求項19記載の半導体装置の製造方法。
- 前記第2絶縁層を形成する工程の後に、前記半導体素子を搭載する工程を実施することを特徴とする請求項19又は20記載の半導体装置の製造方法。
- 前記第2配線形成工程の後に、前記半導体素子を搭載する工程を実施することを特徴とする請求項19乃至21いずれか1項記載の半導体装置の製造方法。
- 前記第2配線形成工程の後に前記第2面の第2配線層の表面にさらに、積層して絶縁層と配線層を形成し、前記第2面の多層配線の形成が完了してから前記半導体素子を搭載する工程を実施することを特徴とする請求項22記載の半導体装置の製造方法。
- 前記第1絶縁層を形成する工程の後、前記第1絶縁層の表面から前記半導体素子の電極端子に達するビアホールと前記第1面に設けられたコア配線に達するビアホールとを形成し、前記ビアホールを導電層で埋めて前記接続部と前記ビアとを形成することを特徴とする請求項19乃至23いずれか1項記載の半導体装置の製造方法。
- 前記第1絶縁層を感光性樹脂で形成する工程と、半導体素子の電極端子に達する前記ビアホールをフォトリソグラフィーにより形成する工程と、前記第2絶縁層を非感光性樹脂で形成する工程と、前記第2絶縁層にレーザーを用いてビアを形成する工程と、を含むことを特徴とする請求項24記載の半導体装置の製造方法。
- 前記半導体素子が前記電極端子の表面に設けられた金属ポストを有する半導体素子であって、前記第1配線形成工程が、前記金属ポストの表面が露出するように前記第1絶縁層の一部を除去し、前記金属ポストにより前記接続部を形成する工程を含むことを特徴とする請求項19乃至23いずれか1項記載の半導体装置の製造方法。
- 前記半導体素子を覆う第1絶縁層を形成する工程が、前記半導体素子の外周部を第1の絶縁樹脂により覆う工程と、前記半導体素子の表面を第2の絶縁樹脂により覆う工程とを備えることを特徴とする請求項19乃至26いずれか1項記載の半導体装置の製造方法。
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