WO2009122774A1 - キャパシタ形成材及びキャパシタを備えたプリント配線板 - Google Patents
キャパシタ形成材及びキャパシタを備えたプリント配線板 Download PDFInfo
- Publication number
- WO2009122774A1 WO2009122774A1 PCT/JP2009/051905 JP2009051905W WO2009122774A1 WO 2009122774 A1 WO2009122774 A1 WO 2009122774A1 JP 2009051905 W JP2009051905 W JP 2009051905W WO 2009122774 A1 WO2009122774 A1 WO 2009122774A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- metal
- capacitor
- oxide
- forming material
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims description 176
- 229910052751 metal Inorganic materials 0.000 claims abstract description 182
- 239000002184 metal Substances 0.000 claims abstract description 182
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 129
- 239000000203 mixture Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 137
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 73
- 238000004519 manufacturing process Methods 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 56
- 230000015572 biosynthetic process Effects 0.000 claims description 55
- 239000010949 copper Substances 0.000 claims description 31
- 229910052759 nickel Inorganic materials 0.000 claims description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 17
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 16
- 229910000480 nickel oxide Inorganic materials 0.000 claims description 14
- 238000002441 X-ray diffraction Methods 0.000 claims description 12
- 150000004706 metal oxides Chemical class 0.000 claims description 12
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 12
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 claims description 11
- 238000001228 spectrum Methods 0.000 claims description 10
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 9
- 239000005751 Copper oxide Substances 0.000 claims description 8
- 229910000431 copper oxide Inorganic materials 0.000 claims description 8
- 239000010408 film Substances 0.000 description 38
- 230000000052 comparative effect Effects 0.000 description 31
- 238000004544 sputter deposition Methods 0.000 description 21
- 239000011888 foil Substances 0.000 description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 16
- 239000001301 oxygen Substances 0.000 description 16
- 229910052760 oxygen Inorganic materials 0.000 description 16
- 230000008569 process Effects 0.000 description 15
- 238000010304 firing Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 13
- 238000005259 measurement Methods 0.000 description 12
- 238000004148 unit process Methods 0.000 description 12
- 238000003980 solgel method Methods 0.000 description 10
- 238000011156 evaluation Methods 0.000 description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 6
- 229910001096 P alloy Inorganic materials 0.000 description 6
- 229910001252 Pd alloy Inorganic materials 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- WZOZCAZYAWIWQO-UHFFFAOYSA-N [Ni].[Ni]=O Chemical compound [Ni].[Ni]=O WZOZCAZYAWIWQO-UHFFFAOYSA-N 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 229910001882 dioxygen Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 229910001297 Zn alloy Inorganic materials 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229910001316 Ag alloy Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 229910000531 Co alloy Inorganic materials 0.000 description 3
- QXZUUHYBWMWJHK-UHFFFAOYSA-N [Co].[Ni] Chemical compound [Co].[Ni] QXZUUHYBWMWJHK-UHFFFAOYSA-N 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000007774 longterm Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000005096 rolling process Methods 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- RIRXDDRGHVUXNJ-UHFFFAOYSA-N [Cu].[P] Chemical compound [Cu].[P] RIRXDDRGHVUXNJ-UHFFFAOYSA-N 0.000 description 2
- KOMIMHZRQFFCOR-UHFFFAOYSA-N [Ni].[Cu].[Zn] Chemical compound [Ni].[Cu].[Zn] KOMIMHZRQFFCOR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- QRJOYPHTNNOAOJ-UHFFFAOYSA-N copper gold Chemical compound [Cu].[Au] QRJOYPHTNNOAOJ-UHFFFAOYSA-N 0.000 description 2
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 2
- XPPWAISRWKKERW-UHFFFAOYSA-N copper palladium Chemical compound [Cu].[Pd] XPPWAISRWKKERW-UHFFFAOYSA-N 0.000 description 2
- YCKOAAUKSGOOJH-UHFFFAOYSA-N copper silver Chemical compound [Cu].[Ag].[Ag] YCKOAAUKSGOOJH-UHFFFAOYSA-N 0.000 description 2
- 239000003353 gold alloy Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 2
- MOFOBJHOKRNACT-UHFFFAOYSA-N nickel silver Chemical compound [Ni].[Ag] MOFOBJHOKRNACT-UHFFFAOYSA-N 0.000 description 2
- 239000010956 nickel silver Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000197 pyrolysis Methods 0.000 description 2
- 238000005204 segregation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000026 X-ray photoelectron spectrum Methods 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(i) oxide Chemical compound [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- UREBDLICKHMUKA-CXSFZGCWSA-N dexamethasone Chemical compound C1CC2=CC(=O)C=C[C@]2(C)[C@]2(F)[C@@H]1[C@@H]1C[C@@H](C)[C@@](C(=O)CO)(O)[C@@]1(C)C[C@@H]2O UREBDLICKHMUKA-CXSFZGCWSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010525 oxidative degradation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000001603 reducing effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- VLCQZHSMCYCDJL-UHFFFAOYSA-N tribenuron methyl Chemical compound COC(=O)C1=CC=CC=C1S(=O)(=O)NC(=O)N(C)C1=NC(C)=NC(OC)=N1 VLCQZHSMCYCDJL-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
- H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
- H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
- H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2063—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10 mixed adhesion layer containing metallic/inorganic and polymeric materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0315—Oxidising metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Definitions
- the invention according to the present application relates to a capacitor forming material and a printed wiring board including the capacitor.
- the capacitor forming material referred to in the present invention has a structure including a dielectric layer between the upper electrode forming layer and the lower electrode forming layer.
- the upper electrode formation layer and the lower electrode formation layer form a capacitor circuit by etching or the like.
- such a capacitor forming material is generally used as a capacitor forming material for a printed wiring board.
- the capacitor forming material of the upper electrode forming layer / dielectric layer / lower electrode forming layer has a problem of adhesion at the interface between the lower electrode forming layer and the dielectric layer and at the interface between the upper electrode forming layer and the dielectric layer. There is. When the adhesion at these positions is lowered, a gap is generated between the dielectric layer and each electrode forming layer, and the required quality as a capacitor of the formed capacitor circuit is not satisfied.
- Patent Document 2 discloses that even when inexpensive Cu is used as an electrode, the conductivity between the electrode film and the dielectric film is sufficiently ensured while ensuring sufficient conductivity of the electrode film.
- the thin film capacitor having a pair of electrode films and a dielectric film provided between the pair of electrode films At least one of the electrode films is a Cu electrode film containing Cu, an adhesion layer containing Cu 2 O is provided between the Cu electrode film and the dielectric film, and the dielectric film is an oxide
- a thin film capacitor characterized by being a dielectric film is disclosed.
- the dielectric film 4 is a solution coating and baking method such as a sol-gel method or a MOD method (organometallic compound deposition method), or a PVD such as a sputtering method.
- the film is formed using a film forming technique such as a CVD method or a CVD method, ”which suggests the use of a sol-gel method.
- a film forming technique such as a CVD method or a CVD method
- the inventors of the present invention have the following invention to stabilize the adhesion between the electrode forming layer and the dielectric layer, and to provide a capacitor forming material for producing a printed wiring board having a high electric capacity and It was conceived that a printed wiring board provided with a capacitor could be provided.
- the outline of the invention will be described.
- Capacitor forming material is a capacitor forming material including an oxide dielectric layer between an upper electrode forming layer and a lower electrode forming layer, and at least one of the upper electrode forming layer and the lower electrode forming layer.
- the present invention is also characterized in that a three-layer structure including a different metal layer between the bulk metal layer and the metal-metal oxide mixed layer is employed. Therefore, it has three types of layer configurations to be described later. These are hereinafter referred to as type I (type Ia, type Ib), type II (type II-a, type II-b), and type III (type III-a, type III-b).
- Capacitor forming material manufacturing method The capacitor forming material manufacturing method according to the present invention preferably employs the following three manufacturing methods according to the type of the capacitor forming material.
- an oxide dielectric layer is formed on the surface of the lower electrode forming layer, and a bulk metal layer / metal-metal oxide mixed layer is formed on the surface of the oxide dielectric layer.
- a manufacturing method characterized by forming a laminate having an upper electrode forming layer having a two-layer structure or a three-layer structure of a bulk metal layer / a different metal layer / a metal-metal oxide mixed layer is employed.
- the laminate referred to in this type I manufacturing method is ("upper electrode formation layer (metal-metal oxide mixed layer / bulk metal layer) / dielectric layer / lower electrode formation layer” or "upper electrode formation layer (metal-metal Oxide mixed layer / dissimilar metal layer / bulk metal layer) / dielectric layer / lower electrode forming layer ”).
- the lower electrode formation layer in Type I is a layer made of a metal that does not intentionally contain a metal oxide.
- a metal-metal oxide mixed layer is provided on the surface of the bulk metal layer, or a different metal layer / metal-metal oxide is provided on the surface of the bulk metal layer.
- a laminated body in which an oxide dielectric layer is formed on the metal-metal oxide mixed layer on the surface of the lower electrode formation layer and an upper electrode formation layer is further formed on the surface of the oxide dielectric layer. Adopting the characteristic manufacturing method.
- the laminate referred to in this type II manufacturing method is (“upper electrode forming layer / dielectric layer / lower electrode forming layer (metal-metal oxide mixed layer / bulk metal layer)” or “upper electrode forming layer / dielectric layer / The lower electrode forming layer (metal-metal oxide mixed layer / dissimilar metal layer / bulk metal layer) ”) is provided.
- the upper electrode formation layer in Type II is a layer made of a metal that does not intentionally contain a metal oxide.
- a metal-metal oxide mixed layer is provided on the surface of the bulk metal layer, or a different metal layer / metal-metal oxide is provided on the surface of the bulk metal layer.
- an oxide dielectric layer is formed on the metal-metal oxide mixed layer on the surface of the lower electrode forming layer.
- a laminate in which an upper electrode forming layer having a two-layer structure of bulk metal layer / metal-metal oxide mixed layer or a three-layer structure of bulk metal layer / different metal layer / metal-metal oxide mixed layer is formed on the surface. The manufacturing method of the capacitor forming material characterized by this is adopted.
- the printed wiring board according to the present invention includes a built-in capacitor layer, and is obtained by forming a built-in capacitor layer using the capacitor forming material described above. To do.
- the printed wiring board according to the present invention is obtained by arranging the capacitor forming material described above in the printed wiring board.
- the capacitor forming material according to the present invention is a capacitor forming material comprising an oxide dielectric layer formed between an upper electrode forming layer and a lower electrode forming layer, wherein at least one of the upper electrode forming layer and the lower electrode forming layer is “Bulk metal layer / metal-metal oxide mixed layer two-layer structure” or “bulk metal layer / different metal layer / metal-metal oxide mixed layer three-layer structure” is provided.
- a printed wiring board in which a capacitor layer is formed using the capacitor forming material for manufacturing the printed wiring board includes a capacitor exhibiting stable capacitor characteristics, and becomes a high-quality multilayer printed wiring board.
- FIG. 3 is a schematic cross-sectional view for explaining a layer structure of a capacitor forming material (type Ia) according to the present invention.
- FIG. 3 is a schematic cross-sectional view for explaining a layer structure of a capacitor forming material (type Ib) including a dissimilar metal layer according to the present invention.
- FIG. 3 is a schematic cross-sectional view for explaining a layer structure of a capacitor forming material (type II-a) according to the present invention.
- FIG. 6 is a schematic cross-sectional view for explaining a layer structure of a capacitor forming material (type II-b) including a dissimilar metal layer according to the present invention.
- FIG. 3 is a schematic cross-sectional view for explaining a layer structure of a capacitor forming material (type III-a) according to the present invention.
- FIG. 4 is a schematic cross-sectional view for explaining a layer structure of a capacitor forming material (type III-b) including a dissimilar metal layer according to the present invention.
- XPS measurement it is a measurement spectrum shown as an example of a state in which a “nickel spectrum” and a “nickel oxide spectrum” can be confirmed separately. It is a schematic diagram for showing the measurement location in XPS measurement and XRD measurement.
- the capacitor forming material 1 for manufacturing a printed wiring board according to the present invention is a capacitor forming material including an oxide dielectric layer 4 between an upper electrode forming layer 2 and a lower electrode forming layer 3, and the upper electrode forming layer 2 and At least one of the lower electrode formation layers 3 has a two-layer structure of bulk metal layer 5 / metal-metal oxide mixed layer 6 in contact with the oxide dielectric layer. Therefore, three types of layer configurations are provided. Hereinafter, each of type I to type III will be described with reference to the drawings. Each type includes an a-type that does not include a dissimilar metal layer and a b-type that includes a dissimilar metal layer. Therefore, it is classified as type Ia and type Ib.
- Type I capacitor forming materials include type Ia shown in FIG. 1 and type Ib shown in FIG.
- the capacitor forming material 1a (type Ia) for manufacturing a printed wiring board according to the present invention comprises the upper electrode forming layer 2, a bulk metal layer 5 and a metal-metal oxide mixed material. It is characterized in that it is composed of two layers with the layer 6.
- the upper electrode forming layer 2 includes a bulk metal layer 5, a dissimilar metal layer 7, a metal-metal. A structure composed of three oxide mixed layers 6 is shown.
- Type II capacitor forming materials include type II-a shown in FIG. 3 and type II-b shown in FIG.
- the capacitor forming material 10a (type II-a) for manufacturing a printed wiring board according to the present invention includes the lower electrode forming layer 3, the bulk metal layer 5, and the metal-metal oxide mixed material. It is characterized in that it is composed of two layers 6.
- FIG. 4 also shows the lower electrode forming layer 3 as a capacitor forming material 10b (type II-b) for manufacturing a printed wiring board according to the present invention, a bulk metal layer 5, a dissimilar metal layer 7, a metal-metal. A structure composed of three oxide mixed layers 6 is shown.
- Type III capacitor forming materials include type III-a shown in FIG. 5 and type III-b shown in FIG.
- the capacitor forming material 20a (type III-a) for manufacturing a printed wiring board according to the present invention includes the upper electrode forming layer 2, the bulk metal layer 5, and the metal-metal oxide mixed material.
- the lower electrode forming layer 3 is composed of two layers of a bulk metal layer 5 and a metal-metal oxide mixed layer 6.
- the upper electrode forming layer 2 includes a bulk metal layer 5, a dissimilar metal layer 7, and a metal-metal.
- An oxide mixed layer 6 is composed of three layers
- the lower electrode forming layer 3 is composed of a bulk metal layer 5, a dissimilar metal layer 7, and a metal-metal oxide mixed layer 6. Yes.
- Each of the type I to type III capacitor forming materials having the layer configurations described above is common in the layer configuration including the oxide dielectric layer 4 between the upper electrode forming layer 2 and the lower electrode forming layer 3.
- At least one bulk metal of the formation layer 2 and the lower electrode formation layer 3 is provided with a “metal-metal oxide mixed layer 6” on the interface side with the oxide dielectric layer 4.
- the presence of the metal-metal oxide mixed layer 6 improves the adhesion between each electrode forming layer and the oxide dielectric layer 4.
- the “metal-metal oxide mixed layer 6” It is effective to provide it on the electrode forming layer side.
- a dissimilar metal layer is provided on both the upper electrode forming layer 2 and the lower electrode forming layer 3, but a dissimilar metal is provided on either the upper electrode forming layer 2 or the lower electrode forming layer 3. It should be noted that some layers may be provided.
- the capacitor forming material according to the present invention described above can form a capacitor circuit of a printed wiring board by etching at least one of the upper electrode forming layer 2 and the lower electrode forming layer 3 after being laminated on a prepreg or the like. it can. Further, a circuit can be formed in advance on the capacitor-forming material according to the present invention by etching, and this can be placed in a printed wiring board. In any case, the capacitor forming material according to the present invention functions as a capacitor in the printed wiring board.
- the capacitor forming material 1 for manufacturing a printed wiring board according to the present invention has a configuration in which an upper electrode forming layer 2 is formed by laminating a bulk metal layer 5 and a metal-metal oxide mixed layer 6.
- the metal-metal oxide mixed layer 6 comes into contact with the oxide dielectric layer 4.
- This metal-metal oxide mixed layer 6 is preferably composed of any one of copper oxide, nickel oxide, copper alloy oxide, and nickel alloy oxide. This is because the adhesiveness with the oxide dielectric layer and the adhesiveness with the bulk metal layer are excellent.
- the metal-metal oxide mixed layer mentioned here is not composed of 100% by weight of metal oxide but contains an unoxidized metal component.
- the copper oxide is mainly Cu 2 O, and is described as a concept including a complex state of Cu 2 O and CuO.
- the copper alloy oxides include copper-phosphorus alloys, copper-zinc alloys, copper-nickel-zinc alloys, copper-palladium alloys, copper-gold alloys, copper-silver alloy oxides, and the like.
- Nickel oxide is mainly NiO.
- the nickel alloy oxide is an oxide such as a nickel-phosphorus alloy, nickel-cobalt alloy, nickel-copper alloy, nickel-palladium alloy, nickel-silver alloy, nickel-cobalt-palladium alloy. In order to specify the state of this metal-metal oxide mixed layer, the following two indices can be used.
- the first index is a value measured by X-ray photoelectron spectroscopy (XPS) of the metal-metal oxide mixed layer. That is, when XPS measurement is performed on the metal-metal oxide mixed layer, the metal spectrum and the metal oxide spectrum constituting the metal-metal oxide mixed layer are separated and can be confirmed. It is preferable. For example, as shown in FIG. 7, a state in which peaks of “nickel spectrum” and “nickel oxide spectrum” can be confirmed separately is applicable. This is because, when such a measurement result is obtained by XPS measurement, the effect of improving the adhesion between the oxide dielectric layer and the upper electrode formation layer is easily obtained.
- XPS X-ray photoelectron spectroscopy
- the extreme surface of the metal-metal oxide mixed layer in contact with the oxide dielectric layer may be oxidized and may not be detected as a mixed layer. It is preferable to expose the inside of the metal-metal oxide mixed layer with XPS observation.
- the metal-metal oxide mixed layer is composed of nickel-nickel oxide
- the peak intensity of the (101) plane of nickel hereinafter simply referred to as “Ni (101)”
- the nickel oxide The peak intensity ratio ([Ni (101)] / [NiO (200)]) to the peak intensity of the (200) plane (hereinafter simply referred to as “NiO (200)”) is 0.02 to 50 or more.
- the range of 0.05 to 10 is more preferable.
- the value of [Ni (101)] / [NiO (200)] is referred to as “peak intensity ratio”.
- the peak intensity ratio is less than 0.02, it is not preferable because the adhesiveness with the oxide dielectric layer is likely to vary. On the other hand, if the peak intensity ratio exceeds 50, the oxide content becomes too low, and it becomes difficult to obtain adhesion with the oxide dielectric layer. When the peak intensity ratio is outside the range of 0.02 to 100, it can be considered that only one of the components is substantially present.
- the peak intensity referred to here is an area (integrated intensity) obtained by integrating the intensities of the X-ray diffraction chart. Ni represents PDF card # 04-0850, NiO represents PDF card # 44-1159. Refers.
- the surface of the metal-metal oxide mixed layer is not rough but has a uniform surface, and the adhesion to the bulk metal layer is also good.
- Table 1 the composition of (Ba 1-x Sr x ) TiO 3 (0 ⁇ x ⁇ 1) formed on the nickel foil (in Table 1, simply indicated as “BST”).
- the surface roughness (Ra) referred to here is measured with an AFM according to JIS B 0601 with a visual field of 2 ⁇ m ⁇ 2 ⁇ m.
- the measurement of each sample is the result of measurement at three locations by changing the location within the same sample.
- the metal-metal oxide mixed layer preferably has an average thickness of 5 nm or more.
- the average thickness of the metal-metal oxide mixed layer is less than 5 nm, the adhesion between the oxide dielectric layer and the bulk metal (and a different metal layer to be described later) is not stabilized.
- the average thickness is more preferably 10 nm or more.
- the upper limit of the average thickness is considered to be 200 nm from the viewpoint of manufacturing cost.
- the metal-metal oxide mixed layer described above can be formed by previously forming a metal layer on the oxide dielectric layer and then oxidizing the metal layer.
- a physical vapor deposition method such as a sol-gel method, a dry process such as a sputtering method, or an EB vapor deposition method because a uniform film thickness and composition can be maintained.
- the bulk metal layer constituting the upper electrode forming layer is preferably composed of any one of copper, nickel, a copper alloy, and a nickel alloy. It is preferable to use copper or a copper alloy when giving priority to heat dissipation as the upper electrode formation layer, and adopt nickel or nickel alloy when giving priority to strength.
- the bulk metal layer constituting the upper electrode forming layer preferably has an average thickness of 1 ⁇ m to 100 ⁇ m.
- the average thickness of the bulk metal layer is less than 1 ⁇ m, the strength is lowered, and therefore, careful handling is required, and the printed wiring board may be deformed by the press pressure during multilayer press, which is preferable. Absent.
- the average thickness of the bulk metal layer exceeds 100 ⁇ m, it is not preferable because processing of a fine upper electrode shape by an etching method becomes difficult and the shape of the formed upper electrode circuit is deteriorated.
- the bulk metal layer constituting the upper electrode forming layer is a method of laminating a metal foil on a metal-metal oxide mixed layer (or a dissimilar metal layer (only when a dissimilar metal layer described later is provided)), It is possible to employ a method such as a plating method or a sputtering method.
- the lower electrode forming layer is composed of a single metal component
- any one of copper, nickel, a copper alloy, and a nickel alloy is used.
- the metal base material used as the lower electrode forming layer here can be obtained as a metal foil, and a metal substrate capable of forming an oxide dielectric layer on its surface is used in its foil state. Therefore, the foil used for the structure of the lower electrode formation layer in the present invention includes all those obtained by a rolling method, an electrolytic method, and the like. And it is described as a concept including a composite foil provided with any one of these copper, copper alloy, nickel and nickel alloy layers in the outermost layer of the metal foil.
- a foil material constituting the lower electrode formation layer a composite foil having a nickel layer or a nickel alloy layer on the surface of a copper foil, or a composite foil having a zinc layer or a copper-zinc alloy layer on the surface of the copper foil is used. It is also possible.
- the lower electrode forming layer is made of copper or copper alloy (brass composition, Corson alloy composition, etc.). It is preferable to configure. This is because the material can be finely etched.
- nickel or a nickel alloy a nickel-phosphorus alloy composition
- the lower electrode forming layer is preferably composed of a nickel-cobalt alloy composition or the like.
- the phosphorus content may be in the range of 0.1 wt% to 11 wt%, more preferably the phosphorus content is in the range of 0.2 wt% to 3 wt%. preferable.
- the phosphorus content is less than 0.1 wt%, it becomes the same as when pure nickel is used, and the significance of alloying is lost.
- the phosphorus content exceeds 11 wt%, phosphorus is segregated at the interface with the oxide dielectric layer, the adhesiveness with the oxide dielectric layer is deteriorated, and peeling easily occurs.
- the phosphorus content in the present invention is a value converted as [P component weight] / [Ni component weight] ⁇ 100 (wt%).
- the average thickness of the lower electrode formation layer is preferably 1 ⁇ m to 100 ⁇ m. If the average thickness is less than 1 ⁇ m, the handling property as a capacitor forming material is lacking, the reliability as an electrode when the capacitor is formed is remarkably lacking, and an oxide dielectric layer having a uniform thickness is formed on the surface. Things become extremely difficult. On the other hand, there is almost no practical requirement for an average thickness exceeding 100 ⁇ m. In addition, when the average thickness of the lower electrode formation layer is set to 10 ⁇ m or less, if a metal foil is used, handling as a foil becomes difficult.
- a metal foil with a carrier foil in which the metal foil and the carrier foil are bonded to each other through a bonding interface as the metal foil constituting the capacitor forming material.
- the carrier foil in such a case may be removed at an arbitrary stage after being processed into the capacitor forming material referred to in the present invention.
- the oxide dielectric layer preferably employs a basic composition of (Ba 1-x Sr x ) TiO 3 (0 ⁇ x ⁇ 1). .
- the basic composition is referred to because it may contain additional components such as manganese and silicon described below.
- the method for forming the oxide dielectric layer is not particularly limited as long as a dielectric film having a basic composition of (Ba 1-x Sr x ) TiO 3 (0 ⁇ x ⁇ 1) can be manufactured. Therefore, various dielectric film manufacturing methods can be employed. For example, sol-gel method, electrophoretic electrodeposition method, chemical vapor phase reaction method such as CVD, vapor deposition method, sputtering method and the like can be used.
- the oxide dielectric layer preferably contains a total of 0.01 mol% to 5.00 mol% of one or more selected from manganese, silicon, nickel, aluminum, lanthanum, niobium, magnesium and tin.
- These additive components are segregated mainly at the grain boundaries constituting the oxide dielectric layer, and function to block the flow path of the leakage current, thus ensuring long-term use stability as a dielectric layer. Use from a viewpoint.
- These components may be used alone or in combination of two or more, but the content to be included in the oxide dielectric film is preferably 0.01 mol% to 5.00 mol%.
- the addition amount of the additive component contained in the oxide dielectric film is 0.25 mol% to 1.50 mol%. This is because the effect of blocking the leakage current of the oxide dielectric layer is further stabilized.
- the oxide dielectric layer is an oxide dielectric film having a perovskite structure, and the oxide component of the additive component is not included in principle in the oxide dielectric film.
- the oxide dielectric layer preferably has an average thickness of 20 nm to 2 ⁇ m, more preferably 20 nm to 1 ⁇ m.
- the average thickness of the oxide dielectric layer is less than 20 nm, the uniformity of the thickness of the formed oxide dielectric layer is impaired, and dielectric breakdown is likely to occur at an early stage. You can't get it.
- an average thickness of about 2 ⁇ m is considered as the practical upper limit.
- the upper electrode forming layer 2 of the capacitor forming material 1 for manufacturing a printed wiring board according to the present invention has a configuration in which a bulk metal layer 5, a dissimilar metal layer 7, and a metal-metal oxide mixed layer 6 are laminated. Also at this time, the metal-metal oxide mixed layer 6 comes into contact with the oxide dielectric layer 4. By providing this dissimilar metal layer 7, the adhesion is further improved.
- the concept of the bulk metal layer 5 and the metal-metal oxide mixed layer 6, the oxide dielectric layer 4 and the lower electrode formation layer 3 constituting the upper electrode formation layer 2 is the type Ia. Since it is the same as that of the form, description here is abbreviate
- the dissimilar metal layer 7 is preferably composed of any one of copper, nickel, a copper alloy, and a nickel alloy.
- the term “different metal layer” is used because it is composed of a metal component different from the above-described bulk metal layer.
- nickel is used as a constituent of the dissimilar metal layer
- copper is used as a constituent of the bulk metal layer. This is because the layer configuration is changed according to the use to secure a good forming ability of the capacitor, and a balance design of strength, heat dissipation performance, and electrical conductivity required for the capacitor becomes possible.
- This dissimilar metal layer may function as an anti-oxidation barrier layer of the metal-metal oxide mixed layer.
- the metal-metal oxide mixed layer is once exposed to the atmosphere.
- the composition ratio of the metal-metal oxide mixed layer changes.
- this change can be prevented if a different metal layer exists on the surface of the metal-metal oxide mixed layer.
- the metal component constituting the dissimilar metal layer is a metal component different from the bulk metal layer, but the same metal component as the metal component constituting the metal-metal oxide mixed layer. It is also possible to use. Therefore, specifically, it is possible to employ nickel for the dissimilar metal layer and employ a nickel-nickel oxide mixed layer as the metal-metal oxide mixed layer.
- the dissimilar metal layer has excellent adhesion to the above-described bulk metal and metal-metal oxide mixed layer.
- the heat resistance characteristics are improved by using a nickel-based material for the dissimilar metal layer, and the heat dissipation characteristics are improved by using a copper-based material for the dissimilar metal layer.
- the copper alloy is a copper-phosphorus alloy, a copper-zinc alloy, a copper-nickel-zinc alloy, a copper-palladium alloy, a copper-gold alloy, a copper-silver alloy, or the like.
- the nickel alloy is a nickel-phosphorus alloy, nickel-cobalt alloy, nickel-copper alloy, nickel-palladium alloy, nickel-silver alloy, nickel-cobalt-palladium alloy, or the like.
- the presence of the dissimilar metal layer 7 improves the moisture absorption resistance, chemical resistance, and heat resistance in the etching process when forming the capacitor circuit, and deteriorates the adhesion between the oxide dielectric layer and the upper electrode formation layer as a capacitor. Can be prevented. Moreover, even when used as a capacitor of a printed wiring board, since the deterioration of the adhesion between the oxide dielectric layer and the upper electrode formation layer is small, long-term stable use is possible. When the average thickness of the dissimilar metal layer 7 is less than 30 nm, it is not preferable because stabilization of adhesion between the oxide dielectric layer and the upper electrode forming layer cannot be promoted.
- the average thickness of the dissimilar metal layer 7 is preferably in the range of 30 nm to 600 nm.
- the dissimilar metal layer 7 described above is preferably manufactured by employing a wet manufacturing method such as an electrolysis method or an electroless method, a physical vapor deposition method such as a sputtering method usually referred to as a dry process, or an EB vapor deposition method. .
- Capacitor forming material manufacturing method As the manufacturing method of the capacitor forming material, any manufacturing method may be adopted as long as the layer configuration of the type I to type III capacitor forming material according to the present invention described above is obtained. I do not care.
- the type I capacitor forming material includes “formation of an oxide dielectric layer on the surface of the lower electrode formation layer”, “two-layer structure of bulk metal layer / metal-metal oxide mixed layer on the surface of the oxide dielectric layer or a bulk Manufacturing of a procedure of “a laminated body in which an upper electrode forming layer having a three-layer structure of metal layer / dissimilar metal layer / metal-metal oxide mixed layer is formed” and, if necessary, “annealing of the laminated body” Adopt the method.
- Type II capacitor forming materials are described as follows: “A metal-metal oxide mixed layer is provided on the surface of the bulk metal layer to form a two-layer structure, or a different metal layer / metal-metal oxide mixed layer is provided on the surface of the bulk metal layer. “A lower electrode forming layer having a layer structure”, “An oxide dielectric layer is formed on a metal-metal oxide mixed layer provided on a surface of a bulk metal layer of the lower electrode forming layer”, “A surface of the oxide dielectric layer And a manufacturing method having a procedure of “annealing the laminated body” is adopted as necessary.
- the type III capacitor forming material is “a metal-metal oxide mixed layer is provided on the surface of the bulk metal layer to form a two-layer structure, or a different metal layer / metal-metal oxide mixed layer is provided on the surface of the bulk metal layer.
- a lower electrode forming layer having a layer structure “An oxide dielectric layer is formed on a metal-metal oxide mixed layer provided on a surface of a bulk metal layer of the lower electrode forming layer”, “The oxide dielectric layer A laminated body in which a two-layer structure of bulk metal layer / metal-metal oxide mixed layer or a three-layer structure of bulk metal layer / different metal layer / metal-metal oxide mixed layer is formed on the surface of And a manufacturing method of a procedure “annealing of the laminate” is adopted as necessary.
- the process of steps (1) to (6) is basically adopted to manufacture a capacitor forming material.
- the method in which the step (5) is omitted is a method for producing a capacitor forming material of “type Ia form”, which is referred to as “type Ia form of production”.
- the “type Ib form” manufacturing method of the capacitor forming material includes all of the steps (1) to (6) and is referred to as “type Ib production form”.
- each process will be described, and “Type Ia manufacturing mode” and “Type Ib manufacturing mode” will be described simultaneously.
- a sol-gel solution for manufacturing an oxide dielectric film having a basic composition of (Ba 1-x Sr x ) TiO 3 (0 ⁇ x ⁇ 1) is prepared.
- a commercially available preparation agent may be used or it may be blended by itself.
- a (Ba 1-x Sr x ) TiO 3 (0 ⁇ x ⁇ 1) film may be obtained as the desired oxide dielectric film.
- the sol-gel solution is applied to the surface of the lower electrode formation layer (a metal foil having an average thickness of 1 ⁇ m to 100 ⁇ m of copper, nickel, copper alloy, or nickel alloy) and oxygen Drying is performed in a contained atmosphere under conditions of 120 ° C. to 250 ° C. ⁇ 30 seconds to 10 minutes, and pyrolysis is performed in a condition containing 270 ° C. to 430 ° C. ⁇ 5 minutes to 30 minutes in an atmosphere containing oxygen.
- the unit process is repeated a plurality of times to adjust the film thickness.
- the sol-gel solution is applied to the surface of the lower electrode forming layer, dried in an oxygen-containing atmosphere at 120 ° C. to 250 ° C. for 30 seconds to 10 minutes, and then in an oxygen-containing atmosphere.
- a series of steps of performing pyrolysis under conditions of 270 ° C. to 430 ° C. ⁇ 5 minutes to 30 minutes is defined as one unit step, and when repeating this one unit step a plurality of times, at least between one unit step and one unit step. It is also preferable to adjust the film thickness by providing at least one 550 ° C. to 900 ° C. ⁇ 2 to 60 minutes of inert gas replacement or pre-baking treatment in vacuum.
- This process is characterized in that a thermal decomposition temperature in a low temperature range of 270 ° C. to 430 ° C. is employed in order to prevent excessive oxidation of the lower electrode formation layer.
- a thermal decomposition temperature in a low temperature range of 270 ° C. to 430 ° C. is employed in order to prevent excessive oxidation of the lower electrode formation layer.
- one unit process is repeated six times, and if one pre-firing step ⁇ one unit process (second time) ⁇ 1 unit
- the process of the process (third time) ⁇ one unit process (fourth time) ⁇ one unit process (fifth time) ⁇ one unit process (sixth time) is adopted.
- the obtained oxide dielectric film is dense and has a small number of structural defects in the crystal grains. Therefore, the capacitor-forming material obtained through this coating process has a low leakage current and a high-capacity dielectric layer even when the upper electrode circuit is formed by a wet etching method. The capacitor provided is obtained.
- a firing process of 550 ° C. to 900 ° C. ⁇ 5 minutes to 60 minutes is performed, and an oxide dielectric layer having an average thickness of 20 nm to 1 ⁇ m is formed on the surface of the lower electrode formation layer Form.
- This firing step is a so-called main firing step, and a final oxide dielectric layer is obtained through this firing.
- the heating temperature at this time is 550 ° C. to 850 ° C. ⁇ 5 minutes to 60 minutes.
- this metal-metal oxide mixed layer forming step copper oxide, nickel oxide, copper alloy having an average thickness of 5 nm to 200 nm is formed on the surface of the oxide dielectric layer formed in the firing step by physical vapor deposition. A metal-metal oxide mixed layer containing either oxide or nickel alloy oxide is formed. A sputtering method is preferably used for forming the metal-metal oxide mixed layer at this time. This is because it is easy to form a thin and uniform thin film, and it is easy to adjust the ratio of metal to metal oxide by changing the composition of the sputtering target and the sputtering conditions (for example, adjusting the oxygen partial pressure in the sputtering atmosphere).
- the dissimilar metal layer forming step described here is a step used only in the type Ib manufacturing mode.
- a dissimilar metal layer of copper, nickel, copper alloy, or nickel alloy having an average thickness of 30 nm to 600 nm is formed on the surface of the metal-metal oxide mixed layer by physical vapor deposition.
- the bulk metal layer constituting the upper electrode forming layer is formed on the surface of the metal-metal oxide mixed layer in the case of the type Ia manufacturing mode, and the type Ib manufacturing mode.
- it is formed on the surface of the dissimilar metal layer as a metal layer of any one of copper, nickel, copper alloy and nickel alloy having an average thickness of 1 ⁇ m to 100 ⁇ m to obtain a capacitor forming material.
- a metal component different from the constituent components of the different metal layer is used for the bulk metal layer. It is preferable to use a sputtering method also for the formation of the bulk metal layer at this time. This is because the film thickness can be easily controlled and adhesion with a metal-metal oxide mixed layer or a dissimilar metal layer formed by a sputtering method can be easily obtained.
- the capacitor forming material according to the present invention manufactured as described above is preferably annealed at a temperature of 300 ° C. to 500 ° C. for 15 minutes to 100 minutes and used as a product.
- a temperature of 300 ° C. to 500 ° C. for 15 minutes to 100 minutes and used as a product.
- the annealing treatment it is possible to obtain the effect of suppressing the leakage current of the capacitor formed using the capacitor forming material and the effect of stabilizing the adhesion between the dielectric layer and the upper electrode forming layer.
- the temperature of the annealing treatment is in the range of 300 ° C. to 500 ° C.
- the adhesion stabilizing effect can be achieved without increasing the dielectric loss (tan ⁇ ) within the annealing time range that can be adopted industrially. It can be obtained stably.
- an inert gas atmosphere is preferably used for the annealing treatment at this time.
- a capacitor forming material comprising an upper electrode forming layer (bulk metal layer / different metal layer / metal-metal oxide mixed layer) / oxide dielectric layer / lower electrode forming layer corresponding to Example 1 described later is used.
- Table 2 shows the results of measuring the leakage currents when annealing is performed and when annealing is not performed. And the formation method of a capacitor circuit is the same method as Example 1 mentioned later. Here, an annealing time of 350 ° C. ⁇ 90 minutes was employed. The leakage current was measured using a digital electrometer manufactured by Advantest Corporation.
- the printed wiring board provided with the capacitor according to the present invention is obtained by using the capacitor forming material described above. That is, the above-described capacitor forming material according to the present invention can be suitably used for forming a built-in capacitor layer of a multilayer printed wiring board.
- the upper electrode forming layer and the lower electrode forming layer on both surfaces of the capacitor forming material are formed into a capacitor circuit shape by an etching method, and this is used as an inner layer capacitor layer constituting material of the multilayer printed wiring board. There is no limitation on the method of manufacturing the multilayer printed wiring board at this time.
- the plate-like capacitor forming material according to the present invention can be used by being sized into an as-is size or an arbitrary size and embedded in a printed wiring board.
- any cutting method may be used as long as the upper electrode forming layer and the lower electrode forming layer existing on both sides of the oxide dielectric layer are in contact with each other at the cutting end portion and are not electrically conductive. May be adopted.
- the upper electrode formation layer and the lower electrode formation layer can be etched into a lattice pattern by etching, and then divided by an exposed oxide dielectric layer to be fragmented, using a laser cutting method, a wire method, a shear cutting method, etc. It becomes possible.
- the capacitor circuit included in the inner layer capacitor layer constituent material obtained in this way, and the fragmented capacitor embedded in the wiring of the printed wiring board, the electrode layer includes the above-described two-layer or three-layer composite layer. Excellent adhesion between the layer and the oxide dielectric layer.
- Example 1 the oxide dielectric film is formed on the surface of a nickel foil that is a base metal (lower electrode forming layer), and the metal-metal oxide mixed layer and the heterogeneous layer are further formed on the surface of the oxide dielectric film.
- a metal layer was formed, a bulk metal layer was sequentially formed, and a capacitor forming material was manufactured as an upper electrode forming layer. And using this capacitor formation material, the capacitor circuit was formed by the etching method, and various dielectric properties were evaluated.
- a sol-gel solution used for the sol-gel method was prepared. Here, it was prepared so as to obtain an oxide dielectric film having a composition of Ba 0.9 Sr 0.1 TiO 3 using a trade name BST thin film forming agent 7 wt% BST manufactured by Mitsubishi Materials Corporation.
- the sol-gel solution is applied to the surface of the metal substrate, dried in an oxygen-containing atmosphere at 150 ° C. for 2 minutes, and 390 ° C. for 15 minutes in an oxygen-containing atmosphere.
- a series of steps for performing thermal decomposition under the conditions was defined as one unit step. Then, in repeating this one unit process 12 times, after the first unit process of the first time, the third unit process of the third time, the first unit process of the sixth time, and the first unit process of the ninth time, one 700 step is performed. The film thickness was adjusted by providing a pre-baking treatment with inert gas replacement at 15 ° C. for 15 minutes.
- firing treatment is performed in an inert gas substitution atmosphere (nitrogen substitution atmosphere) at 850 ° C. for 30 minutes to form a lower electrode formation layer (nickel foil). An oxide dielectric layer was formed on the surface.
- a copper layer having an average thickness of 2 ⁇ m was formed as a bulk metal layer by sputtering.
- a copper target was placed in the vacuum chamber.
- a capacitor forming material was obtained as an upper electrode forming layer having a three-layer structure of metal-metal oxide mixed layer / dissimilar metal layer / bulk metal layer.
- XPS measurement and XRD measurement As shown in FIG. 8 (layer configuration of Example 1 corresponding to the type Ib form), the XPS spectrum and the XRD spectrum are the dielectric layer 4 and the metal-metal oxide mixed layer 6. And XPS measurement and XRD measurement were performed on the metal-metal oxide mixed layer 6 side.
- the XPS apparatus includes ULVAC. QUANTUM 2000 manufactured by Phi Co., Ltd. was used. And X'Pert Pro made from Panalical was used for the XRD apparatus at this time. These measurement results are all shown in Table 3.
- etching resist layer was provided on the surface of the upper electrode forming layer of each capacitor forming material, and an etching pattern for forming an upper electrode circuit shape was exposed and developed. Thereafter, the upper electrode formation layer was etched with an etchant, and the etching resist was peeled off to form a capacitor circuit having an upper electrode circuit area of 4 mm ⁇ 4 mm size.
- Electric capacity density When the upper electrode circuit area was 4 mm ⁇ 4 mm, the initial average capacity density was as high as 1214 nF / cm 2 . In addition, the electric capacity density of an Example and the comparative example mentioned later is shown as an average value which measured with 30 electrodes.
- Dielectric loss The dielectric loss of the capacitor circuit when the area of the upper electrode circuit was 4 mm ⁇ 4 mm was measured and found to be 0.041. In addition, the dielectric loss of an Example and the comparative example mentioned later is shown as an average value which measured with three samples.
- Leakage current The leakage current was measured using a digital electrometer manufactured by Advantest Co., Ltd., using a capacitor circuit when the upper electrode circuit area was 4 mm ⁇ 4 mm size.
- Adhesion Copper plating is performed on the upper electrode forming layer of the obtained capacitor forming material, plating is performed to an average thickness of 22 ⁇ m, and a 30 mm wide linear peel strength measuring circuit is formed to form the upper electrode. Measured as the peel strength between the forming layer and the dielectric layer.
- the copper plating performed here is performed for convenience of measurement, and it is clearly stated that it has nothing to do with the configuration of the present invention. As a result, it was 0.373 kgf / cm.
- the peeling strength of an Example and the comparative example mentioned later is shown as an average value which measured with three samples. In this case, the peel strength was measured using an autograph (AGS-1kNG) manufactured by Shimadzu Corporation under the condition of a peel rate of 50 mm / min. *
- Example 2 the same process as in Example 1 was adopted to obtain a capacitor forming material, and the same evaluation was performed. The only difference is that the nickel-nickel oxide mixed layer has an average thickness of 50 nm. Each characteristic of this sample is listed in Table 3 so that it can be compared with Example 1 and a comparative example described later.
- Example 3 the same process as in Example 1 was adopted, a capacitor forming material was obtained, and then an annealing treatment was performed, and the same evaluation was performed. Therefore, the only difference is the presence or absence of annealing treatment.
- the capacitor forming material manufactured in Example 1 was subjected to a heat treatment for 90 minutes in a nitrogen stream atmosphere at a temperature of 350 ° C.
- Table 3 Each characteristic of this sample is listed in Table 3 so that it can be compared with Example 1, Example 2, and a comparative example described later.
- Comparative Example 1 In Comparative Example 1, the step (4) of Example 1 was omitted, and a metal layer (nickel layer) having an average thickness of 600 nm was formed only in the step (5). Therefore, the peak intensity ratio corresponds to infinity ( ⁇ ). Other processes were performed in the same manner as in the example to obtain a capacitor forming material.
- the average capacity density was 1127 nF / cm 2
- the dielectric loss was 0.023
- the peel strength was 0.004 kgf / cm.
- Comparative Example 2 is a metal-metal oxide in which the oxygen gas inflow rate in step (4) of Example 1 is 2.5 cc / min and the oxygen partial pressure is 1.8 ⁇ 10 ⁇ 4 Torr. An attempt was made to form a mixed layer. However, when the mixed metal-metal oxide layer is analyzed by X-ray diffraction, the peak of nickel oxide is negligible, and the intentionally formed nickel oxide is not formed. Think of it as a nickel layer. Therefore, in the comparison with the following examples, it is handled in the same manner as in Comparative Example 1. Other processes were performed in the same manner as in the example to obtain a capacitor forming material.
- the average capacity density was 1158 nF / cm 2
- the dielectric loss was 0.021
- the peel strength was 0.010 kgf / cm.
- the average capacity density was 347 nF / cm 2
- the dielectric loss was 0.143
- the peel strength was 0.263 kgf / cm.
- Comparative Example 4 In Comparative Example 4, the sample after firing in Step (4) of Example 1 was placed in a vacuum chamber of a sputtering apparatus in which a copper target was placed, and oxygen gas was supplied into the vacuum chamber at 10.0 cc / min. The flow rate was set to a steady state with an oxygen partial pressure of 6.8 ⁇ 10 ⁇ 4 Torr. Thereafter, a copper oxide layer having an average thickness of 100 nm was formed by sputtering. Then, the flow of oxygen gas into the vacuum chamber of the sputtering method apparatus was stopped, and it was waited for most of the oxygen to be deaerated.
- the average capacity density was 947 nF / cm 2
- the dielectric loss was 0.028
- the peel strength was 0.005 kgf / cm.
- Comparative Example 1 and Comparative Example 2 have extremely low peel strength (adhesiveness) between the upper electrode formation layer and the dielectric layer. Therefore, after processing into a capacitor circuit, peeling of the upper electrode circuit due to vibration, peeling of the upper electrode circuit due to impact during handling, and expansion behavior of the printed wiring board due to heat generation during use as a printed wiring board The risk of causing peeling of the upper electrode circuit due to is increased.
- Comparative Example 4 As is clear from the contents of Comparative Example 4 in Table 3, when the layer is made of only copper oxide instead of the metal-metal oxide mixed layer, the peel strength between the upper electrode forming layer and the dielectric layer ( Adhesion) is extremely low. In addition, the capacity density of the capacitor circuit is reduced.
- the average capacitance density (Cp) is large, the dielectric loss (tan ⁇ ) is also relatively small, and the peel strength between the upper electrode formation layer and the dielectric layer is The value of (Adhesion) is also high at 0.314 kgf / cm to 0.544 kgf / cm. That is, it can be said that the capacitor forming material according to the present invention is excellent in total balance. And a printed wiring board provided with a capacitor circuit obtained by using this capacitor forming material has high-quality capacitor characteristics and is excellent in long-term use stability.
- the capacitor forming material according to the present invention is either a metal-metal oxide mixed layer or a metal-metal oxide mixed layer / different metal layer between the oxide dielectric layer and the bulk metal layer constituting the electrode forming layer. It is characterized by having the layer structure of By having such a layer structure, the adhesion between the electrode forming layer and the oxide dielectric layer is increased. Therefore, when a printed wiring board including a capacitor is manufactured using the capacitor forming material for manufacturing a printed wiring board according to the present invention, it is possible to supply the market as a long-life product having high-quality capacitor characteristics.
- the production does not require a special device, and it is possible to use existing equipment and to make a large capital investment. I don't need it. Good adhesion is exhibited between the oxide dielectric layer and the upper electrode formation layer, and a high-quality product is obtained in a state where a high electric capacity is ensured.
- Capacitor forming material (Type Ia) 1b Capacitor forming material (Type Ib) 10a Capacitor forming material (Type II-a) 10b Capacitor forming material (Type II-b) 20a Capacitor forming material (Type III-a) 20b Capacitor forming material (Type III-b) 2 Upper electrode forming layer 3 Lower electrode forming layer 4 Oxide dielectric layer 5 Bulk metal layer 6 Metal-metal oxide mixed layer 7 Dissimilar metal layer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
当該下部電極形成層の表面にある金属-金属酸化物混合層の上に酸化物誘電層を形成し、更に、当該酸化物誘電層の表面に上部電極形成層を形成した積層体とすることを特徴とする製造方法を採用する。このタイプIIの製造方法で言う積層体は、(「上部電極形成層/誘電層/下部電極形成層(金属-金属酸化物混合層/バルク金属層)」又は「上部電極形成層/誘電層/下部電極形成層(金属-金属酸化物混合層/異種金属層/バルク金属層)」)の層構成を備えるものである。なお、タイプIIにおける上部電極形成層は、意図的に金属酸化物を含ませていない金属からなる層である。
本件発明に係るプリント配線板製造用のキャパシタ形成材1は、上部電極形成層2と下部電極形成層3との間に酸化物誘電層4を備えるキャパシタ形成材において、当該上部電極形成層2及び下部電極形成層3の少なくとも一方は、バルク金属層5/当該酸化物誘電層と接する金属-金属酸化物混合層6の2層構造を備えることを特徴とする。従って、3タイプの層構成を備える。以下、タイプI~タイプIIIのそれぞれを図面を用いて説明する。なお、各タイプの中には、異種金属層を含まないa型と異種金属層を含むb型とが存在する。よって、タイプI-a、タイプI-bのようにして分別する。
本件発明に係るキャパシタを備えたプリント配線板は、以上に述べてきたキャパシタ形成材を用いて得られたことを特徴とする。即ち、上述の本件発明に係るキャパシタ形成材は、多層プリント配線板の内蔵キャパシタ層の形成に好適に用いることが出来る。当該キャパシタ形成材の両面にある上部電極形成層と下部電極形成層とをエッチング法でキャパシタ回路形状とし、これを多層プリント配線板の内層キャパシタ層構成材料として用いる。このときの多層プリント配線板の製造方法に関しては、何ら限定はない。
ここでは、圧延法で製造した平均厚さ50μmのニッケル箔を使用した。なお、圧延法で製造したニッケル箔の平均厚さは、ゲージ厚さとして示したものである。キャパシタ形成材となったとき、このニッケル箔の層が下部電極回路の形成に用いられる。
(1) この溶液調製工程では、ゾル-ゲル法に用いるゾル-ゲル溶液を調製した。ここでは、三菱マテリアル株式会社製の商品名 BST薄膜形成剤 7wt%BSTを用いて、Ba0.9Sr0.1TiO3の組成の酸化物誘電膜を得られるように調製した。
前記各キャパシタ形成材の上部電極形成層の表面にエッチングレジスト層を設け、上部電極回路形状を形成するための、エッチングパターンを露光し、現像した。その後、エッチング液で上部電極形成層をエッチング加工して、エッチングレジスト剥離を行うことで、上部電極回路面積が4mm×4mmサイズのキャパシタ回路を形成した。
電気容量密度: 上部電極回路面積が4mm×4mmサイズとした場合の初期の平均容量密度は1214nF/cm2と高い電気容量を示した。なお、実施例及び後述する比較例の電気容量密度は、30個の電極で測定を行った平均値として示している。
この比較例1では、実施例1の工程(4)を省略し、工程(5)のみで平均厚さ600nmの金属層(ニッケル層)を形成した。従って、ピーク強度比は、無限大(∞)に相当する。その他の工程は、実施例と同様にして、キャパシタ形成材を得た。
この比較例2は、実施例1の工程(4)での酸素ガスの流入量を2.5cc/minとして、酸素分圧が1.8×10-4Torrの状態として、金属-金属酸化物混合層の形成を試みた。しかし、このときの金属-金属酸化物混合層をX線回折法で分析すると、酸化ニッケルのピークは極僅かであり、意図的に生成した酸化ニッケルの形成は出来ていない状態であり、通常のニッケル層と考えて差し支えのないものである。従って、以下の実施例との対比においては、比較例1と同様と考えて取り扱う。その他の工程は、実施例と同様にして、キャパシタ形成材を得た。
この比較例3は、実施例1の工程(4)での酸素ガスの流入量を10.0cc/minとして、酸素分圧が6.8×10-4Torrの状態として、金属酸化物のみで構成した金属酸化物層のみで、平均厚さ100nmの酸化ニッケル層を形成した。このときの金属酸化物層をX線回折法で分析すると、未酸化のニッケルは殆ど見られず、酸化ニッケルのピークのみと考えて差し支えのないものである。従って、[Ni(101)]=0と考え、ピーク強度比は無限小(≒0)に相当する。その他の工程は、実施例と同様にして、キャパシタ形成材を得た。
この比較例4は、実施例1の工程(4)で、焼成後の試料を、銅ターゲットを配置したスパッタリング装置の真空チャンバー内に入れ、当該真空チャンバー内に、酸素ガスを10.0cc/minのフロー速度で流入し、酸素分圧が6.8×10-4Torrの定常状態とした。その後、スパッタリング法により、平均厚さ100nmの酸化銅層を形成した。そして、スパッタリング法装置の真空チャンバー内への酸素ガスの流入を止め、酸素の殆どが脱気するのを待った。そして、酸素の脱気が完了した後に、再びスパッタリング法を用いて、金属酸化物層上に、平均厚さ2μmの銅層をバルク金属層として形成した。このときの酸化銅層をX線回折法で分析すると、未酸化の銅は殆ど見られず、酸化銅のピークのみと考えて差し支えのないものである。従って、[Cu(200)]=0と考え、実施例のピーク強度比に相当する([Cu(200)]/[Cu2O(111)])≒0の銅-酸化銅混合層(金属-金属酸化物混合層)を形成した。 その他の工程は、実施例と同様にして、キャパシタ形成材を得た。なお、CuはPDFカード#04-0836、Cu2OはPDFカード#05-0667を参照している。
表3の比較例1及び比較例2の掲載内容から明らかなように、金属-金属酸化物混合層ではなく金属ニッケルになると、平均容量密度(Cp)は大きく、誘電損失(tanδ)も小さく、一見すれば良好なキャパシタ特性を備えるように見える。ところが、比較例1及び比較例2は、上部電極形成層と誘電層との間での引き剥がし強さ(密着性)の値が、極端に低くなっている。したがって、キャパシタ回路に加工して以降の、振動による上部電極回路の剥離、ハンドリング時の衝撃による上部電極回路の剥離、プリント配線板として使用している途中での発熱現象によるプリント配線板の膨張挙動による上部電極回路の剥離等を起こす危険性が高くなる。
1b キャパシタ形成材(タイプI-b)
10a キャパシタ形成材(タイプII-a)
10b キャパシタ形成材(タイプII-b)
20a キャパシタ形成材(タイプIII-a)
20b キャパシタ形成材(タイプIII-b)
2 上部電極形成層
3 下部電極形成層
4 酸化物誘電層
5 バルク金属層
6 金属-金属酸化物混合層
7 異種金属層
Claims (20)
- 上部電極形成層と下部電極形成層との間に酸化物誘電層を備えるキャパシタ形成材において、
当該上部電極形成層及び下部電極形成層の少なくとも一方は、バルク金属層と、当該酸化物誘電層と接する金属-金属酸化物混合層との2層構造を備えることを特徴とするキャパシタ形成材。 - 前記上部電極形成層は、バルク金属層と金属-金属酸化物混合層との2層構造を備え、
当該金属-金属酸化物混合層と当該酸化物誘電層とが接するように積層配置した層構成を備えることを特徴とする請求項1に記載のキャパシタ形成材。 - 前記金属-金属酸化物混合層をX線光電子分光分析で測定した際に、当該金属-金属酸化物混合層を構成する金属スペクトルと金属酸化物スペクトルとが分離して確認可能である請求項1に記載のキャパシタ形成材。
- 前記金属-金属酸化物混合層を構成する金属酸化物は、銅酸化物、ニッケル酸化物、銅合金酸化物、ニッケル合金酸化物のいずれかである請求項1に記載のキャパシタ形成材。
- 前記金属-金属酸化物混合層が、ニッケルとニッケル酸化物との混合組成である場合において、
X線回折法で測定したニッケルの(101)面のピーク強度(Ni(101))と、酸化ニッケルの(200)面のピーク強度(NiO(200))とのピーク強度比([Ni(101)]/[NiO(200)])が、0.02~50の範囲にある請求項1に記載のキャパシタ形成材。 - 前記金属-金属酸化物混合層は、平均厚さ5nm~200nmである請求項1に記載のキャパシタ形成材。
- 前記上部電極形成層及び下部電極形成層を構成するバルク金属層は、銅、ニッケル、銅合金、ニッケル合金のいずれかで構成したものである請求項1に記載のキャパシタ形成材。
- 前記上部電極形成層と下部電極形成層との少なくとも一方において、
当該バルク金属層と金属-金属酸化物混合層との間に、異種金属層を備える3層構造を備えるものである請求項1に記載のキャパシタ形成材。 - 前記異種金属層は、バルク金属層と異なる金属成分であって、金属-金属酸化物混合層に含まれる金属成分で構成したものである請求項8に記載のキャパシタ形成材。
- 前記異種金属層は、平均厚さ30nm~600nmである請求項8に記載のキャパシタ形成材。
- 前記酸化物誘電層は、(Ba1-x Srx)TiO3(0≦x≦1)の基本組成を備えるものである請求項1に記載のキャパシタ形成材。
- 前記酸化物誘電層は、平均厚さが20nm~2μmである請求項1に記載のキャパシタ形成材。
- 請求項1に記載のキャパシタ形成材の製造方法であって、
下部電極形成層の表面に酸化物誘電層を形成し、
当該酸化物誘電層の表面に、バルク金属層/金属-金属酸化物混合層の2層構造又はバルク金属層/異種金属層/金属-金属酸化物混合層の3層構造の上部電極形成層を形成した積層体とすることを特徴としたキャパシタ形成材の製造方法。 - 前記積層体にアニール処理を施すものである請求項13に記載のキャパシタ形成材の製造方法。
- 請求項1に記載のキャパシタ形成材の製造方法であって、
バルク金属層表面へ金属-金属酸化物混合層を設けて2層構造、又は、バルク金属層表面へ異種金属層/金属-金属酸化物混合層を設けて3層構造の下部電極形成層とした後に、
当該下部電極形成層の表面にある金属-金属酸化物混合層の上に酸化物誘電層を形成し、
更に、当該酸化物誘電層の表面に上部電極形成層を形成した積層体とすることを特徴としたキャパシタ形成材の製造方法。 - 前記積層体にアニール処理を施すものである請求項15に記載のキャパシタ形成材の製造方法。
- 請求項1に記載のキャパシタ形成材の製造方法であって、
バルク金属層表面へ金属-金属酸化物混合層を設けて2層構造、又は、バルク金属層表面へ異種金属層/金属-金属酸化物混合層を設けて3層構造の下部電極形成層とした後に、
当該下部電極形成層の表面にある金属-金属酸化物混合層の上に酸化物誘電層を形成し、
当該酸化物誘電層の表面に、バルク金属層/金属-金属酸化物混合層の2層構造又はバルク金属層/異種金属層/金属-金属酸化物混合層の3層構造の上部電極形成層を形成した積層体とすることを特徴としたキャパシタ形成材の製造方法。 - 前記積層体にアニール処理を施すものである請求項17に記載のキャパシタ形成材の製造方法。
- 請求項1に記載のキャパシタ形成材を用いて内層キャパシタ層を形成して得られることを特徴とするプリント配線板。
- 請求項1に記載のキャパシタ形成材をプリント配線板内に配して得られることを特徴とするプリント配線板。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/933,261 US20110005817A1 (en) | 2008-03-31 | 2009-02-04 | Capacitor-forming material and printed wiring board provided with capacitor |
CN200980111865.2A CN101983408B (zh) | 2008-03-31 | 2009-02-04 | 电容器形成材料和带有电容器的印刷电路板 |
JP2010505425A JPWO2009122774A1 (ja) | 2008-03-31 | 2009-02-04 | キャパシタ形成材及びキャパシタを備えたプリント配線板 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008093057 | 2008-03-31 | ||
JP2008-093057 | 2008-03-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009122774A1 true WO2009122774A1 (ja) | 2009-10-08 |
Family
ID=41135173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/051905 WO2009122774A1 (ja) | 2008-03-31 | 2009-02-04 | キャパシタ形成材及びキャパシタを備えたプリント配線板 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20110005817A1 (ja) |
JP (1) | JPWO2009122774A1 (ja) |
KR (1) | KR20100123886A (ja) |
CN (1) | CN101983408B (ja) |
TW (1) | TW200949873A (ja) |
WO (1) | WO2009122774A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010095295A1 (ja) | 2009-02-20 | 2010-08-26 | 株式会社村田製作所 | 抵抗記憶素子およびその使用方法 |
WO2010095296A1 (ja) * | 2009-02-20 | 2010-08-26 | 株式会社村田製作所 | 抵抗記憶素子およびその使用方法 |
WO2014088691A1 (en) * | 2012-12-03 | 2014-06-12 | Advanced Technology Materials Inc. | IN-SITU OXIDIZED NiO AS ELECTRODE SURFACE FOR HIGH k MIM DEVICE |
US20150269314A1 (en) | 2014-03-20 | 2015-09-24 | Rudjer Boskovic Institute | Method and apparatus for unsupervised segmentation of microscopic color image of unstained specimen and digital staining of segmented histological structures |
CN103971933B (zh) * | 2014-05-12 | 2017-02-15 | 同济大学 | 一种固态薄膜电容器及其制备方法 |
KR102584993B1 (ko) * | 2018-02-08 | 2023-10-05 | 삼성전기주식회사 | 커패시터 부품 및 그 제조방법 |
JP7056290B2 (ja) * | 2018-03-23 | 2022-04-19 | Tdk株式会社 | 薄膜キャパシタ、及び薄膜キャパシタの製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0745475A (ja) * | 1993-06-29 | 1995-02-14 | Hitachi Ltd | 薄膜コンデンサ及びその製造方法 |
JPH11243032A (ja) * | 1998-02-25 | 1999-09-07 | Kyocera Corp | 薄膜コンデンサ |
JP2001185443A (ja) * | 1999-12-22 | 2001-07-06 | Hitachi Ltd | 薄膜コンデンサ |
JP2007150207A (ja) * | 2005-11-30 | 2007-06-14 | Tdk Corp | 誘電体素子とその製造方法 |
JP2007329189A (ja) * | 2006-06-06 | 2007-12-20 | Tdk Corp | 薄膜コンデンサ及びその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3764160B2 (ja) * | 2004-09-10 | 2006-04-05 | 三井金属鉱業株式会社 | キャパシタ層形成材及びキャパシタ層形成材を用いて得られる内蔵キャパシタ回路を備えるプリント配線板。 |
US7192654B2 (en) * | 2005-02-22 | 2007-03-20 | Oak-Mitsui Inc. | Multilayered construction for resistor and capacitor formation |
US8223966B2 (en) * | 2006-05-10 | 2012-07-17 | Mediatek Inc. | Multiple stream decrypting and decoding systems and related methods thereof |
US8557352B2 (en) * | 2006-06-20 | 2013-10-15 | Tdk Corporation | Method of making a metal oxide film, laminates and electronic devices |
US7605048B2 (en) * | 2007-04-06 | 2009-10-20 | Kemet Electronics Corporation | Method for forming a capacitor having a copper electrode and a high surface area aluminum inner layer |
-
2009
- 2009-02-04 WO PCT/JP2009/051905 patent/WO2009122774A1/ja active Application Filing
- 2009-02-04 KR KR1020107021592A patent/KR20100123886A/ko active IP Right Grant
- 2009-02-04 US US12/933,261 patent/US20110005817A1/en not_active Abandoned
- 2009-02-04 JP JP2010505425A patent/JPWO2009122774A1/ja active Pending
- 2009-02-04 CN CN200980111865.2A patent/CN101983408B/zh not_active Expired - Fee Related
- 2009-02-10 TW TW098104134A patent/TW200949873A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0745475A (ja) * | 1993-06-29 | 1995-02-14 | Hitachi Ltd | 薄膜コンデンサ及びその製造方法 |
JPH11243032A (ja) * | 1998-02-25 | 1999-09-07 | Kyocera Corp | 薄膜コンデンサ |
JP2001185443A (ja) * | 1999-12-22 | 2001-07-06 | Hitachi Ltd | 薄膜コンデンサ |
JP2007150207A (ja) * | 2005-11-30 | 2007-06-14 | Tdk Corp | 誘電体素子とその製造方法 |
JP2007329189A (ja) * | 2006-06-06 | 2007-12-20 | Tdk Corp | 薄膜コンデンサ及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101983408A (zh) | 2011-03-02 |
KR20100123886A (ko) | 2010-11-25 |
JPWO2009122774A1 (ja) | 2011-07-28 |
CN101983408B (zh) | 2012-11-14 |
US20110005817A1 (en) | 2011-01-13 |
TW200949873A (en) | 2009-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2009122774A1 (ja) | キャパシタ形成材及びキャパシタを備えたプリント配線板 | |
US6493207B2 (en) | Multilayer ceramic capacitor | |
JP5158061B2 (ja) | 薄膜コンデンサ | |
US11715593B2 (en) | Multi-layer ceramic capacitor | |
JP6020503B2 (ja) | 積層セラミック電子部品 | |
JP5267251B2 (ja) | 薄膜コンデンサ、及び薄膜コンデンサの製造方法 | |
JP6020502B2 (ja) | 積層セラミック電子部品 | |
WO2009125620A1 (ja) | コンデンサおよびその製造方法 | |
JP2006196848A (ja) | キャパシタ層形成材及びそのキャパシタ層形成材の製造方法並びにそのキャパシタ層形成材を用いて得られる内蔵キャパシタ層を備えたプリント配線板 | |
JP2007194592A (ja) | 誘電体素子とその製造方法 | |
WO2006118236A1 (ja) | 酸化物誘電層の形成方法及びその形成方法で得られた酸化物誘電層を備えたキャパシタ層形成材 | |
JP4665866B2 (ja) | バルブ金属複合電極箔の製造方法 | |
JP3958343B2 (ja) | 酸化物誘電層の形成方法及びその形成方法で得られた酸化物誘電層を備えたキャパシタ層形成材 | |
JP7070947B2 (ja) | 配線基板及びその製造方法、並びに電子部品及びその製造方法 | |
JP4765321B2 (ja) | 導電性ペースト | |
JP2008166470A (ja) | 電子部品及びその製造方法 | |
JP4211783B2 (ja) | 導電性ペーストおよび積層セラミック電子部品 | |
JP4665854B2 (ja) | バルブ金属複合電極箔およびその製造方法 | |
JP2008252019A (ja) | 薄膜キャパシタの製造方法 | |
JP2006332572A (ja) | 積層セラミックコンデンサの製法および積層セラミックコンデンサ | |
JPH0696988A (ja) | 積層セラミックコンデンサー内部電極用ペースト及び該ペーストを用いた積層セラミックコンデンサー | |
JPWO2007029789A1 (ja) | プリント配線板の内蔵キャパシタ回路に適したpzt系誘電層の形成方法 | |
TWI387421B (zh) | A multilayer printed circuit board capacitor layer forming material, and a capacitor layer forming material | |
JP2008135478A (ja) | 端子電極形成方法及び電子部品の製造方法 | |
JP2019091749A (ja) | コンデンサ、及び該コンデンサの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980111865.2 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09728782 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010505425 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12933261 Country of ref document: US |
|
ENP | Entry into the national phase |
Ref document number: 20107021592 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09728782 Country of ref document: EP Kind code of ref document: A1 |