Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/14—Error detection or correction of the data by redundancy in operation
  • G06F11/1402—Saving, restoring, recovering or retrying
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/16—Protection against loss of memory contents
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
  • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Definitions

• the present invention relates to a semiconductor storage device.
• the present invention relates to a semiconductor storage device that includes, for example, an NAND flash memory.
• An NAND flash memory is a non-volatile memory that can retain information even when power supply is stopped.
• the NAND flash memory is widely popular because it has better per-bit cost than other types of non-volatile memory.
• influence of aged deterioration in written data and read-disturb have been becoming actualized in the NAND flash memory.
• the read-disturb refers to data corruption accompanying a reading process.
• the aged deterioration is a phenomenon in which a floating gate that accumulates electric charge gradually loses electric charge with time progress, thereby causing data error.
• the read-disturb is a phenomenon in which an error occurs in stored data, because a minute amount of electric charge is accumulated in a floating gate of the memory cell adjacent to a memory cell from which data is read out.
• NAND flash memory is performed after stored data is read out and error correction is performed.
• a method of extending the data retaining period for data stored in the NAND flash memory by a refresh operation as mentioned above, for example, a method can be considered in which a number of times data is read out from the NAND flash memory and the like is counted. Then a refresh operation is performed when the number of times of readout reaches a specified number. Alternatively, a method can be considered in which a refresh operation is performed when an error count ( the number of errors) increases (refer to, for example, Patent
• the NAND flash memory is a device such that the number of rewriting is limited, life of the NAND flash memory is shortened by the refresh operation being needlessly performed.
• Patent Document 1 Japanese Patent Application Laid-open No. 2004-326867
• the present invention provides a semiconductor storage device that can efficiently perform a refresh operation.
• a semiconductor storage device comprising: a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing; and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
• Fig. 1 is a block diagram of an overall configuration of a semiconductor storage device according to a first embodiment of the present invention
• Fig. 2 is a diagram explaining a configuration of a first management table in the semiconductor storage device according to the first embodiment
• Fig. 3 is a flowchart of a monitored block selecting process performed in the semiconductor storage device according to the first embodiment
• Fig. 4 is a flowchart of a monitored block registering process for registering a monitored block to the first management table in the semiconductor storage device according to the first embodiment
• Fig. 5 is a flowchart of a registering process for registering a block to the first management table in the semiconductor storage device according to the first embodiment
• Fig. 6 is a flowchart of an error count monitoring process performed on a block registered to the first management table in the semiconductor storage device according to the first embodiment
• Fig. 7 is a flowchart of a deleting process for deleting a block on which a refresh operation has been performed from the first management table in the semiconductor storage device according to the first embodiment
• Fig. 8 is a diagram explaining a configuration of a second management table in the semiconductor storage device according to the first embodiment
• Fig. 9 is a flowchart of a monitored block selecting process performed in the semiconductor storage device according to the first embodiment
• Fig. 10 is a diagram explaining a configuration of a third management table in the semiconductor storage device according to the first embodiment
• Fig. 11 is a flowchart of a monitored block selecting process performed in the semiconductor storage device according to the first embodiment
• Fig . 12 is a diagram explaining a configuration of a fourth management table in the semiconductor storage device according to the first embodiment
• Fig. 13 is a flowchart of a monitored block selecting process performed in the semiconductor storage device according to the first embodiment
• Fig. 14 is a diagram explaining a configuration of a fifth management table in the semiconductor storage device according to the first embodiment
• Fig. 15 is a flowchart of a registering process for registering a block to the first management table in the semiconductor storage device according to the first embodiment
• Fig. 16 is a diagram explaining a configuration of a sixth management table in the semiconductor storage device according to the first embodiment
• Fig. 17 is a flowchart of a deleting process for deleting a block excluded from error count monitoring from a first management table of a semiconductor storage device according to a sixth embodiment
• Fig. 18 is a diagram explaining a configuration of a seventh management table in the semiconductor storage device according to the first embodiment
• Fig. 19 is a flowchart of an error count monitoring process performed on a monitored block registered to a first management table in a semiconductor storage device according to a seventh embodiment ;
• Fig. 20 is a block diagram of a configuration of an SSD in an example of the present invention.
• Fig. 21 is a block diagram of a configuration of a drive controlling circuit in the example.
• Fig. 22 is a block diagram of a configuration of a processor in the example of the present invention.
• Fig. 23 is a perspective view of an example of a portable computer on which the SSD is mounted in the example
• Fig. 24 is a diagram of an example of a system configuration of the portable computer on which the SSD is mounted in the example of the present invention.
• FIG. 1 is a block diagram of an overall configuration of a semiconductor storage device 1 according to a first embodiment.
• the semiconductor storage device 1 shown in Fig. 1 is an embodiment of the present invention. The present invention is not limited to the configuration.
• the semiconductor storage device 1 according to the first embodiment includes a controlling unit 3 and an NAND flash memory 10.
• the controlling unit 3 includes a central processing unit (CPU) 4, a random access memory (RAM) 5, a host interface
• the CPU 4 runs programs.
• the RAM 5 stores therein data, programs, and the like.
• the host I/F 6 communicates with a host device 2 connected to the semiconductor storage device 1.
• the NAND I/F 8 controls data transfer performed between the controlling unit 3 and the NAND flash memory 10.
• the bus 9 connects the CPU 4, the RAM 5, the host I/F 6, the timer 7, and the NAND I/F 8 in a manner allowing communication.
• the NAND flash memory 10 is configured by arraying a plurality of blocks.
• a block is a unit by which data is erased.
• a block includes a plurality of pages .
• a page is a unit by which data is written and read.
• the semiconductor storage device 1 communicates with the host device 2, via the host I/F 6, thereby performing data transfer between the host device 2 and the semiconductor storage device 1 in response to a request from the host device 2.
• Interpretation of the request from the host device 2 and control of the semiconductor storage device 1 itself are realized by the CPU 4 interpreting a program stored in the RAM 5 within the controlling unit 3.
• Data provided by the host device 2 is stored in the NAND flash memory 10.
• the controlling unit 3 mediates data transfer between the host device 2 and the NAND flash memory 10.
• the controlling unit 3 within the semiconductor storage device 1 communicates with the host device 2, via the host I/F 6, thereby performing data transfer between the RAM 5 within the controlling unit 3 and the host device 2.
• Data transferred from the host device 2 is temporarily retained in the RAM 5 within the controlling unit 3.
• the data is written to the NAND flash memory 10, via the NAND I/F 8.
• the controlling unit 3 the data is read from the NAND flash memory 10 in response to an instruction from the CPU 4, and the read data is stored in the RAM 5 within the controlling unit 3.
• the controlling unit 3 then transfers the data stored in the RAM 5 to the host device 2, via the host I/F 6.
• the NAND I/F 8 used when the data is written to and read from the NAND flash memory 10 includes an error correcting unit 21 and an error count detecting unit 22.
• the error correcting unit 21 and the error count detecting unit 22 serve as an error correcting circuit.
• the error correcting unit 21 provides a function for correcting an error in data read out from an arbitrary block within the NAND flash memory 10.
• the error count detecting unit 22 provides a function for detecting an error count of errors corrected by the error correcting unit 21.
• a correction capability of an error correcting code attached by the error correcting unit 21 is two bits or more.
• the present embodiment is described under a premise that the correction capability is eight bits. However, the present invention is not limited to this error correction capability.
• the error correcting unit 21 calculates the error correcting code of the data to be written in, and writes the error correcting code in the NAND flash memory 10 with the data.
• the error correcting unit 21 uses the data read out from the NAND flash memory 10 and the error correcting code stored with the data in the NAND flash memory 10 to correct an error in the read data.
• the error count detecting unit 22 detects an error count of corrected errors and stores therein the detected error count.
• the error count of corrected errors is stored in the error count detecting unit 22.
• a location in which the error count of corrected errors is stored is not limited thereto.
• the NAND I/F 8 When the error correcting unit 21 corrects the error, the NAND I/F 8 generates an interrupt to the CPU 4, thereby giving notification that an error has occurred in the data stored in the NAND flash memory 10. The CPU 4 then accesses the error count detecting unit 22 in the NAND I/F 8 and obtains the count of corrected errors.
• the timer 7 when an arbitrary amount of time is set, then internally measures time.
• the timer 7 generates an interrupt to the CPU 4 when the set amount of time elapses.
• the CPU 4 is notified of the elapse of the set amount of time by the interrupt from the timer 7.
• the NAND flash memory 10 stores therein data provided by the host device 2 and error correcting codes calculated from the data by the error correcting unit 21 in combination.
• the RAM 5 includes a first management table 31.
• the first management table 31 records therein information on blocks requiring a refresh operation to be performed in a near future.
• Fig. 2 is a diagram explaining a configuration of the first management table 31.
• the first management table 31 includes a plurality of entries .
• a block number in the NAND flash memory 10 is registered to each entry.
• the first management table 31 is accessed by an entry number.
• a block recorded in each entry is treated as a block in which an error count of storing data is to be monitored (referred to, hereinafter, as a monitored block) .
• the RAM 5 also may include a second management table 32, a third management table 33, a fourth management table 34, a fifth management table 35, a sixth management table 36, and a seventh management table 37.
• the second management table 32 to the seventh management table 37 will be described hereafter.
• Fig. 3 is a flowchart of a process for selecting a monitored block according to the first embodiment.
• the error correcting section 21 corrects the error in the read data.
• the error count detecting unit 22 detects the count of errors corrected and stores therein the detected error count.
• the CPU 4 accesses the error count detecting unit 22, acquires the error count of the errors that have occurred in the read data, and checks the error count (Step SlOl) .
• the CPU 4 then checks whether the error count is equal to a first threshold value or more (Step S102) .
• the first threshold value is a threshold value of the error count used to select a block to be monitored.
• the first threshold value is a two-bit.
• the CPU 4 selects the block in which the error has occurred (the block in which the data read out from the NAND flash memory 10 is stored) as the monitored block and registers the block to the first management table 31 (Step S103) .
• the CPU 4 completes the process without registering the block to the first management table 31.
• the data stored in the block registered to the first management table 31 has a high error count. It is very likely that the error count will further increase due to the influence of the aged deterioration and the read-disturb. Therefore, the CPU 4 periodically reads out the data in the block registered to the first management table 31 from the NAND flash memory 10, checks the error count, and monitors increasing tendency in the error count of the data. The CPU 4 performs a refresh operation on the block when the error count of errors that have occurred in the data stored in the block exceeds a specified number.
• the error count is detected from only the data read out from the NAND flash memory 10 in response to a read request by the host device 2, the aged deterioration occurring in data stored in a block that is rarely read out from the NAND flash memory 10 cannot be detected. Therefore, it is preferable that data in all areas of the first management table 31 in the NAND flash memory 10 is read at an arbitrary timing and the error count of the data is checked.
• the arbitrary timing can be when power is turned on, an interval of once every few months, and the like. As a result, the increasing tendency in the error count can be monitored for the data stored in blocks that are rarely read out.
• Fig. 4 is a flowchart of a process for checking whether a block newly selected as the monitored block is already registered to the first management table 31.
• the CPU 4 checks content registered in an Nth entry (N is an entry number in the first management table 31) in the first management table 31 (Step Sill) .
• the CPU 4 judges whether a block registered to the Nth entry is the same as the block newly selected as the monitored block (Step S112) .
• the CPU 4 completes the process.
• the CPU 4 checks whether the Nth entry is a last entry (Step S113) .
• the CPU 4 returns to Step Sill and increments the entry number by one.
• the CPU 4 completes the process.
• Fig. 5 is a flowchart of a process for registering the monitored block to the first management table 31.
• the CPU 4 checks the Nth entry (N is an entry number in the first management table 31) (Step S121) in the first management table 31 and judges whether the Nth entry is a blank entry (Step S122) .
• the CPU 4 registers the monitored block to the blank entry (Step S126) and completes the process.
• the CPU 4 checks whether the Nth entry is the last entry (Step S123) .
• the CPU 4 returns to Step S121 and increments the entry number by one.
• Step S123 the CPU 4 forcibly performs the refresh operation on a block registered to the first management table 31 and creates a blank entry in the first management table 31 (Step S124) . Since the error count of the data in the refreshed block decreases, the CPU 4 deletes the block from the first management table 31. The CPU 4 then registers the new monitored block to the blank entry (Step S125) and completes the process.
• Fig. 6 is a flowchart of a process for monitoring the error count of the block registered to the first management table 31.
• the CPU 4 checks the Nth entry (N is an entry number in the first management table 31) in the first management table 31 (Step S131) .
• the CPU 4 judges whether a block is already registered to the Nth entry (Step S132) .
• the CPU 4 checks whether the Nth entry is the last entry (Step S136) .
• the CPU 4 returns to Step S131 and increments the entry number by one.
• the CPU 4 completes the process .
• Step S132 when a block is already registered (Yes at Step S132) , the CPU 4 reads out the data in the block registered to the Nth entry from the NAND flash memory 10 to the RAM 5 within the controlling unit 3.
• the error correcting unit 21 corrects an error in the read data.
• the error count detecting unit 22 detects the count of corrected errors and stores therein the detected error count.
• the CPU 4 accesses the error count detecting unit 22, obtains the error count of the errors that have occurred in the read data, and checks the error count (Step S133) .
• the CPU 4 judges whether the error count of the read data is equal to a second threshold value or more (Step S134) .
• the second threshold value is a threshold value of the error count used to select a block in which data is to be rewritten (refreshed) by a predetermined method.
• the second threshold value is a four-bit.
• the second threshold value is set taking into consideration the correction capability of the error correcting code.
• the CPU 4 checks whether the Nth entry is the last entry (Step S136) . When the Nth entry is not the last entry (No at Step 136) , the CPU 4 returns to Step S131 and increments the entry number by one. When the Nth entry is the last entry (Yes at Step S136) , the CPU 4 completes the process.
• Step S134 when the error count is equal to the second threshold value or more (four bits or more) (Yes at Step S134) , the CPU 4 performs a refresh operation on the block registered to the Nth entry (Step S135) .
• the CPU 4 then checks whether the Nth entry is the last entry (Step S136) . When the Nth entry- is not the last entry (No at Step S136) , the CPU 4 returns to Step S131 and increments the entry number by one. When the Nth entry is the last entry (Yes at Step S131) , the CPU 4 completes the process.
• an error count threshold value (second threshold value) for refreshing the monitored block registered in the first management table 31 is set to be greater than an error count threshold value (first threshold value) for registering a block as the monitored block to the first management table 31.
• Fig. 7 is a flowchart of a process for deleting the refreshed block from the first management table 31.
• the CPU 4 checks the Nth (N is an entry number in the first management table 31) entry in the first management table 31 (Step S141) .
• the CPU 4 judges whether the registered block is a subject block, namely a refreshed block (Step S142) .
• the CPU 4 checks whether the entry is the last entry (Step S144) .
• the CPU 4 returns to Step S141 and increments the entry number by one.
• the CPU 4 completes the process.
• Step S142 when the registered block is the subject block (Yes at Step S142) , the CPU 4 deletes the block registered in the Nth entry from the first management table 31 (Step S143) and completes the process.
• the data can be rewritten in another empty block rather than being rewritten in the block in which the data had originally been written.
• the block in the NAND flash memory 10 storing the data that will require the refresh operation to be performed in the near future, due to the influence of the aged deterioration and the read-disturb, is selected based on the error count of errors occurring in the data stored in the block.
• the selected block is registered in the first management table 31 as the monitored block of which the error count of the data is monitored.
• the data in the block registered to the first management table 31 is periodically read and the error count is checked.
• the refresh operation is performed.
• an interval at which the refresh operation is performed on the block can be extended within a range of the correction capability of the error correcting code, thereby reducing the number of refresh operation performed.
• the number of times the NAND flash memory 10 is rewritten can be controlled.
• data corruption caused by the aged deterioration and the read-disturb can be prevented with more certainty by the refresh operation being less frequently performed.
• a semiconductor storage device can be actualized in which an amount of processing and power consumption during the refresh operation is suppressed.
• the error count threshold value (second threshold value) for refreshing the monitored block registered to the first management table 31 is greater than the error count threshold value (first threshold value) for registering a block as the monitored block to the first management table 31.
• first threshold value the error count threshold value for registering a block as the monitored block to the first management table 31.
• Fig. 8 is a diagram explaining a configuration of a second management table 32.
• the second management table 32 is a management table storing therein a read-out amount of data in a block in the NAND flash memory 10.
• the second management table 32 is configured in the RAM 5.
• the second management table 32 stores each of the block numbers in the NAND flash memory 10 and read-out amounts of data read from the blocks.
• the CPU 4 Whenever the CPU 4 reads out data from a block in the NAND flash memory 10, the CPU 4 counts a read-out amount of the data by a number of pages.
• the CPU 4 stores a page count in the second management table 32 and updates the page count.
• the read-out amount stored in the second management table 32 is a read-out amount counted after the data is stored in the block in the NAND flash memory 10. A value of the read-out amount is cleared whenever the data in the block is erased.
• An integrated quantity of data volume or a read-out frequency can be used as the read-out amount of the data.
• Fig. 9 is a flowchart of a monitored block selecting process according to the second embodiment.
• the CPU 4 updates a read-out amount in the second management table 32 of the data in the block (Step S151) -
• the CPU 4 checks whether the updated read-out amount of the data is equal to a third threshold value or more (Step S152) .
• the third threshold value is a threshold value of the read-out amount of the data from the block used to select a block to be monitored.
• the third threshold value is a read-out amount of ICTlO pages.
• the CPU 4 registers the block from which the data is read out to the first management table 31 as the monitored block (Step S153) .
• the CPU 4 completes the process without registering the block to the first management table 31.
• a method of monitoring the error count of the data in the blocks registered to the first management table 31 is similar to that according to the first embodiment. Detailed descriptions thereof are omitted.
• the block in the NAND flash memory 10 storing the data that will require a refresh operation to be performed in the near future, due to the influence of the aged deterioration and the read-disturb, is selected based on the read-out amount of the data stored in the block.
• the selected block is registered in the first management table 31 as the monitored block of which the error count of the data is monitored. Then, the data in the block registered to the first management table 31 is periodically read and the error count is checked. When the error count of the data exceeds a specified number, the refresh operation is performed.
• a third embodiment a case that a monitored block is selected based on a writing time at which data is written in a block in the NAND flash memory 10 in the semiconductor storage device 1 of Fig. 1 is described.
• a method of registering the monitored block according to the third embodiment differs from that according to the first embodiment.
• Other aspects according to the third embodiment are the same as those according to the first embodiment.
• Fig. 10 is a diagram explaining a configuration of a third management table 33.
• the third management table 33 is a management table storing therein a writing time at which data is written in a block in the NAND flash memory 10.
• the third management table 33 is configured in the RAM 5.
• the third management table 33 stores each of the block numbers in the NAND flash memory 10 and writing times at which data are written in the blocks.
• the CPU 4 When the CPU 4 writes data in the block in the NAND flash memory 10, the CPU 4 stores a writing time in the third management table 33.
• a value of the writing time stored in the third management table 33 is cleared whenever the data in the block in the NAND flash memory is erased.
• the writing time stored in the third management table 33 is merely required to indicate a time difference between a point in time at which the data is written and a current time, through use of a total number of erasures in the NAND flash memory and the like, in addition to an operating time of the semiconductor storage device 1.
• Fig. 11 is a flowchart of a monitored block selecting process according to the third embodiment.
• the CPU 4 calculates a difference between a writing time stored in the third management table 33 at which a last writing operation has been performed on the block from which the data is to be read, and a current time. In other words, the CPU 4 calculates an amount of elapsed time from the writing time of the block from which the data is to be read (Step S161) . The CPU 4 then checks whether the elapsed time from the writing time of the block is equal to a fourth threshold value or more (Step S162) .
• the fourth threshold value is a threshold value of an amount of time elapsed from a writing time of the block used to select the block to be monitored. Here, for example, the fourth threshold value is one month.
• the CPU 4 registers the block from which the data is read to the first management table 31 as the monitored block (Step S163) .
• the CPU 4 completes the process without registering the block to the first management table 31.
• a method of monitoring the error count of the data in the blocks registered to the first management table 31 is similar to that according to the first embodiment. Detailed descriptions thereof are omitted.
• the elapsed time from the writing time of the block is checked only for the data read out from the NAND flash memory 10 in response to a read request by the host device 2, the aged deterioration occurring in data stored in a block that is rarely read out from the NAND flash memory 10 cannot be detected. Therefore, it is preferable that data in all areas of the first management table 31 in the NAND flash memory 10 is read at an arbitrary timing and the elapsed time from the writing time of the blocks is checked.
• the arbitrary timing can be when power is turned ON, an interval of once every few months, and the like. As a result, the increasing tendency in the error count can be monitored for the data stored in blocks that are rarely read.
• the block in the NAND flash memory 10 storing the data that will require a refresh operation to be performed in the near future, due to the influence of the aged deterioration and the read-disturb, is selected based on the elapsed time from a last writing time of the block.
• the selected block is registered in the first management table 31 as the monitored block of which the error count of the data is monitored. Then, the data in the block registered to the first management table 31 is periodically read and the error count is checked. When the error count of the data exceeds a specified number, the refresh operation is performed.
• a fourth embodiment a case that a monitored block is selected based on a sequence in which data is written in blocks in the NAND flash memory 10 in the semiconductor storage device 1 of Fig. 1 is described.
• a method of registering the monitored block according to the fourth embodiment differs from that according to the first embodiment.
• Other aspects according to the fourth embodiment are the same as those according to the first embodiment.
• Fig. 12 is a diagram explaining a configuration of a fourth management table 34.
• the fourth management table 34 is a management table storing therein a sequence in which data is written in the blocks in the NAND flash memory 10.
• the fourth management table 34 is configured in the RAM 5.
• the fourth management table 34 stores each of the block numbers in the NAND flash memory 10 and corresponding sequence numbers in which data is written in the NAND flash memory 10.
• the CPU 4 When the CPU 4 writes data in a block in the NAND flash memory 10, the CPU 4 stores the sequence number in which the data is written in the NAND flash memory 10 in the fourth management table 34 and updates the fourth management table 34.
• the fourth management table 34 is preferably actualized by a linked structure or the like, such that processes to be performed do not increase even when writing sequence numbers are updated whenever a writing process is performed. As a result, processing load placed on the CPU 4 can be reduced and processing time can be shortened.
• a writing process for writing data in the NAND flash memory 10 in response to a request from the host device 2 is performed, a sequence number in which data is written in the blocks in the NAND flash memory 10 is stored and the sequence numbers are updated through procedures shown in Fig. 13. A block of which the error count is to be monitored is decided based on the writing sequence number.
• Fig. 13 is a flowchart of a monitored block selecting process according to the fourth embodiment.
• the CPU 4 stores the writing sequence number in the fourth management table 34 and updates the writing sequence numbers (Step S171) .
• the CPU 4 then checks a block corresponding to an Nth writing sequence number (N is a writing sequence number in the fourth management table 34) in the fourth management table 34 (Step S172) .
• the CPU 4 checks whether the writing sequence number is equal to a fifth threshold value or less or, in other words, whether the block is older than the fifth threshold value (Step S173) .
• the fifth threshold value is a threshold value of a writing sequence used to select the block to be monitored.
• the fifth threshold value is ten blocks from a block with an oldest (smallest) writing sequence number.
• the CPU 4 checks whether the block is registered to the first management table 31 (Step S174) .
• the CPU registers the block to the first management table 31 as the monitored block (Step S175) .
• the CPU registers the block that has been written further in the past than the fifth threshold value in the first management table 31 as the monitored block, and checks the error count of the data.
• Step S174 when the block is already registered to the first management table 31 (Yes at Step S174), the CPU 4 checks whether the Nth writing sequence number is a last writing sequence number (Step S176) .
• the CPU 4 returns to Step S172 and increments the writing sequence number by one.
• the Nth writing sequence number is the last writing sequence number (Yes at Step S176)
• the CPU 4 completes the process.
• Step S173 when the writing sequence number is not equal to the fifth threshold value or less or, in other words, is a newer block than the fifth threshold value (No at Step S173) , the CPU 4 checks whether the Nth writing sequence number is the last writing sequence number (Step S176) .
• Step S176 the CPU 4 returns to Step S172 and increments the writing sequence number by one.
• the Nth writing sequence number is the last writing sequence number (Yes at Step S176)
• the CPU 4 completes the process.
• a method of monitoring the error count of the data in the blocks registered to the first management table 31 is similar to that according to the first embodiment. Detailed descriptions thereof are omitted.
• the block in the NAND flash memory 10 storing the data that will require a refresh operation to be performed in the near future, due to the influence of the aged deterioration and the read-disturb, is selected based on the sequence in which the data are written in the blocks in the NAND flash memory 10.
• the selected block is registered in the first management table 31 as the monitored block of which the error count in the data is monitored. Then, the data in the block registered to the first management table 31 is periodically read and the error count is checked. When the error count of the data exceeds a specified number, the refresh operation is performed.
• an interval at which the refresh operation is performed on the block can be extended within a range of the correction capability of the error correcting code, thereby reducing a number of refresh operations performed.
• the number of times the NAND flash memory 10 is rewritten can be controlled.
• data corruption due to the aged deterioration and the read-disturb can be prevented with more certainty by the refresh operation being less frequently performed.
• a semiconductor storage device can be actualized in which an amount of processing and power consumption during the refresh operation is suppressed.
• a process performed when a blank entry is not available when a block is registered to the first management table 31 in the semiconductor storage device 1 according to the first embodiment to the fourth embodiment is described.
• Fig. 14 is a diagram explaining a configuration of a fifth management table 35.
• the fifth management table 35 is a management table storing therein a registration sequence of monitored blocks registered to the first management table 31.
• the fifth management table 35 is configured in the RAM 5.
• the fifth management table 35 stores numbers of monitored blocks registered to the first management table 31 and sequence numbers of a sequence in which the monitored blocks are registered to the first management table 31 (registration sequence number) .
• registration sequence number the monitored blocks are registered to the first management table 31
• the monitored blocks are sequentially stored such that a monitored block that is registered earlier has a lower entry number in the first management table 31.
• the CPU 4 registers a block number of the monitored block to the fifth management table 35.
• the fifth management table 35 is preferably actualized by a linked list because the CPU 4 updates the registration sequence numbers whenever a monitored block is registered to or deleted from the first management table 31. As a result, processing load placed on the CPU 4 can be reduced and processing time can be shortened.
• Fig. 15 is a flowchart of a registering process for registering the monitored block to the first management table 31 according to the fifth embodiment.
• the CPU 4 checks whether a registered block count of blocks registered to the fifth management table 35 is less than a sixth threshold value (Step S181) .
• the sixth threshold value is a maximum number of blocks that can be registered to the first management table 31 and a maximum number of blocks that can be registered to the fifth management table 35.
• the registered block count of the blocks registered to the fifth management table 35 being less than the sixth threshold value indicates that a blank entry is available in the first management table 31.
• the registered block count of the blocks registered to the fifth management table 35 not being less than the sixth threshold value indicates than a blank entry is not available in the first management table 31.
• the CPU 4 registers the monitored block to the blank entry in the first management table 31 (Step S184) .
• the CPU 4 further registers the block number of the monitored block to the fifth management table 35 and completes the process.
• the CPU 4 references the fifth management table 5 and refreshes data in the monitored block of which the registration sequence number in the fifth management table 35 is earliest (Step S182) .
• the CPU 4 refreshes data in the block that has been registered to the first management table 31 and the fifth management table 35 earliest.
• the CPU 4 then deletes the refreshed block from the first management table 31 and the fifth management table 35 (Step S183) .
• the CPU 4 registers the new monitored block to the blank entry in the first management table 31.
• the CPU 4 then registers the monitored block registered to the blank entry in the first management table 31 to the fifth management table 35 (Step S184) .
• a new monitored block can be registered to the first management table 31 even when a blank entry is not available when the monitored block is registered to the first management table 31.
• the monitored blocks storing data of which the error count is monitored can be managed.
• a process performed when a block that has become excluded from data error count monitoring is deleted from the first management table 31 in the semiconductor storage device 1 according to the first embodiment to the fifth embodiment is described.
• Fig. 16 is a diagram explaining a configuration of a sixth management table 36.
• the sixth management table 36 is a management table storing therein blocks in the NAND flash memory 10 in which data to be retained is not stored.
• the sixth management table 36 is configured in the RAM 5.
• a block number of a block that does not store therein data to be retained, among block numbers of blocks in the NAND flash memory 10 is registered in each entry.
• the sixth management table 36 is accessed by entry numbers.
• the CPU 4 acquires information from the sixth management table 36 on a block that does not store therein data to be retained and, as a result, can write a new data in the block.
• the CPU 4 also registers the block in which the data to be retained is no longer present to the sixth management table 36. A state in which the data to be retained is no longer present occurs mainly when a new data is written.
• Fig. 17 is a flowchart of a deleting process for deleting a block excluded from error count monitoring from the first management table according to the sixth embodiment.
• N is an entry number in the first management table 31
• the CPU 4 judges whether a block registered to the Nth entry is a subject block (a block excluded from monitoring in which the data to be retained is no longer present) (Step S192) .
• the CPU 4 judges whether the entry is a last entry (Step S193) .
• Step S193 when the entry is not the last entry (No at Step S193), the CPU 4 returns to Step S191 and increments the entry number by one.
• the entry is the last entry (Yes at Step S193) , the CPU 4 completes the process.
• Step S192 when the block is the subject block (Yes at Step S192) , the CPU 4 performs a deleting process to delete the block from the first management table 31.
• the CPU 4 registers the block number of the block to the sixth management table 36 and completes the process (Step S194).
• the block registered to the sixth management table 36 is not required to be updated because the block does not store therein data to be retained.
• the semiconductor storage device 1 when a block is generated that is excluded from monitoring and in which data to be retained is no longer present when, for example, new data is written in the block in the NAND flash memory in which the data is stored, the block that is excluded from monitoring can be deleted from the first management table 31 with certainty, and blank entries in the first management table 31 can be managed.
• a method of monitoring a monitored block registered to the first management table 31 in the semiconductor storage device 1 according to the first embodiment to the sixth embodiment is described.
• Fig. 18 is a diagram explaining a configuration of a seventh management table 37.
• the seventh management table 37 is a management table storing therein error counts of blocks in the NAND flash memory 10 registered to the first management table 31.
• the seventh management table 37 is configured in the RAM 5.
• the seventh management table 37 includes a plurality of entries. A block number of a block registered to the first management table 31 and an error count detected from data stored in the block are registered to each entry.
• the seventh management table 37 is accessed by an entry number. Values of the error counts registered to the seventh management table 37 are updated whenever error count monitoring is performed.
• Fig. 19 is a flowchart of an error count monitoring process performed on the monitored block registered to the first management table 31.
• the CPU 4 sets a monitoring interval period in the timer
• the error count monitoring process on the monitored block registered to the first management table 31 is performed whenever an interrupt is generated by the timer 7.
• the timer 7 internally measures time when the CPU sets the monitoring interval period. After the set period elapses, the timer 7 generates an interrupt to the CPU 4.
• the CPU 4 checks an Nth entry (N is an entry number in the seventh management table 37) of the seventh management table 37 (Step S201) .
• the CPU 4 judges whether a block is already registered to the Nth entry (Step S202) .
• the CPU 4 judges whether the Nth entry is a last entry (Step S206) .
• the CPU 4 returns to Step S201 and increments the entry number by one.
• the CPU 4 completes the error count monitoring process .
• Step S202 when a block is already registered (Yes at Step S202) , the CPU 4 checks an error count (number of bits) of the block registered to the seventh management table 37 (Step S203) .
• the CPU 4 judges whether the error count is equal to a seventh threshold value or more (Step S204).
• the seventh threshold value is used to select a block on which an error count detecting process is to be performed, among the monitored blocks .
• the seventh threshold value is, for example, four bits of error.
• the CPU 4 checks whether the Nth entry is the last entry (Step S206) . When the Nth entry is not the last entry (No at Step S206) , the CPU 4 returns to Step S201 and increments the entry number by one. When the Nth entry is the last entry (Yes at Step S206) , the CPU 4 completes the error count monitoring process.
• Step S204 when the error count is the seventh threshold value or more (four bits or more) (Yes at Step S204), the CPU 4 reads out the data in the block from the NAND flash memory 10 to the RAM 5 within the controlling unit 3 and performs an error count detecting process on the data (Step S205) .
• the CPU 4 updates the seventh management table 37 with a detected error count. Based on the detected error count, the CPU 4 performs the refresh operation according to the first embodiment, described with reference to Fig. 6.
• Step S206 the CPU 4 checks whether the Nth entry is the last entry.
• the CPU 4 returns to Step S201 and increments the entry number by one.
• the CPU 4 completes the error count monitoring process.
• a value set as the above-described seventh threshold value decreases whenever the error count detecting process is performed, gradually facilitating error count detection to be performed on blocks with a low error count. As a result, the error count detection is performed each time on the blocks with a high error count over a short cycle. The error count detection is performed on the blocks with a low error count over a long cycle.
• the value set as the seventh threshold value returns to an original value after the value is decreased to a predetermined, specified value.
• the semiconductor storage device 1 determines whether an error count detecting process is newly performed on a monitored block based on the error counts registered to the seventh management table 37.
• the error count detection is performed on the blocks with a high error count over a short cycle.
• the error count detection is performed on the blocks with a low error count over a long cycle.
• the monitoring intervals of the monitored blocks registered to the first management table 31 can be changed based on the error counts registered to the seventh management table 37.
• the error count of the data in a block that will most likely require updating in the near future, among the monitored blocks registered to the first management table 31, can be monitored with certainty. At the same time, frequency of the error count monitoring can be reduced.
• an error count monitoring cycle according to the seventh embodiment will be described.
• an upper limit is set for a monitoring cycle (monitoring interval period set in the timer 7) of blocks having a low error count.
• the upper limit of the monitoring cycle is set to be shorter than an amount of time required from when an error count of data stored in a block exceeds the first threshold value until the error count of the data stored in the block reaches an upper limit of a correction capability of the error correcting section 21.
• the monitoring cycle can be set in advance to a period predicted from an error occurrence state and various conditions, such as a range of ambient temperature, of the semiconductor storage device 1.
• Fig. 20 is a block diagram of a configuration of a SSD 100.
• the SSD 100 includes a plurality of NAND flash memories (NAND memory) 10, a dynamic random access memory (DRAM) 101, a drive controlling circuit 102, and a power supply circuit 103.
• the NAND memories 10 are used to store data.
• the DRAM 101 is used for data transfer and as a work area.
• the drive controlling circuit 102 controls the NAND memories 10 and the DRAM 101.
• the drive controlling circuit 102 outputs a control signal for controlling a light-emitting diode (LED) provided outside of the SSD 100. The LED is used to indicate status.
• LED light-emitting diode
• the SSD 100 transmits and receives data to and from a host device, such as a personal computer, via an advanced technology attachment (ATA) interface (I/F) .
• a host device such as a personal computer
• I/F advanced technology attachment
• the SSD 100 transmits and receives data to and from a debugging device, via an RS-232C interface (I/F) .
• I/F RS-232C interface
• the power supply circuit 103 receives external power supply and generates a plurality of internal power supplies using the external power supply.
• the internal power supplies are supplied to each section within the SSD 100.
• the power supply circuit 103 detects a rise or fall of the external power supply and generates a power-ON reset signal.
• the power-ON reset signal is sent to the drive controlling circuit 102.
• Fig. 21 is a block diagram of a configuration of the drive controlling circuit 102.
• the drive controlling circuit 102 includes a data access bus 104, a first circuit controlling bus 105, and a second circuit controlling bus 106.
• the first circuit controlling bus 105 is connected to a processor 107 that controls the overall drive controlling circuit 102.
• a boot read-only memory (ROM) 108 is also connected to the first circuit controlling bus 105, via a ROM controller 109.
• the boot ROM 108 stores a boot program of each management program (firmware [FW] ) .
• a clock controller 110 is also connected to the first circuit controlling bus 105. The clock controller 110 receives the power-ON reset signal from the power supply circuit 103 and supplies each section with a reset signal and a clock signal.
• the second circuit controlling bus 106 is connected to the first circuit controlling bus 105.
• a parallel IO (PIO) circuit 111 and a serial IO (SIO) circuit 112 are connected to the second circuit controlling bus 106.
• the PIO circuit 111 supplies a status indicating signal to the LED used to indicate the status.
• the SIO circuit 112 controls the RS-232C interface.
• An ATA interface controller (ATA controller) 113 An ATA interface controller (ATA controller) 113, a first error check and correct (ECC) circuit 114, an NAND controller
• the ATA controller 113 transmits and receives data to and from the host device, via the ATA interface.
• a static random access memory (SRAM) 120 is connected to the data access bus 104, via a SRAM controller 121.
• the SRAM 120 is used as a data work area
• the NAND controller 115 includes an NAND interface (I/F)
• the NAND interface 118, a second ECC circuit 117, and a direct memory access (DMA) transfer controlling DMA controller 116.
• DMA direct memory access
• the DMA transfer controlling DMA controller 116 performs access control between the NAND memories 10 and the DRAM 101.
• Fig. 22 is a block diagram of a configuration of a processor 107.
• the processor 107 includes a data managing unit 122, an ATA command processing unit 123, a security managing unit 124, a boot loader 125, an initialization managing unit 126, and a debug supporting unit 127.
• the data managing unit 122 controls data transfer between the NAND memories 10 and the DRAM 101, and various functions related to an NAND chip, via the NAND controller 115 and the first ECC circuit 114.
• the ATA command processing unit 123 performs a data transfer process in cooperation with the data managing unit 122, via the ATA controller 113 and the DRAM controller 119.
• the security managing unit 124 manages various pieces of security information in cooperation with the data managing unit 122 and the ATA command processing unit 123.
• the boot loader 125 loads each management program (FW) from the NAND memory 10 to the SRAM 120 when power is turned ON.
• the initialization managing unit 126 performs initialization of each controller and circuit within the drive controlling circuit 102.
• the debug supporting unit 127 processes debugging data supplied from an external source via the RS-232C interface.
• Fig. 23 is a perspective view of an example of a portable computer 2000 on which the SSD 100 is mounted.
• the portable computer 200 includes a main body 201 and a display unit 202.
• the display unit 202 includes a display housing 203 and a display device 204 housed within the display housing 203.
• the main body 201 includes a casing 205, a keyboard (KB) 206, and a touch pad 207 serving as a pointing device.
• the casing 205 houses therein a main circuit board, an optical disk drive (ODD), a card slot, the SSD 100, and the like.
• the card slot is provided adjacent to a peripheral wall of the casing 205.
• An opening 208 facing the card slot is provided on the peripheral wall. A user can insert and remove an additional device into and from the card slot from outside of the casing 205, through the opening 208.
• the SSD 100 can be used mounted within the portable computer 22 in place of a conventional hard disk drive (HDD) .
• the SSD 100 can be used as an additional device by being inserted into the card slot provided in the portable computer 200.
• Fig. 24 is a diagram of an example of a system configuration of the portable computer 200 on which the SSD 100 is mounted.
• the portable computer 200 includes a CPU 301, a north bridge 302, a main memory 303, a video controller 304, an audio controller 305, a south bridge 309, a basic input output system read-only memory (BIOS-ROM) 310, the SSD 100, an ODD unit 311, an embedded controller/keyboard controller integrated chip (IC) (EC/KBC) 312, a network controller 313 and the like.
• the CPU 301 is a processor provided to control operation of the portable computer 200.
• the CPU 301 runs an operating system (OS) loaded onto a main memory 303 from the SSD 100.
• OS operating system
• the CPU 301 when the ODD unit 311 can perform at least one process between reading from loaded optical disc and writing to the loaded optical disc, the CPU 301 performs the processes.
• the CPU 301 also runs a system BIOS stored in the BIOS-ROM 310.
• the system BIOS is a program for performing hardware control within the portable computer 200.
• the north bridge 302 is a bridge device connecting a local bus of the CPU 301 and the south bridge 309.
• a memory controller that access-controls the main memory 303 is also included in the north bridge 302.
• the north bridge 302 also provides a function for communicating with the video controller 304 and the audio controller 305 via an accelerated graphics port (AGP) bus and the like.
• AGP accelerated graphics port
• the main memory 303 temporarily stores programs and data, and functions as a work area.
• the main memory 303 is, for example, configured by a DRAM.
• the video controller 304 is a video reproduction controller that controls a liquid crystal display (LCD) 316 of the display unit 202 used as a display monitor of the portable computer 200.
• the audio controller 305 is an audio reproduction controller that controls a speaker 306 on the portable computer 200.
• the south bridge 309 controls each device on a low pin count bus 314 and each device on a peripheral component interconnect bus 315.
• the south bridge 309 also controls the SSD 100 via the ATA interface.
• the SSD 100 is a memory device storing various software and data
• the portable computer 200 accesses the SSD 100 in sector units.
• the portable computer 200 inputs a writing command, a read-out command, a flash command, and the like into the SSD 100, via the ATA interface.
• the south bridge 309 also provides a function for access-controlling the BIOS-ROM 310 and the ODD unit 311.
• the EC/KBD 312 is a single chip microcomputer in which an embedded controller for power management and a keyboard controller for controlling the KB 206 and the touch pad 207 are integrated.
• the EC/KBD 312 provides a function for turning ON and OFF the power supply of the portable computer 200 in response to operation of a power button by the user.
• the network controller 313 is a communication device that communicates with an external network, such as the Internet.
• the semiconductor storage device 1 is not limited to the SSD.
• the semiconductor storage device 1 can be configured as a memory card, represented by a Secure Digital (SD) card (registered trademark) .
• SD Secure Digital
• the semiconductor storage device 1 can be applied to various electronic devices, such as a mobile phone, a personal digital assistant (PDA) , a digital still camera, and a digital video camera, in addition to the portable computer.
• PDA personal digital assistant

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