WO2009041041A1 - 不揮発性記憶素子及び不揮発性半導体記憶装置、並びにそれらの読み出し方法及び書き込み方法 - Google Patents

不揮発性記憶素子及び不揮発性半導体記憶装置、並びにそれらの読み出し方法及び書き込み方法 Download PDF

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Publication number
WO2009041041A1
WO2009041041A1 PCT/JP2008/002657 JP2008002657W WO2009041041A1 WO 2009041041 A1 WO2009041041 A1 WO 2009041041A1 JP 2008002657 W JP2008002657 W JP 2008002657W WO 2009041041 A1 WO2009041041 A1 WO 2009041041A1
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WO
WIPO (PCT)
Prior art keywords
memory element
storage device
nonvolatile
electrode
reading data
Prior art date
Application number
PCT/JP2008/002657
Other languages
English (en)
French (fr)
Inventor
Koichi Osano
Shunsaku Muraoka
Satoru Fujii
Kazuhiko Shimakawa
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to CN2008800012285A priority Critical patent/CN101568971B/zh
Priority to US12/516,703 priority patent/US7965539B2/en
Priority to JP2009501765A priority patent/JP4383523B2/ja
Publication of WO2009041041A1 publication Critical patent/WO2009041041A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0076—Write operation performed depending on read result
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/34—Material includes an oxide or a nitride
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Abstract

　本発明の不揮発性記憶素子(101)は、第１電極(111)と第２電極(113)との間に設けられる可変抵抗層(112)は、４族、５族、又は６族の金属元素の酸化物を含むように構成されており、特定の電圧の電気的パルスが第１電極(111)と第２電極(113)との間に印加された場合に、その抵抗値が高抵抗値ＲＨとなる第１の高抵抗状態及び第２の高抵抗状態、並びにその抵抗値が低抵抗値ＲＬとなる低抵抗状態の何れかの状態をとり得る。
PCT/JP2008/002657 2007-09-28 2008-09-25 不揮発性記憶素子及び不揮発性半導体記憶装置、並びにそれらの読み出し方法及び書き込み方法 WO2009041041A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2008800012285A CN101568971B (zh) 2007-09-28 2008-09-25 非易失性存储元件和半导体存储装置及其读写方法
US12/516,703 US7965539B2 (en) 2007-09-28 2008-09-25 Nonvolatile memory element, nonvolatile semiconductor memory apparatus, and reading method and writing method therefor
JP2009501765A JP4383523B2 (ja) 2007-09-28 2008-09-25 不揮発性記憶素子及び不揮発性半導体記憶装置、並びにそれらの読み出し方法及び書き込み方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007253331 2007-09-28
JP2007-253331 2007-09-28

Publications (1)

Publication Number Publication Date
WO2009041041A1 true WO2009041041A1 (ja) 2009-04-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/002657 WO2009041041A1 (ja) 2007-09-28 2008-09-25 不揮発性記憶素子及び不揮発性半導体記憶装置、並びにそれらの読み出し方法及び書き込み方法

Country Status (4)

Country Link
US (1) US7965539B2 (ja)
JP (1) JP4383523B2 (ja)
CN (1) CN101568971B (ja)
WO (1) WO2009041041A1 (ja)

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JP2009267411A (ja) * 2008-04-25 2009-11-12 Seagate Technology Llc 複数メモリ層を有するメモリセルを含む記憶装置
WO2009147790A1 (ja) * 2008-06-03 2009-12-10 パナソニック株式会社 不揮発性記憶素子、不揮発性記憶装置、および不揮発性半導体装置
KR20120039518A (ko) * 2009-05-29 2012-04-25 포르슝스젠트룸 율리히 게엠베하 메모리 소자, 스택킹, 메모리 매트릭스, 및 작동 방법
WO2013057912A1 (ja) * 2011-10-18 2013-04-25 パナソニック株式会社 不揮発性記憶素子、不揮発性記憶装置、及び不揮発性記憶素子の書き込み方法
JP2016042403A (ja) * 2014-08-19 2016-03-31 ルネサスエレクトロニクス株式会社 半導体装置及びフォーミング方法

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US8437174B2 (en) 2010-02-15 2013-05-07 Micron Technology, Inc. Memcapacitor devices, field effect transistor devices, non-volatile memory arrays, and methods of programming
US8416609B2 (en) 2010-02-15 2013-04-09 Micron Technology, Inc. Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems
KR101744757B1 (ko) * 2010-06-22 2017-06-09 삼성전자 주식회사 가변 저항 소자, 상기 가변 저항 소자를 포함하는 반도체 장치 및 상기 반도체 장치의 동작 방법
US8634224B2 (en) * 2010-08-12 2014-01-21 Micron Technology, Inc. Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and reading from a memory cell, and methods of programming a memory cell
CN102034535B (zh) * 2010-12-15 2013-01-16 清华大学 带有操控电路的三值型阻变存储单元及其读写实现方法
WO2012178114A2 (en) * 2011-06-24 2012-12-27 Rambus Inc. Resistance memory cell
US8942024B2 (en) * 2011-12-06 2015-01-27 Agency For Science, Technology And Research Circuit arrangement and a method of writing states to a memory cell
JP2013197420A (ja) * 2012-03-21 2013-09-30 Toshiba Corp 抵抗変化メモリ素子
DE102013200615A1 (de) * 2013-01-16 2014-07-17 Helmholtz-Zentrum Dresden - Rossendorf E.V. Komplementärer Widerstandsschalter, dessen Herstellung und Verwendung
EP2917946B1 (de) 2013-01-16 2018-08-29 Helmholtz-Zentrum Dresden - Rossendorf e.V. Verfahren und schaltkreis-anordnung zum verschlüsseln und entschlüsseln einer bitfolge

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WO2008059701A1 (ja) * 2006-11-17 2008-05-22 Panasonic Corporation 不揮発性記憶素子、不揮発性記憶装置、不揮発性半導体装置、および不揮発性記憶素子の製造方法
WO2008126365A1 (ja) * 2007-03-29 2008-10-23 Panasonic Corporation 不揮発性記憶装置、不揮発性記憶素子および不揮発性記憶素子アレイ

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WO2008059701A1 (ja) * 2006-11-17 2008-05-22 Panasonic Corporation 不揮発性記憶素子、不揮発性記憶装置、不揮発性半導体装置、および不揮発性記憶素子の製造方法
WO2008126365A1 (ja) * 2007-03-29 2008-10-23 Panasonic Corporation 不揮発性記憶装置、不揮発性記憶素子および不揮発性記憶素子アレイ

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009267411A (ja) * 2008-04-25 2009-11-12 Seagate Technology Llc 複数メモリ層を有するメモリセルを含む記憶装置
US8179713B2 (en) 2008-06-03 2012-05-15 Panasonic Corporation Nonvolatile memory element, nonvolatile memory device, and nonvolatile semiconductor device
JP4460646B2 (ja) * 2008-06-03 2010-05-12 パナソニック株式会社 不揮発性記憶素子、不揮発性記憶装置、および不揮発性半導体装置
JPWO2009147790A1 (ja) * 2008-06-03 2011-10-20 パナソニック株式会社 不揮発性記憶素子、不揮発性記憶装置、および不揮発性半導体装置
WO2009147790A1 (ja) * 2008-06-03 2009-12-10 パナソニック株式会社 不揮発性記憶素子、不揮発性記憶装置、および不揮発性半導体装置
KR20120039518A (ko) * 2009-05-29 2012-04-25 포르슝스젠트룸 율리히 게엠베하 메모리 소자, 스택킹, 메모리 매트릭스, 및 작동 방법
CN102449702A (zh) * 2009-05-29 2012-05-09 于利奇研究中心有限公司 存储元件、堆叠、存储矩阵和用于运行的方法
JP2012528419A (ja) * 2009-05-29 2012-11-12 フォルシュングスツェントルム・ユーリッヒ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング メモリ素子、積層体、メモリマトリックス及びそれらの動作方法
KR101725361B1 (ko) 2009-05-29 2017-04-10 포르슝스젠트룸 율리히 게엠베하 메모리 소자, 스택킹, 메모리 매트릭스, 및 작동 방법
WO2013057912A1 (ja) * 2011-10-18 2013-04-25 パナソニック株式会社 不揮発性記憶素子、不揮発性記憶装置、及び不揮発性記憶素子の書き込み方法
JP5291270B1 (ja) * 2011-10-18 2013-09-18 パナソニック株式会社 不揮発性記憶素子、不揮発性記憶装置、及び不揮発性記憶素子の書き込み方法
US9111640B2 (en) 2011-10-18 2015-08-18 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile memory element, nonvolatile memory device, and writing method for use in nonvolatile memory element
JP2016042403A (ja) * 2014-08-19 2016-03-31 ルネサスエレクトロニクス株式会社 半導体装置及びフォーミング方法

Also Published As

Publication number Publication date
CN101568971B (zh) 2012-11-07
US7965539B2 (en) 2011-06-21
JPWO2009041041A1 (ja) 2011-01-20
JP4383523B2 (ja) 2009-12-16
US20100271859A1 (en) 2010-10-28
CN101568971A (zh) 2009-10-28

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