Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
  • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/34—Analogue value compared with reference values
  • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
  • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
  • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
  • H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
  • H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
  • H03M1/141—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit in which at least one step is of the folding type; Folding stages therefore
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/20—Increasing resolution using an n bit system to obtain n + m bits
  • H03M1/202—Increasing resolution using an n bit system to obtain n + m bits by interpolation
  • H03M1/203—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit
  • H03M1/204—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators
  • H03M1/205—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators using resistor strings for redistribution of the original reference signals or signals derived therefrom
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/34—Analogue value compared with reference values
  • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
  • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
  • H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
  • H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string

Definitions

• the present invention relates to a folding circuit and an analog / digital converter including the same.
• FIG. 1 is a circuit diagram showing a general folding circuit.
• the folding circuit 10 includes a ladder resistor 11 that generates a reference voltage, a plurality of amplifier circuits D1 to D5 whose current output terminals are alternately connected, and load resistors R1 and R2.
• the ladder resistor 11 includes a plurality of resistors R3 to R6 connected in cascade between a supply terminal for the maximum reference voltage Vrt and a supply terminal for the minimum reference voltage Vrb. Nodes between each resistor and multiple reference voltages whose values change sequentially from the above two supply terminals ⁇ , ⁇ 1, ⁇ 2, ⁇ 3
• Vrt is output.
• FIG. 2 is a diagram illustrating a circuit example of an amplifier circuit.
• the amplifier circuits D1 to D5 include two NMOS transistors 12a and 12b forming a differential pair, and one current source 13.
• the voltage of the input signal (input voltage Vin) is applied to the gate of the NMOS transistor 12a, and the reference voltage Vr is input to the gates of the other MOS transistors 12b.
• the sources of the NMOS transistors 12a and 12b are connected to each other and are biased by the current flowing through the current source 13.
• FIG. 3 considering this input / output characteristic (FIG. 3), a transistor that draws a current in the differential pair whenever each amplifier circuit exceeds the reference voltage Vr is shown in FIG.
• the reference voltage Vr is applied to the NMOS transistor 12b side (hereinafter referred to as the positive phase output side) )
• To the NMOS transistor 12a side to which the input voltage Vin is applied (hereinafter referred to as the negative phase output side).
• the folding circuit tends to have a low input band because the change in the input signal increases by the number of turns. For this reason, a track hold circuit (T / H) is often provided at the input stage to stop the change of the input signal in synchronization with the control clock. As a result, the input bandwidth can be easily extended to the bandwidth of the T / H.
• an amplifier circuit that generates a folding waveform is a continuous circuit and is therefore very vulnerable to a large amplitude response. This is largely due to the fact that the bias current is completely steered by the excessive input in the differential pair that forms the folding circuit, and one of the transistors shown in Fig. 2 is cut off.
• Non-Patent Document 1 To solve this problem, the problem as described in Non-Patent Document 1 is solved and a high-speed response is achieved.
• a switch 14 is provided at the output terminal of the amplifier circuit that generates the folding waveform, and the switch is turned on only during the track period of the track hold circuit (T / H).
• the aim is to improve the recovery time of the amplifier circuit by resetting the! This is described in this non-patent document 1 as being 5 times faster than before!
• Non-Patent Document 1 "An 8b 600MS / s 200mW CMOS Folding A / D Converter Using an Amplifier Preset Technique” Govert Geelen etal, ISSCC04 Digest of Technical Paper 1 4.2, 2004 Feb.
• the differential analog input signal is received by the track hold and the differential output follows the differential analog input signal during the track, and the CLK signal is held.
• the input signal at the rising edge (falling edge) is maintained and differential output is performed.
• the differential amplifier circuit amplifies and outputs the differential signal, and the differential distributed amplifier circuit generates a desired folded waveform.
• An object of the present invention is to provide a folding circuit and an analog digital converter capable of reducing the load of a clock signal with a small signal response and preventing an increase in the area constituting the circuit.
• a first aspect of the present invention is a reference voltage generation circuit that generates a plurality of different voltages as a reference voltage, and converts a difference voltage between the plurality of reference voltages and the analog input voltage into a difference current and outputs the difference current
• a plurality of amplifier circuits, and the output terminals of the amplifier circuits are alternately connected to each other, and the amplifier circuit is composed of a differential amplifier circuit having a cascode output transistor, A switch that is turned on in synchronization with the control clock is provided between both sources of the cascode output transistor.
• a preamplifier circuit including a differential pair input stage, a cascode output transistor, and a load resistor is provided upstream of the amplifier circuit.
• a switch that is turned on in synchronization with the control clock is provided between both sources of the code output transistor.
• a second aspect of the present invention is an analog-to-digital converter having a folding circuit that generates a predetermined number of folding waveforms, wherein the folding circuit is based on a plurality of different voltages.
• a reference voltage generation circuit for generating a voltage, and a plurality of amplifier circuits for converting a difference voltage between the plurality of reference voltages and the analog input voltage into a difference current and outputting the difference current, and outputting an output terminal of the amplifier circuit Are connected alternately, and the amplifier circuit is composed of a differential amplifier circuit having a cascode output transistor, and a switch that is turned on in synchronization with a control clock is provided between both sources of the cascode output transistor. ing.
• the reset switch is provided at the node on the source side of the cascode transistor.
• the output differential amplitude can be suppressed without adding the parasitic capacitance of the switch to the differential current output of the amplifier circuit.
• FIG. 1 is a circuit diagram of a general folding circuit.
• FIG. 2 is a circuit diagram of an amplifier circuit.
• FIG. 3 is an input / output characteristic diagram of an amplifier circuit.
• FIG. 4 is a folding waveform diagram.
• FIG. 5 is a circuit diagram showing a differential amplifier circuit with a reset switch.
• FIG. 6 is a block diagram showing a configuration example of a parallel folding AD converter according to the first embodiment of the present invention.
• FIG. 7 is a circuit diagram showing an example of the physical configuration of the lower bits of the parallel folding AD converter of FIG. 6.
• FIG. 8 is a diagram showing a folded waveform of the output of the distributed amplifier circuit in the first embodiment.
• FIG. 9 is a circuit diagram showing a configuration example of a differential distributed amplifier circuit.
• FIG. 10 is a diagram showing an interpolation waveform by the interpolation circuit in the first embodiment.
• FIG. 11 is a diagram showing a differential distributed amplifier circuit output when there is no reset switch.
• FIG. 12 is a diagram showing an output of the differential distributed amplifier circuit when there is a reset switch.
• FIG. 13 is a block diagram showing a configuration example of a cascade-type folding AD converter according to a second embodiment of the present invention.
• FIG. 14 is a circuit diagram showing an example of the physical configuration of the lower bits of the cascade-type folding AD converter of FIG.
• FIG. 15 is a diagram showing a folded waveform of the dispersion amplifier circuit output in the second embodiment.
• FIG. 16 is a diagram showing an interpolation waveform by an interpolation circuit in the second embodiment.
• FIG. 17 is a diagram showing a circuit example of a first-stage preamplifier circuit in the second embodiment.
• '2nd distributed amplifier circuit group 144 ... Reset switch, 145, 146 ... Cascode transistor (NMOS ⁇ transistors), NT1304, NT1310 ... Reset switch, NT1305, NT130 5, NT1311, ⁇ 1312 De transistor.
• FIG. 6 is a block diagram showing a configuration example of the parallel folding AD converter according to the first embodiment of the present invention.
• Figure 7 shows the specifics of the lower bits of the parallel folding AD converter of Figure 6. It is a circuit diagram which shows an example of a structure.
• the folding AD converter 100 includes a track hold (T / H) circuit 110, a reference voltage generation circuit 120, a preamplifier circuit group 130, and a distributed amplifier circuit group 140. , A load resistance group 150, a buffer group 160, a lower side interpolation circuit 170, an upper side master comparator latch group 180, and a lower side master comparator latch group 190.
• the load resistance group 150 is included in the distributed amplifier circuit group 140
• the buffer group 160 is included in the interpolation circuit 170.
• the track hold circuit 110 has a function of stopping the change of the input signal Vin in synchronization with the control clock signal CLK in the input stage.
• the track hold circuit 110 outputs a track when the clock signal CLK is high and outputs a hold when the clock signal CLK is low.
• the output of the track hold circuit 110 is supplied in parallel to the non-inverting input (+) of each differential amplifier circuit of the preamplifier circuit group 130.
• the reference voltage generation circuit 120 has a ladder resistor 121.
• the ladder resistor 121 includes a plurality of resistors Rl 101 to R1124 connected in cascade between a supply terminal for the maximum reference voltage VRT and a supply terminal for the minimum reference voltage VRB. Nodes between two resistors connected in series REF;! ⁇ REF1 and multiple reference voltages whose values change sequentially from the two supply terminals 1 ⁇ , ⁇ 1 ⁇ 1, ⁇ 1 ⁇ 2, ⁇ 1 ⁇ 3 , '' ', VR12 is output.
• the preamplifier circuit group 130 includes a plurality of, for example, twelve differential amplifier circuits 1301 to 1312.
• the plurality of differential amplifier circuits 1301 to 13013 compares the input voltage Vin with the reference voltages VR1 to VR12. Then, current is output to the distributed amplifier circuit group 140 according to the difference between the input voltage Vin and the reference voltage VR;! To VR12 (current is drawn from the output terminal).
• the distributed amplifier circuit group 140 has a plurality of, for example, twelve differential distributed amplifier circuits 1401 to 1412.
• Each differential distributed amplifier circuit 1401 ⁇ ; 1412 corresponds to the corresponding differential amplifier circuit 1301 ⁇ ; 1312 of the preamplifier circuit group 130, the negative output of the pre-amplifier circuit group 13012 is a non-inverting input terminal (+), and the positive output is an inverting input terminal.
• AVinl in FIG. 8 is the input dynamic range of the differential distributed amplifier circuit. This linear range is divided into the first, fifth, and ninth differential distributed amplifier circuits 1401, 1
• the first folded waveform WV1 with a degree degree of 3 is generated.
• a third folded waveform WV3 having a diderly number of 3 is generated by superimposing the third, seventh, and eleventh differential dispersion amplifier circuits 1403, 1407, and 1411.
• a fourth folded waveform WV4 having a diary number of 3 is generated by superimposing the fourth, eighth, and twelfth differential dispersion amplifier circuits 1404, 1408, and 1411 on each other.
• FIG. 9 is a circuit diagram showing a configuration example of the differential distributed amplifier circuits 1401 to 1412.
• the differential distributed amplifier circuit in FIG. 9 is configured by NMOS transistors NT141 to NT146.
• the sources of the NMOS transistors NT141 and NT142 constituting the differential pair are connected to each other, the connection point is connected to the drain of the NMOS transistor NT143, and the source of the NMOS transistor NT143 is connected to the reference potential VSS.
• the gate of the NMOS transistor 141 is connected to the signal (voltage) VIP supply line
• the gate of the NMOS transistor NT142 is connected to the signal (voltage) VOP supply line
• the gate of the NMOS transistor NT143 is supplied with the bias signal BAIS. Connected to line.
• This NMOS transistor NT143 functions as a current source.
• the node N1 is formed by the connection point.
• the source of the NMOS transistor NT144 is connected to the drain of the NMOS transistor NT142, and a node N2 is formed by the connection point.
• the gate of the NMOS transistor NT144 is connected to a supply line of a clock signal CLK that is set to a high level during tracking and to a low level during honored.
• the source of NMOS transistor NT145 is connected to node Nl (the drains of NMOS transistors NT141 and NT144), and the drain is connected to a predetermined load resistance element of load resistance group 150.
• the source of the NMOS transistor NT146 is connected to the node N2 (the drain of the NMOS transistor NT142, the source of NT144), and the drain is connected to another predetermined load resistance element of the load resistor group 150.
• NMOR transistors NT145 and NT146 are connected to the power supply potential VDD
• the load resistance group 150 has one end connected to the load resistance elements R151 to R158 connected to the power supply potential VDD, one end connected to the other end of each load resistance element R151 to 158, and the other end side to a distributed amplification circuit.
• the group 140 differential dispersion amplifier circuits 1401 to 1401 have output lines L1 to L8 to which one of the two outputs of 1412 is connected.
• the output line L1 includes a first output of the first differential dispersion amplifier circuit 1401, a second output of the fifth differential dispersion amplifier circuit 1405, and a first output of the ninth differential dispersion amplifier circuit 1409. 1 output is connected to the output line L2, the second output of the first differential dispersion amplifier circuit 1401, the first output of the fifth differential dispersion amplifier circuit 1405, the ninth differential dispersion amplifier circuit The 1409's second output is connected.
• the output line L3 includes the first output of the second differential dispersion amplifier circuit 1402, the second output of the sixth differential dispersion amplifier circuit 1406, and the second output of the tenth differential dispersion amplifier circuit 1410. 1 output is connected to the output line L4, the second output of the second differential distributed amplifier circuit 1402, the first output of the sixth differential distributed amplifier circuit 1406, the tenth differential distributed amplifier. The second output of circuit 14 10 is connected.
• the output line L5 includes the first output of the third differential dispersion amplifier circuit 1403, the second output of the seventh differential dispersion amplifier circuit 1407, and the first output of the eleventh differential dispersion amplifier circuit 1411. 1 output is connected to the output line L6, the second output of the third differential dispersion amplifier circuit 1403, the first output of the seventh differential dispersion amplifier circuit 1407, the eleventh differential dispersion amplifier The second output of circuit 14 11 is connected!
• the output line L7 includes the first output and the eighth difference of the fourth differential dispersion amplifier circuit 1404.
• the second output of the dynamic dispersion amplifier circuit 1408 is connected to the first output of the twelfth differential dispersion amplifier circuit 1412, and the second output of the fourth differential dispersion amplifier circuit 1404 is connected to the output line L8.
• the first output of the eighth differential dispersion amplifier circuit 1408 and the second output of the twelfth differential dispersion amplifier circuit 14 12 are connected.
• the buffer group 160 has a plurality of, for example, four buffers 161 (II) to 164 (14).
• the input terminal (one) side of the NOFFA 161 is connected to the output line L1 of the load resistance group 150, and the input terminal (+) side is connected to the output line L2 of the load resistance group 150!
• the input terminal (one) side of the noffer 162 is connected to the output line L3 of the load resistance group 150, and the input terminal (+) side is connected to the output line L4 of the load resistance group 150!
• the input terminal (one) side of NOFFA 163 is connected to the output line L5 of the load resistance group 150, and the input terminal (+) side is connected to the output line L6 of the load resistance group 150!
• the input terminal (-) side of the FF 164 is connected to the output line L7 of the load resistance group 150, and the input terminal (+) side is connected to the output line L8 of the load resistance group 150!
• the interpolation circuit 170 is connected in series between the resistor elements R1701 to R1716 connected in series between the first output and the second output of the buffer 161, and between the second output and the first output of the buffer 161. It is composed of resistance elements R1717 to R1732 connected to!
• the first output of the buffer 162 is connected to the connection point between the resistance elements R1728 and R1729, and the second output of the buffer 162 is connected to the connection point between the resistance elements R1712 and R1713.
• the first output of the buffer 163 is connected to the connection point between the resistance elements R1724 and R1725, and the second output of the buffer 163 is connected to the connection point between the resistance elements R1708 and R1709.
• the first output of the buffer 164 is connected to the connection point between the resistance elements R1720 and R1721, and the second output of the buffer 164 is connected to the connection point between the resistance elements R1704 and R1705.
• the interpolation circuit 170 performs resistance division as shown in FIG. 16 interpolation waveforms are output.
• the upper master “comparator” latch group 180 compares the differential outputs of the distributed amplifier circuit group 140 and outputs a binary signal having a predetermined number of bits.
• the lower master's comparator 190 has 16 master's controllers 1901 to 1916, compares the output of the interpolation circuit 170, and outputs a binary signal. [0049] Next, the operation of the above configuration will be described.
• the differential input signal Vin is tracked when the clock signal CLK is at a high level by the track hold circuit 110, and held when the clock signal CLK is at a low level. Is input to the preamplifier circuit group 130.
• the preamplifier circuits 1301 to 1312 of the preamplifier circuit group 130 compare with the differential reference potential divided by the resistance in the reference voltage generation circuit 120, amplify and output.
• Pre-amplifier circuits 1301 to 13012 receive differential output signals, and differential distributed amplifier circuits 1401 to 1412 generate folded waveforms (FIG. 8).
• AVinl in FIG. 8 is the input dynamic range of the differential distributed amplifier circuit.
• the differential distributed amplifier circuits 1401 (first), 1405 (fifth), and 1409 (ninth) By overlapping this linear range with the differential distributed amplifier circuits 1401 (first), 1405 (fifth), and 1409 (ninth), the first folded waveform W VI with degree 3 is generated. To do.
• the 2-6-10th, 3-7-11th, 4-8-12th differential dispersion amplifier circuits are overlapped to generate a total of four folded waveforms.
• the folded waveforms are received by buffers 161 (11), 162 (12), 163 (13), and 164 (14), and 16 interpolation waveforms (Fig. 10) are output by the resistance division interpolation circuit 170 To do.
• Fig. 10 shows the interpolated waveforms generated from the outputs of buffers 161 and 162 (11 and 12). Similarly, noters 162 and 163 (12 and 13), and noters 163 and 164 (13 and 14) Interpolated waveforms are generated by the noffers 164 and 161 (14 and II).
• the latch comparator (MCL) receives this signal and outputs a 4-bit digital signal.
• FIG. 11 and FIG. 12 are diagrams showing differential distributed amplifier circuit output waveforms when the switch is not present and the input is changed to REF ;! to REF9 (VR ;! to VR9).
• Reset switch 144 force Synchronized with S track hold clock, at high level h, ie Turns on during tracking, turns off at low level, that is, turns off during holding.
• the differential output during hold is expressed as follows.
• Vhold (Vl-VO) exp (-t / ⁇ ) (* 1)
• Vhold is the output of the differential dispersion amplifier circuit during hold
• VI is the desired output voltage value obtained by multiplying the input by DC gain
• V0 is the initial output voltage value at the moment when the clock switches from track to hold
• ⁇ is a time constant of the amplifier circuit output.
• FIG. 13 is a block diagram showing a configuration example of a cascade-type folding AD converter according to the second embodiment of the present invention.
• FIG. 14 is a circuit diagram showing a physical configuration example of the lower bits of the cascade-type folding AD converter of FIG.
• the AD converter 100A of the second embodiment is different from the AD converter 100 of the first embodiment in that the reference voltages generated by the reference voltage generation circuit 120A are nine VRs !! to VR9,
• the first distributed resistor group 200 is arranged at the output stage of the first distributed amplifier circuit group 140A as the differential distributed amplifier circuit 1401 ⁇ ; 1409 of the first distributed amplifier circuit group 140A.
• Nofer group 210 is arranged, the first interpolation circuit 220 is arranged at the output stage of the first buffer group 210, the second distributed amplifier circuit group 230 is arranged at the output stage of the first interpolation circuit 220, and the second dispersion
• the second load resistance element group 150A is arranged at the output stage of the amplifier circuit group 230, the second buffer group 160A and further the second interpolation circuit 170A are arranged at the output stage of the second load resistance group 150A.
• the second load resistance group 150A has the same configuration as the load resistance group 150 of the first embodiment
• the second buffer group 160A is the same as the buffer group 160 of the first embodiment.
• the second interpolation circuit 170A has the same configuration as the interpolation circuit 170 of the first embodiment.
• the first load resistance group 200 has one end connected to the other end of each of the load resistance elements R20;! To 208, and one end connected to the power supply potential VDD.
• the differential distributed amplifier circuits 1401 to 1401 of the amplifier circuit group 140A; one of the two outputs of 1409 is connected to output lines L11 to L16.
• the output line L11 includes a first output of the first differential dispersion amplifier circuit 1401, a second output of the fifth differential dispersion amplifier circuit 1405, and a second output of the ninth differential dispersion amplifier circuit 1409. 1 output is connected to the output line L12, the second output of the first differential dispersion amplifier circuit 1401, the first output of the fifth differential dispersion amplifier circuit 1405, the ninth differential dispersion amplifier circuit The 1409's second output is connected.
• the output line L13 includes the first output of the second differential dispersion amplifier circuit 1402, the second output of the sixth differential dispersion amplifier circuit 1406, and the second output of the tenth differential dispersion amplifier circuit 1410. 1 output is connected to the output line L14, the second output of the second differential dispersion amplifier circuit 1402, the first output of the sixth differential dispersion amplifier circuit 1406, the tenth differential dispersion amplifier The second output of circuit 14 10 is connected.
• the output line L15 includes a first output of the third differential dispersion amplifier circuit 1403, a second output of the seventh differential dispersion amplifier circuit 1407, and a second output of the eleventh differential dispersion amplifier circuit 1411. 1 output is connected to the output line L16, the second output of the third differential dispersion amplifier circuit 1403, the first output of the seventh differential dispersion amplifier circuit 1407, the eleventh differential dispersion amplifier The second output of circuit 14 11 is connected!
• the first buffer group 210 has a plurality of, for example, three buffers 21;! -213.
• the input terminal (one) side of the notaper 201 is connected to the output line L13 of the first load resistor group 200, and the input terminal (+) side is connected to the output line L14 of the load resistor group 150.
• the input terminal (one) side of the noffer 212 is connected to the output line L15 of the first load resistance group 200, and the input terminal (+) side is connected to the output line L15 of the first load resistance group 200! /.
• the input terminal (one) side of the noffer 213 is connected to the output line LI1 of the first load resistance group 200, and the input terminal (+) side is connected to the output line L12 of the first load resistance group 200.
• the first interpolation circuit 220 includes a resistance element R220;! To R2212 connected in series between the first output and the second output of the buffer 213, and the second output and the first output of the buffer 213.
• the resistor elements R2213 to R2224 are connected in series between them.
• the first output of the buffer 212 is connected to the connection point between the resistance elements R2204 and R2205, and the second output of the buffer 212 is connected to the connection point between the resistance elements R2216 and R2217. Is connected to the connection point between the resistance elements R2208 and R2209, and the second output of the buffer 211 is connected to the connection point between the resistance elements R2220 and R2221.
• the second distributed amplifier circuit group 230 includes twelve differential distributed amplifier circuits 230;! To 2312.
• the input terminal (one) side of the differential distributed amplifier circuit 2301 is connected to the second output of the buffer 213, and the input terminal (+) side is connected to the first output of the buffer 213.
• the input terminal (one) side of the differential distributed amplifier circuit 2302 is connected to the connection point between the resistance elements R2211 and R2212, and the input terminal (+) side is connected to the connection point between the resistance elements R2223 and R2224.
• the input terminal (one) side of the differential distributed amplifier circuit 2303 is connected to the connection point between the resistance elements R2210 and R2211, and the input terminal (+) side is connected to the connection point between the resistance elements R2222 and R2223.
• the input terminal (one) side of the differential distributed amplifier circuit 2304 is connected to the connection point between the resistance elements R2209 and R2210, and the input terminal (+) side is connected to the connection point between the resistance elements R2221 and R2222.
• the input terminal ( ⁇ ) side of the differential distributed amplifier circuit 2305 is connected to the connection point between the resistance elements R2208 and R2209, and the input terminal (+) side is connected to the connection point between the resistance elements R2220 and R2221.
• the input terminal (one) side of the differential distributed amplifier circuit 2306 is connected to the connection point between the resistance elements R2207 and R2208, and the input terminal (+) side is connected to the connection point between the resistance elements R2219 and R2220.
• the input terminal (one) side of the differential distributed amplifier circuit 2307 is connected to the connection point between the resistance elements R2206 and R2207, and the input terminal (+) side is connected to the connection point between the resistance elements R2218 and R2219. ing.
• the input terminal (one) side of the differential distributed amplifier circuit 2308 is connected to the connection point between the resistance elements R2205 and R2206, and the input terminal (+) side is connected to the connection point between the resistance elements R2217 and R2218.
• the input terminal ( ⁇ ) side of the differential distributed amplifier circuit 2309 is connected to the connection point between the resistance elements R2204 and R2205, and the input terminal (+) side is connected to the connection point between the resistance elements R2216 and R2217.
• the input terminal (one) side of the differential distributed amplifier circuit 2310 is connected to the connection point between the resistance elements R2203 and R2204, and the input terminal (+) side is connected to the connection point between the resistance elements R2215 and R2216.
• the input terminal (one) side of the differential distributed amplifier circuit 2311 is connected to the connection point between the resistance elements R2202 and R2203, and the input terminal (+) side is connected to the connection point between the resistance elements R2214 and R2215.
• the input terminal (one) side of the differential distributed amplifier circuit 2312 is connected to the connection point between the resistance elements R2201 and R2202, and the input terminal (+) side is connected to the connection point between the resistance elements R2213 and R2214.
• the outputs of the differential distributed amplifier circuit 230;! To 2312 of the second distributed amplifier circuit group 230 are the differential distributed amplifier circuits 1401 to 1401 of the first embodiment (FIG. 7) and the load resistor group. Connected in the same relationship as 150 output lines L1 to L8. Therefore, the detailed explanation is omitted here.
• the processing up to the first interpolation circuit 220 is performed in the same manner as in the first embodiment.
• buffer 16;! To 164 receives and outputs the above folded waveform, and outputs 16 interpolated waveforms (Fig. 15) by the quadrant second interpolation circuit 170A using resistors, and latch comparator MCL receives and outputs a 4-bit digital signal.
• VOP AP * Vin (Wed 1)
• V01 Al * VOP (Wed 2)
• V02 A2 * V01 (Wed 3)
• VOP 0 during tracking, and each amplifier circuit output signal V01, V02 also becomes zero.
• the output amplitude of each distributed amplifier circuit can be suppressed and analog settling can be accelerated.
• FIG. 17 is a diagram illustrating a circuit example of a first-stage preamplifier circuit according to the second embodiment.
• the differential amplifier circuit of FIG. 17 includes NMOS transistors NT130 ;! to NT1312 and load resistance elements Routl and Rout2.
• the sources of the NMOS transistors NT1301 and NT1302 constituting the differential pair are connected to each other, the connection point is connected to the drain of the NMOS transistor NT1303, and the source of the NMOS transistor NT1303 is connected to the reference potential VSS.
• the gate of the NMOS transistor 1301 is connected to the signal (voltage) VIP supply line
• the gate of the NMOS transistor NT1302 is connected to the signal (voltage) REFP supply line
• the gate of the NMOS transistor NT1303 is supplied with the bias signal BAIS. Connected to line.
• This NMOS transistor NT1303 functions as a current source. Are connected, and a node Ni l is formed by the connection point.
• the source of the NMOS transistor NT1304 is connected to the drain of the NMOS transistor NT1302, and a node N12 is formed by the connection point.
• the gate of the NMOS transistor NT1304 is connected to a supply line of a clock signal CLK which is set to a high level during tracking and set to a low level during holding.
• the source of the NMOS transistor NT1305 is connected to the node Ni l (the drains of the NMOS transistors NT1301 and NT1304), and the drain is connected to the load resistor Routl.
• the source of the NMOS transistor NT1306 is connected to the node N12 (the drain of the NMOS transistor NT1302, the source of the NT1304), and the drain is connected to the load resistance element Rout2.
• the gates of the NMOR transistors NT1305 and NT1306 are connected to the power supply potential VDD.
• the sources of the NMOS transistors NT1307 and NT1308 constituting the differential pair are connected to each other, the connection point is connected to the drain of the NMOS transistor NT1309, and the source of the NMOS transistor NT13039 is connected to the reference potential.
• the gate of the NMOS transistor 1307 is connected to the supply line of the signal (voltage) PEFN, the gate of the NMOS transistor NT1308 is connected to the supply line of the signal (voltage) VIN, and the gate of the NMOS transistor NT1309 is connected to the bias signal BAIS. Connected to supply line.
• This NMOS transistor NT1309 functions as a current source. Are connected, and a node N13 is formed by the connection point.
• the source of the NMOS transistor NT1310 is connected to the drain of the NMOS transistor NT1308, and a node N14 is formed at the connection point!
• the gate of the NMOS transistor NT1310 is connected to a supply line of a clock signal CLK that is set to a high level during tracking and set to a low level during honored.
• the source of the NMOS transistor NT1311 is connected to the node N13 (the drains of the NMOS transistors NT1307 and NT1310), and the drain is connected to the load resistor Routl. Drain, NT1310 source) and drain connected to load resistor Rout2 Has been.
• the gates of the NMOR transistors NT131 1 and NT1312 are connected to the power supply potential VDD.
• Cascode transistors NT1305, NT1306, NT13 1 1 and 1312 are inserted in the differential pair VOP and VON, and reset switches NT1304 and NT1310 are inserted in the source side of the differential pair VOP and VON.
• the clock signal CLK force is turned on at the S noise level, that is, on during tracking, and turned off at the low level, that is, held.
• a folding AD converter by adding a switch to the source side of the cascode transistor in the amplifier circuit, the response of the amplifier circuit that attaches the parasitic capacitance of the switch to the output node can be improved.
• Cascade-type folding AD converters are provided that enable high-speed operation by introducing a switch only in the first stage preamplifier circuit.
• the force S described as an example of the low-order 4-bit converter is not limited to this configuration, and the present invention can be applied to a 4-bit or higher converter.

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• 2006
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