Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
  • H04N25/42—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
  • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
  • H04N25/621—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
  • H04N25/622—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming by controlling anti-blooming drains
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N25/73—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors using interline transfer [IT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/15—Charge-coupled device [CCD] image sensors
  • H10F39/158—Charge-coupled device [CCD] image sensors having arrangements for blooming suppression
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/15—Charge-coupled device [CCD] image sensors
  • H10F39/153—Two-dimensional or three-dimensional array CCD image sensors
  • H10F39/1534—Interline transfer

Definitions

• the invention relates generally to the field of charge-coupled devices and, more particularly, to providing more than one substrate voltage reference for optimum anti-blooming protection in pixel summing modes.
• FIG. 2 shows an interline charge-coupled device (CCD) 100. It includes an array of photodiodes 105 connected to vertical CCD 110 (VCCD). The image readout process begins by transferring charge from the photodiodes 105 to the adjacent VCCDs 110. Next, one line at a time is transferred into the horizontal CCD (HCCD) 115. The HCCD serially transfers charge to an output charge-sensing amplifier 120.
• Figure 3 shows a cross section of one interline CCD pixel (with portions of adjacent pixels shown for clarity) of Fig. 2. The photodiode 105 collects photo-generated charge. The charge is confined in the photodiode 105 by a surface pinning p+ implant 230 and a vertical overflow drain 215.
• Adjacent to the photodiode 105 is the VCCD buried channel 200 built in a p-type well 205 on an n-type substrate 210. Transfer of charge through the VCCD 110 is controlled by the gate 220. The VCCD 1 10 is shielded from light by an opaque metal layer 225.
• the overflow drain 215 is a lightly doped region that has a high degree of manufacturing process variability. The variability is so great that the voltage applied to the substrate 210 must by changed from one image sensor to the next.
• the substrate voltage controls how much charge can be held in the photodiode 105. If the charge capacity of the photodiode is too high, then a bright spot of light will generate more charge than can be held in the VCCD 110. This causes VCCD blooming. If the charge capacity is too low, then the output amplifier 120 will never reach saturation.
• the substrate voltage is adjusted for each individual image sensor to optimize the photodiode charge capacity for the best compromise between anti-blooming protection and saturation signal level. In the past, image sensors have been fabricated with a substrate reference voltage generation circuit.
• FIG. 1 This circuit contains four fuses, Fl through F4, across a set of resistors in series, Rl through R4. By blowing one or more of the fuses, 16 possible reference voltage combinations Vl are possible. This reference voltage is then connected to the image sensor substrate for optimum anti-blooming and saturation signal.
• resistors may be substituted by MOSFET transistors with the gates tied to the transistor source or drain.
• interline CCDs are used to sum pixels.
• a simple example is shown in Figure 4.
• An interline CCD 100 is shown where two rows of charge from the VCCD 110 is summed into the HCCD 115. This summing process may cause the HCCD 1 15 charge capacity to be exceeded and result in horizontal charge blooming. It is also possible to sum pixels together in the VCCD to increase frame rates. The pixel summing in the VCCD may exceed the VCCD charge capacity.
• a well-known solution to prevent blooming of the VCCD or HCCD when summing pixels is to further increase the substrate voltage when in pixel summing mode.
• Figure 5 illustrates the photodiode 105 channel potential vs. depth in the silicon wafer.
• the pinning layer 230 holds the potential at OV.
• the n-type photodiode 105 and lightly doped overflow drain 215 form a potential barrier between the photodiode and substrate 210.
• the substrate voltage is set to VSubl , the photodiode capacity is larger at ⁇ VB.
• the image sensor changes to pixel summing mode, then the substrate voltage is increased to VSub2 which lowers the photodiode charge capacity to ⁇ VA.
• the problem is how to generate a second reference voltage.
• the obvious solution would be to place an entire second reference voltage generator on the image sensor like that shown in Figure 1. This is undesirable because adding more fuses to the image sensor requires extra bond pads for a wafer probe tester to be able to set the fuses. Even if laser trimmed fuses are used, the additional fuses decrease the manufacturing yield of the sensor and increases the chance of debris from the fuse setting process contaminating the pixel array. Therefore, a new circuit is needed that does not increase the number of fuses and can supply more than one reference voltage for pixel summing image sensors.
• the invention resides in an image sensor comprising (a) plurality of pixels for converting incident photons into electrical charge; (b) an overflow drain to draw off excess charge from at one or more of the pixels; (c) a mechanism for summing charge from two or more of the pixels; (d) a first network of resistive devices generating a first overflow drain voltage where at least one of the resistive devices has, in parallel, a fuse that can be opened in response to an external stimulus to provide the optimum overflow drain voltage for pixel anti-blooming protection and saturation signal level for when a plurality of pixels are summed together; and (e) a second network of resistive devices connected to the first network of resistive devices generating a second overflow drain voltage where the second overflow drain voltage is a fraction of the first overflow drain voltage and the second overflow drain voltage provides the optimum overflow drain voltage for pixel anti-blooming and
• the present invention provides the advantage of a simple image sensor substrate voltage circuit that can supply multiple substrate reference voltages without increasing the number of programmable fuse elements.
• Fig. 1 is a schematic of a prior art substrate voltage reference circuit
• Fig. 2 is a top view of a prior art interline CCD
• Fig. 3 is a cross section of a pixel Fig. 2;
• Fig. 4 is a top view of a prior art interline CCD illustrating the summing of two pixels
• Fig. 5 is a graph of an interline CCD photodiode potential vs. silicon depth
• Fig. 6 is a top view of an image sensor of the present invention
• Fig. 7 is a cross section of Fig. 6;
• Fig. 8 is a graph illustrating the relationship between optimum substrate voltage for two pixel summing and optimum substrate voltage for no pixel summing
• Fig. 9 is a schematic illustrating a dual substrate reference voltage circuit of the present invention
• Fig. 10 is a schematic illustrating a multiple substrate reference voltage circuit of the present invention.
• Fig. 1 1 is a schematic illustrating a multiple substrate reference voltage circuits using resistors of the present invention
• Fig. 12 is a schematic illustrating a multiple substrate reference voltage circuit using FETs
• Fig. 13 is a schematic of a multiple substrate reference voltage circuit using anti-fuses of the present invention
• Fig. 14 is a schematic of a CMOS image sensor pixels with charge summing capability of the present invention
• Fig. 15 is a camera imaging system using and image sensor having multiple substrate reference voltages of the present invention.
• FIG. 6 shows an interline CCD image sensor 300 of the present invention with an integrated substrate reference voltage circuit 360 of the invention on the same silicon substrate.
• the image sensor 300 has an array of pixels 304 consisting of a photodiode 305, which collects charge in response to incident light (i.e., photons), adjacent to a vertical CCD shift register 310 that receives charge from the photodiodes.
• a horizontal CCD shift register 315 receives charge from the vertical CCD shift registers 310 and serially transfers charge to an output charge sensing node 320.
• the vertical CCD 310 is capable of summing together charge from two or more photodiodes 305 within the vertical CCD 310.
• Figure 7 shows a horizontal cross section of one of the pixels 304. It consists of an n-type photodiode 305 under a p-type surface pinning layer 330 and above the lightly doped vertical overflow drain 316 in the n-type substrate 317.
• the opaque light shield 303 prevents the CCD shift register buried channel 302 from being sensitive to light.
• An equivalent image sensor can have all of the silicon doping polarities (n-type and p-type) exchanged.
• FIG. 8 shows the relationship between the optimum substrate voltage for two pixel summing vs. the optimum substrate voltage for no pixel summing. It is a straight line intersecting the origin.
• Figure 9 shows a circuit that will produce a second voltage V2 that can reproduce the straight line in Figure 8.
• V2 is the optimum substrate voltage for the full resolution un-summed image
• Vl is the optimum substrate voltage for two pixel summing.
• the current flowing out of the VDD power supply is given by:
• VDD i -
• Fl through F4 are values of 1 or 0 depending if the fuse Fl through F4 is conducting current or is blown.
• the Vl and V2 output voltages are given by:
• V ⁇ VDD - i(R 5 + F 1 R 1 + F 2 R 2 )
• V2 R * V ⁇ R 7 + R S
• Vl and V2 have a linear relationship and an intercept through the origin.
• the circuit of Figure 9 uses the same number of fuses as the prior art but provides two reference voltage of exactly the correct value for pixel summing and non-pixel summing modes.
• Interline CCDs are not limited to summing only 2 pixels. It is possible for one sensor to have multiple levels of pixel summing. For example, an image sensor might take full resolution pictures and also have video modes with 2, 4, or 8 pixel summing. Odd numbered pixel summing is also possible such as a color image sensor with the Bayer color filter pattern summing 3x3 (9 pixel) sub- arrays of like colors. All of these pixel-summing modes will need reference voltages on one image sensor.
• the solution is to extend the circuit of Figure 9 to the circuit shown in Figure 10 where another voltage divider operating off the V2 voltage generates a third voltage V3.
• Figure 1 1 shows two variations of the circuit in Figure 10 that can generate a third voltage V3. From, these examples it should be clear how to add an unlimited number of additional voltage dividers to generate more substrate voltage references.
• FIG. 13 shows two CMOS image sensor pixels. There is one photodiode 426 and 423 for each pixel.
• the photodiodes have a surface pinning layer 424 and a vertical overflow drain 422.
• the charge capacity of the photodiodes 426 and 423 is regulated by the overflow drain 422 barrier height that is in turn controlled by the voltage applied to the substrate 421.
• Charge from the photodiode 426 is transferred to a shared floating diffusion 425 by a transfer gate 427 controlled by the signal line 428.
• Charge from the photodiode 423 is transferred to a floating a shared floating diffusion 425 by a transfer gate 414 controlled by the signal line 419.
• Each photodiode signal charge can be read either by transferring independently to the floating diffusion 425 or in a pixel summing operation both transfer gates 414 and 427 are turned on at the same time to sum two pixels together.
• the floating diffusion 425 is reset by transistor 413 controlled by signal line 41 1.
• Transistor 417 is preferably a part of a source follower connected to a power line 412.
• Transistor 418 is a row select transistor turned on by signal line 420 to connect the source follower to the signal output line 416.
• CMOS pixel structure allows two-pixel summing or no pixel summing read out modes. It can also be extended to allow for 3 or 4 pixel summing options. In the case of pixel summing is it desirable to use the overflow drain reference voltage circuit invention to supply reference voltages for each of the pixel summing modes.
• Figure 15 shows a camera imaging system 471 (preferably a digital camera) employing an image sensor 470 with the integrated overflow drain voltage reference circuit of the present invention.
• the present invention permits the digital camera system 471 to operate in full resolution picture taking modes as well as lower resolution pixel summed motion video imaging modes with optimal anti-blooming protection and saturation signal level.

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• Engineering & Computer Science (AREA)
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• Signal Processing (AREA)
• Transforming Light Signals Into Electric Signals (AREA)
• Solid State Image Pick-Up Elements (AREA)

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• 2006
  • 2006-07-19 US US11/488,961 patent/US7508432B2/en active Active
• 2007
  • 2007-07-18 WO PCT/US2007/016280 patent/WO2008011064A2/en not_active Ceased
  • 2007-07-18 EP EP07810576.4A patent/EP2041958B1/en active Active
  • 2007-07-18 JP JP2009520819A patent/JP4982562B2/ja active Active

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