Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/08—Address circuits; Decoders; Word-line control circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
  • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
  • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/689—Vertical floating-gate IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/693—Vertical IGFETs having charge trapping gate insulators
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/681—Floating-gate IGFETs having only two programming levels
  • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection

Definitions

• Nonvolatile semiconductor memory and driving method thereof are nonvolatile semiconductor memory and driving method thereof.
• the present invention relates to a nonvolatile semiconductor memory and a driving method thereof.
• a flash memory cell array having a memory cell force using the sidewall of the island-like semiconductor layer uses a diffusion layer on a source line or a source surface.
• the diffusion layer has a higher resistance than metal.
• a current flows through the resistor, a potential difference is generated. Therefore, the voltage of the source diffusion layer of the memory cell at the time of writing becomes higher than 0V, the voltage between the source and the drain decreases, the current flowing between the source and the drain decreases, and the writing speed decreases.
• the voltage of the source diffusion layer of the memory cell is higher than 0 V, and the source The voltage between the drain and drain decreases, the current flowing between the source and drain decreases, and the readout speed decreases.
• Patent Document 1 Japanese Patent Application Laid-Open No. 8-148587
• Non-Patent Document 1 Howard Pein et al. IEEE Electron Device Letters, Vol.14, No.8, pp.415-417, 1993
• an object of the present invention is to provide a nonvolatile semiconductor memory such as a memory cell card that uses the sidewalls of the island-like semiconductor layer to avoid a decrease in writing speed and reading speed.
• the present invention has the following configuration.
• the source region, the channel region, and the drain region are formed in this order from the substrate side, and further, the charge storage stack formed outside the channel region via the gate insulating film.
• a memory cell having a control gate formed so as to cover the charge storage layer through an insulating layer outside the charge storage layer.
• the nonvolatile memory arranged in a matrix of n rows and m columns on the substrate A semiconductor memory,
• a plurality of source lines wired in the column direction so as to interconnect the source regions of the memory cells aligned in the column direction of the matrix;
• a plurality of parallel bit lines wired in the column direction so as to connect the drain regions of the memory cells aligned in the column direction;
• a plurality of gate lines wired in the row direction so as to interconnect the control gates of the memory cells aligned in the row direction substantially perpendicular to the column direction;
• a non-volatile semiconductor memory configured to inject charges into a charge storage layer using hot electron injection is provided.
• the source region, the channel region, and the drain region are formed in this order from the substrate side, and further, the charge formed outside the channel region via the gate insulating film
• a memory cell having an accumulation layer and a control gate formed outside the charge accumulation layer so as to cover the charge accumulation stack via an insulating layer is formed on the substrate by n rows m.
• Non-volatile semiconductor memory arranged in a matrix of columns,
• a plurality of parallel bit lines wired in the column direction so as to connect the drain regions of the memory cells aligned in the column direction;
• a plurality of gate lines wired in the row direction so as to interconnect the control gates of the memory cells aligned in the row direction substantially perpendicular to the column direction;
• a non-volatile semiconductor memory configured to inject charges into a charge storage layer using hot electron injection is provided.
• the source region, the channel region, and the drain region are formed in this order from the substrate side, and the charge formed outside the channel region via the gate insulating film.
• Memory cells having a storage layer and a control gate formed on the outside of the charge storage layer so as to cover the charge storage stack via an insulating layer are arranged in a matrix of n rows and m columns on the substrate.
• a plurality of source lines wired in the column direction so as to interconnect the source regions of the memory cells aligned in the column direction of the matrix;
• a plurality of gate lines wired in the row direction so as to interconnect the control gates of the memory cells aligned in the row direction substantially perpendicular to the column direction;
• a common source line that is wired one by one every p rows (P n) of the matrix, the common source line being formed of metal that interconnects the source lines;
• a non-volatile semiconductor memory is provided.
• the source region, the channel region, and the drain region are formed in this order on the substrate side force, and further, the charge is formed outside the channel region via a gate insulating film.
• Memory cells having a storage layer and a control gate formed outside the charge storage layer so as to cover the charge storage layer via an insulating layer are arranged in a matrix of n rows and m columns on the substrate.
• a plurality of gate lines wired in the row direction so as to interconnect the control gates of the memory cells aligned in the row direction substantially perpendicular to the column direction;
• a non-volatile semiconductor memory is provided.
• 0V or positive first voltage is applied to the selected bit line, 0V is applied to the non-selected bit line, a positive second voltage is applied to the selected control gate line, and 0V is applied to the non-selected control gate line.
• a positive first voltage is applied to the selected control gate line, 0 V is applied to the non-selected control gate line, 0 V is applied to the source line or the source surface and the common source line, and a positive voltage is applied to the selected bit line.
• a method of reading from a non-volatile semiconductor memory is provided in which a selected memory cell is read by applying a second voltage.
• a positive first voltage is applied to the bit line and the source line or the source surface and the common source line, and 0V is applied to the control gate line, and the FN (Fowler-Nordheim) tunnel current is used to make a ⁇ cell.
• a non-volatile semiconductor memory erasing method for discharging charges from the charge storage layer.
• a positive first voltage is applied to the bit line and the source line or the source surface and the common source line, 0 V is applied to the selected control gate line, and a positive second voltage is applied to the non-selected control gate line.
• the source line can be reduced in resistance, and the memory cell can be written at the time of writing.
• 0V can be applied to the source diffusion layer, sufficient voltage can be applied between the source and drain, sufficient current can flow between the source and drain, and a decrease in writing speed can be avoided.
• 0 V can be applied to the source diffusion layer of the memory cell, a sufficient voltage can be applied between the source and the drain, and a sufficient current can flow between the source and the drain.
• a decrease in reading speed can be avoided.
• the nonvolatile semiconductor memory according to the present invention includes a number of island-like semiconductor layers formed on a semiconductor substrate.
• the island-like semiconductor layer includes a drain diffusion layer formed thereon, a source diffusion layer formed therebelow, and a channel region on a sidewall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulating film.
• a non-volatile semiconductor memory cell having a control gate formed on the charge storage layer.
• the nonvolatile semiconductor memory has a structure in which the nonvolatile semiconductor memory cells are arranged in a matrix and bit lines connected to the drain diffusion layer are wired in the column direction.
• the nonvolatile semiconductor memory cells are arranged in a matrix, bit lines connected to the drain diffusion layer are wired in the column direction, and control gate lines are arranged in the row direction. It is also possible to adopt a structure in which the source lines connected to the source diffusion layer are wired in the column direction. Further, in this nonvolatile semiconductor memory, a common source line made of metal is wired in the row direction, one for each predetermined number (eg, 64) of control gate lines. At this time, the common source line is used as a source. A structure connected to a line can also be used.
• the nonvolatile semiconductor memory cells are arranged in a matrix on the source surface formed of the diffusion layer, and the bit lines connected to the drain diffusion layer are arranged in columns. It is also possible to adopt a structure in which the control gate lines are wired in the row direction. Furthermore, in this nonvolatile semiconductor memory, a common source line made of metal is wired in the row direction, one for each predetermined number (eg, 64) of control gate lines. At this time, this common source line is used as a source. A structure connected to the surface can also be used.
• 0V or a positive first voltage is applied to the selected bit line
• 0V is applied to the non-selected bit line
• a positive second voltage is applied to the selected control gate line.
• a positive first voltage is applied to the selected control gate line, 0V is applied to the non-selected control gate line, and 0V is applied to the source line or the source surface and the common source line.
• the selected memory cell can be read by applying a positive second voltage to the selected bit line.
• a positive first voltage is applied to the bit line and the source line or the source surface and the common source line, and 0 V is applied to the control gate line, thereby utilizing the FN tunnel current.
• the charge storage layer force of all memory cells can also release charges.
• a positive first voltage is applied to the bit line and the source line or the source surface and the common source line, 0 V is applied to the selected control gate line, and the non-selected control gate line is applied.
• a positive second voltage charges can be discharged from the charge storage layer of the memory cell connected to the control gate line selected using the FN tunnel current.
• FIGS. 1, 2, 3, and 4 The layout and cross-sectional structure of the nonvolatile semiconductor memory according to the present invention are shown in FIGS. 1, 2, 3, and 4, respectively.
• a source line 2 and a source diffusion layer 3 are formed on a silicon oxide film 1, an island-like semiconductor layer 4 is formed thereon, and a drain is formed on the island-like semiconductor layer 4.
• the rain diffusion layer 5 is formed, and the charge storage layer 6 formed through the gate insulating film is formed on the channel region of the side wall sandwiched between the drain diffusion layer 5 and the source diffusion layer 3, and the charge storage layer 6 is
• a control gate 7 is formed to form a memory cell.
• a bit line 8 is formed on the drain diffusion layer.
• a common source line 9 having a metal force assigned to a row is formed on the source line for every predetermined number of control gate lines (here, every 64 lines).
• a source surface 10 and a source diffusion layer 3 are formed on a silicon oxide film 1, an island-like semiconductor layer 4 is formed thereon, and a drain diffusion is formed above the island-like semiconductor layer 4.
• Layer 5 is formed, and a charge storage layer 6 formed through a gate insulating film is formed on the channel region of the side wall sandwiched between the drain diffusion layer 5 and the source diffusion layer 3, and is controlled on the charge storage layer 6
• a gate 7 is formed to form a memory cell.
• a bit line 8 is formed on the drain diffusion layer.
• a common source line 9 having a metal force assigned to a row is formed on the source every predetermined number of control gate lines (here, every 64 lines).
• FIG. 9 is an XX ′ cross-sectional view of the SOI substrate in which the P-type silicon 100 is formed on the silicon oxide film 1.
• FIG. 10 is a YY ′ cross-sectional view
• FIG. 11 is a YY ′ cross-sectional view
• X-X 'cross-section corresponds to Figure 2.
• P-type silicon 100 is etched by reactive ion etching to form source line 2 (Fig. 12 ( ⁇ - ⁇ '), Fig. 13 ( ⁇ -),), Fig. 14 ( ⁇ - ⁇ ,)).
• An oxide film is deposited, flattened by CMP, and etched back using reactive ion etching (Fig. 15 ( ⁇ -X,), Fig. 16 (Y-Y '), Fig. 17). (Y- Y ')).
• etching the vertical silicon 100 by reactive ion etching forms the island-shaped semiconductor layer 101 (FIG. 18 ( ⁇ - ⁇ '), Fig. 19 ( ⁇ - ⁇ ' ), Figure 20 ( ⁇
• a lower portion of the island-like semiconductor layer 101 serves as a source line.
• FIG. 21 (X-X,), FIG. 22 ( ⁇ - ⁇ ,
• FIG. 24 ( ⁇ - ⁇ ′), FIG. 25 ( ⁇ - ⁇ ,), FIG. 26 ( ⁇ - ⁇ ')).
• the polycrystalline silicon film is etched by reactive ion etching, and left as a sidewall spacer on the island-shaped semiconductor sidewall to form the charge storage layer 6 (FIG. 27 (X- X,), Fig. 28 ( ⁇ - ⁇ ,), Fig. 29 ( ⁇ - ⁇ ,)).
• An insulating film may be deposited by CVD.
• FIG. 33 (X-X,), FIG. 34 (Y-Y,), FIG. 35 ( ⁇
• a patterned resist 106 is formed by a known photolithography technique (FIG. 39 (X-X '), FIG. 40 (Y-Y'), FIG. 41 (Y-Y ')). .
• the polycrystalline silicon film 105 is etched by reactive ion etching, and left on the side wall of the charge storage layer in the form of a sidewall spacer, thereby forming the control gate 7 ( Fig. 42 ( ⁇ - ⁇ '), Fig. 43 (Y-Y'), Fig. 44 (Y-Y ')).
• the source line 2, the source diffusion layer 3, and the drain diffusion layer 5 are formed by an ion implantation method or the like (FIGS. 45 (X-X '), 46 (Y-Y'), and 47 (Y -Y ')).
• an interlayer insulating film 107 such as a silicon oxide film is deposited and planarized using CMP or the like, and then the interlayer insulating film is etched by reactive ion etching using a resist as a mask.
• a resist as a mask.
• metal 108 is deposited by sputtering or the like (Fig. 51 (X-X,), Fig. 52 ( ⁇ - ⁇ ,),
• the metal is etched by reactive ion etching to form a common source line 9 (FIG. 54 (X-X '), FIG. 55 (Y-Y'), FIG. 56 (Y -Y ')).
• FIG. 57 ( ⁇ - ⁇ ,), FIG. 58 ( ⁇ - ⁇ ,), FIG. 59 ( ⁇ - ⁇ ,
• the operation of injecting (writing) charges into the charge storage layer of the selected memory cell Ml by hot electron is performed as shown in FIG. Apply 0V or a voltage (5V) that generates a hot electron to the selected bit line 200, apply 0V to the unselected bit line 201, and apply a high voltage (9V to the selected control gate line 202). ), 0 V is applied to the non-selected control gate line 203, and 0 V is applied to the source line 204 and the common source line 205. With the above operation, charges can be injected into the charge storage layer using hot electrons.
• the data read operation of the selected memory cell Ml is performed as shown in FIG. A voltage (3V) is applied to the selected control gate line 202, 0V is applied to the unselected control gate line 203, 0V is applied to the source line 204 and the common source line 205, and a voltage is applied to the selected bit line 200. By applying (0.5V), the selected memory cell can be read.
• the operation of discharging (erasing) charges by the FN tunnel current from the charge storage layer of the memory cell connected to the selected control gate line of the memory cell array is performed as shown in FIG.
• An erase voltage (18V) is applied to all bit lines, source lines, and common source lines, and 0V is applied to the selected control gate line 202.
• (9V) charges can be discharged from the charge storage layer of the memory cell connected to the selected control gate line using the FN tunnel current.
• the single charge storage layer surrounding the island-shaped semiconductor is formed on the channel region on the side wall sandwiched between the drain diffusion layer and the source diffusion layer of the island-shaped semiconductor layer via the gate insulating film.
• the force charge storage layer using a memory cell having a structure is not necessarily a single charge storage layer.
• a plurality of charge storage layers 300 may be surrounded.
• the source line can be reduced in resistance.
• 0V can be applied to the source diffusion layer of the memory cell at the time of writing, a sufficient voltage can be applied between the source and drain, a sufficient current can flow between the source and drain, and the writing speed can be improved. A decrease can be avoided.
• 0 V can be applied to the source diffusion layer of the memory cell, a sufficient voltage can be applied between the source and the drain, and a sufficient current can flow between the source and the drain. It is possible to avoid a decrease in speed.
• FIG. 1 is a layout of a nonvolatile semiconductor memory according to the present invention.
• FIG. 2 corresponds to a cross-sectional view taken along the line XX ′ in FIG. 1 of the nonvolatile semiconductor memory according to the present invention.
• FIG. 3 Corresponds to the YY 'cross-sectional view in Fig. 1 of the nonvolatile semiconductor memory according to the present invention.
• FIG. 4 Corresponds to the YY 'cross-sectional view of the nonvolatile semiconductor memory according to the present invention in Fig. 1.
• FIG. 5 is a layout of a nonvolatile semiconductor memory according to the present invention.
• FIG. 6 corresponds to a cross-sectional view taken along the line XX ′ in FIG. 1 of the nonvolatile semiconductor memory according to the present invention.
• FIG. 7 Corresponds to the YY 'cross-sectional view of the nonvolatile semiconductor memory according to the present invention in Fig. 1.
• FIG. 8 Corresponds to the YY 'sectional view of Fig. 1 of the nonvolatile semiconductor memory according to the present invention.
• FIG. 9 is a process drawing showing an XX ′ cross section in a manufacturing example of the memory cell array according to the present invention.
• FIG. 10 is a cross-sectional process diagram along Y-Y showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 11 is a cross-sectional process diagram along Y-Y showing a manufacturing example of a memory cell array according to the present invention.
• FIG. 12 is a cross-sectional process diagram along XX showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 13 is a cross-sectional process drawing showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 14 is a cross-sectional process diagram along Y-Y showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 15 is a sectional view taken along the line XX showing an example of manufacturing the memory cell array according to the present invention.
• FIG. 16 is a cross-sectional process diagram along Y-Y showing a manufacturing example of a memory cell array according to the present invention.
• FIG. 17 is a cross-sectional process diagram along Y-Y showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 18 is a cross-sectional process diagram along XX showing an example of manufacturing the memory cell array according to the present invention.
• FIG. 19 is a cross-sectional process diagram along Y-Y showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 20 is a cross-sectional process diagram along Y-Y showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 21 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 22 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 23 shows a manufacturing example of a memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 24 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 25 shows a manufacturing example of a memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 26 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 27 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 28 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 29 is a cross-sectional process diagram along Y-Y showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 30 is a sectional view taken along the line XX showing an example of manufacturing the memory cell array according to the present invention.
• FIG. 31 is a process drawing showing a manufacturing example of the memory cell array taken along the line Y-Y, according to the present invention.
• FIG. 32 is a sectional view taken along the line Y-Y showing the manufacture example of the memory cell array according to the present invention.
• FIG. 33 is a cross-sectional process diagram along XX showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 34 is a sectional view showing a manufacturing example of the memory cell array taken along the line Y-Y, according to the present invention.
• FIG. 35 is a sectional view taken along the line Y--Y showing an example of manufacturing the memory cell array according to the present invention.
• FIG. 36 is a cross-sectional process diagram along XX showing an example of manufacturing the memory cell array according to the present invention.
• FIG. 37 is a process drawing showing a manufacturing example of the memory cell array taken along the line Y-Y, according to the present invention. 38] FIG. 38 is a YY cross-sectional process drawing showing the manufacture example of the memory cell array according to the present invention.
• FIG. 39 XX is a sectional process diagram showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 40 is a YY cross-sectional process drawing showing the manufacture example of the memory cell array according to the present invention.
• FIG. 41 Y-Y, a cross-sectional process diagram showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 42] XX is a sectional process diagram showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 43 Y-Y sectional view showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 44 is a Y-Y sectional view showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 45 XX, sectional process drawing showing the manufacture example of the memory cell array according to the present invention.
• FIG. 46 Y-Y sectional view showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 47 Y-Y, cross-sectional process drawing showing the manufacture example of the memory cell array according to the present invention.
• FIG. 48 XX is a sectional process diagram showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 49 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 50 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 51 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 52 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 53 shows an example of manufacturing a memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 54 shows a manufacturing example of a memory cell array according to the present invention.
• FIG. 55 Y-Y, showing a manufacturing example of a memory cell array according to the present invention
• FIG. 1 A first figure.
• FIG. 56 shows a manufacturing example of the memory cell array according to the present invention.
• FIG. 1 A first figure.
• FIG. 57 A cross-sectional process drawing XX showing an example of manufacturing the memory cell array according to the present invention.
• FIG. 58 is a Y-Y sectional view showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 59 is a Y-Y sectional view showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 60 A cross-sectional process diagram along XX showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 61 YY cross-sectional process drawing showing the manufacture example of the memory cell array according to the present invention.
• FIG. 62 is a Y-Y cross-sectional process drawing showing the manufacture example of the memory cell array according to the present invention.
• FIG. 63] XX is a sectional process diagram showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 64 Y-Y sectional view showing a manufacturing example of the memory cell array according to the present invention.
• FIG. 65 is a Y-Y cross-sectional process drawing showing the manufacture example of the memory cell array according to the present invention.
• FIG. 66 is a diagram showing a potential relationship at the time of data writing.
• FIG. 67 is a diagram showing a potential relationship during data reading.
• FIG. 68 is a diagram showing a potential relationship when all memory cells are erased.
• FIG. 69 is a diagram showing a potential relationship when erasing a memory cell connected to a selected control gate line.
• FIG. 70 is a bird's eye view showing another embodiment according to the present invention.
• FIG. 71 is a bird's eye view showing another embodiment according to the present invention.
• FIG. 72 is a cross-sectional view showing another embodiment according to the present invention.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Non-Volatile Memory (AREA)
• Semiconductor Memories (AREA)
• Read Only Memory (AREA)

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• 2006
  • 2006-07-12 JP JP2006191470A patent/JP5088465B2/ja active Active
• 2007
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  • 2007-07-12 WO PCT/JP2007/063889 patent/WO2008007731A1/ja not_active Ceased
  • 2007-07-12 EP EP13170935.4A patent/EP2639825A3/en not_active Withdrawn
  • 2007-07-12 CN CN2007800262290A patent/CN101490837B/zh not_active Expired - Fee Related
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  • 2007-07-12 KR KR1020097000601A patent/KR101020846B1/ko not_active Expired - Fee Related
• 2009
  • 2009-01-12 US US12/319,782 patent/US7940574B2/en not_active Expired - Fee Related

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