CN109326604A - 三维存储器及其操作方法 - Google Patents

三维存储器及其操作方法 Download PDF

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Publication number
CN109326604A
CN109326604A CN201710645400.1A CN201710645400A CN109326604A CN 109326604 A CN109326604 A CN 109326604A CN 201710645400 A CN201710645400 A CN 201710645400A CN 109326604 A CN109326604 A CN 109326604A
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China
Prior art keywords
source electrode
charge storage
line
electrode line
layer
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Pending
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CN201710645400.1A
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English (en)
Inventor
陈江宏
蔡耀庭
洪文
廖祐楷
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN201710645400.1A priority Critical patent/CN109326604A/zh
Priority to US16/048,364 priority patent/US10580487B2/en
Publication of CN109326604A publication Critical patent/CN109326604A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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Abstract

本发明提供一种三维存储器及其操作方法，包括：衬底、多条源极线、多个隔离结构、多条漏极线、多个位线、多个电荷存储结构以及多个导体层。源极线位于衬底上。隔离结构分别位于源极线之间，以电性隔离源极线。漏极线位于源极线上。漏极线与源极线的延伸方向不同。位线自源极线延伸至漏极线。电荷存储结构分别围绕位线。导体层分别覆盖沿各源极线排列的电荷存储结构的表面。

Description

三维存储器及其操作方法
技术领域
本发明涉及一种半导体元件及其操作方法，尤其涉及一种三维存储器及其操作方法。
背景技术
闪速存储器(Flash memory)元件由于具有可多次进行数据的存入、读取、抹除等动作，且存入的数据在断电后也不会消失的优点，所以已成为个人电脑和电子设备所广泛采用的一种非易失性存储器元件。
典型的闪速存储器元件是以掺杂的多晶硅制作浮置栅极与控制栅极。而且，浮置栅极与控制栅极之间以介电层相隔。浮置栅极与衬底之间是以穿隧氧化层相隔。在读取闪速存储器中的数据时，是对控制栅极上施加一工作电压，并依据浮置栅极的带电状态来影响其下通道的开/关，而此通道的开/关即为判读数据值“0”或“1”的依据。
随着科技的进步，各类电子产品皆朝向高速、高效能、且轻薄短小的趋势发展，而在这趋势之下，对于更高存储能力的闪速存储器的需求也随之增加。因此，闪速存储器的设计也已朝向具有高积集度及高密度的三维闪速存储器结构发展。
发明内容
本发明提供一种三维存储器及其操作方法，其可在单一存储单元中存储4比特(4bits)的数据，进而提高整体三维存储器存储能力。
本发明提供一种三维存储器，其将隔离结构配置在相邻源极线之间，藉此降低读取时的干扰。
本发明提供一种三维存储器，包括：衬底、多条源极线、多个隔离结构、多条漏极线、多个位线、多个电荷存储结构以及多个导体层。源极线位于衬底上。隔离结构分别位于源极线之间，以电性隔离源极线。漏极线位于源极线上。漏极线与源极线的延伸方向不同。位线自源极线延伸至漏极线。电荷存储结构分别围绕位线。导体层分别覆盖沿各源极线排列的电荷存储结构的表面。
在一实施例中，形成位线的材料包括第一型多晶硅材料。形成源极线与漏极线的材料包括第二型多晶硅材料。第一型多晶硅材料不同于第二型多晶硅材料。
在一实施例中，各位线包括第一部分、第二部分与第三部分。第二部分位于第一部分与第三部分之间。第二部分被电荷存储结构所包围。第一部分连接源极线且作为源极。第三部分连接漏极线且作为漏极。
在一实施例中，三维存储器还包括硅化金属层位于源极线上，以降低所述源极线与位线之间的电阻值。
在一实施例中，电荷存储结构是经组态以存储4比特的数据。
在一实施例中，电荷存储结构包括穿隧介电层、电荷存储层以及电子阻挡层。所述电荷存储层位于穿隧介电层与电子阻挡层之间。
在一实施例中，电荷存储层的材料包括氮化硅、氧化铝、二氧化铪、二氧化锆、氧化镧、氧化钇或其组合。
本发明提供一种用于所述三维存储器的操作方法，包括：程序化、抹除或读取电荷存储结构。
在一实施例中，程序化电荷存储结构的步骤包括对导体层施加一正电压，对漏极线施加另一正电压，并将源极线接地，以将电子存储在靠近所述漏极线的所述电荷存储结构中。
在一实施例中，抹除电荷存储结构的步骤包括对导体层施加一负电压，对漏极线施加一正电压，并将源极线接地，以将电洞吸引至靠近所述漏极线的电荷存储结构中。
在一实施例中，读取电荷存储结构的机制包括对导体层施加一读取电压，对漏极线施加一正电压，并将源极线接地，以读取靠近所述漏极线的电荷存储结构中的存储状态。
在一实施例中，读取电荷存储结构的机制包括对导体层施加一读取电压，对源极线施加一正电压，并将漏极线接地，以读取靠近所述源极线的电荷存储结构中的存储状态。
基于上述，本发明通过在相邻两条源极线之间配置隔离结构，以电性隔离相邻两条源极线，进而降低读取时的干扰。另外，本发明以高介电常数材料当作电荷存储层，其可在单一存储单元中存储4比特的数据，进而提高整体三维存储器存储能力。此外，本发明通过价带-导带热电洞注入模式来抹除所述存储单元，其可降低穿隧介电层的损害，进而提升三维存储器的可靠度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1为本发明的一实施例的三维存储器的立体示意图。
图2A至图2L为沿图1的A-A线的制造流程的剖面示意图。
图3A至图3P为沿图1的B-B线的制造流程的剖面示意图。
图4A为程序化本发明的一实施例的三维存储器的剖面示意图。
图4B为抹除本发明的一实施例的三维存储器的剖面示意图。
图4C与图4D分别为读取本发明的一实施例的三维存储器的剖面示意图。
附图标记说明
10、12、14：开口 110：隔离层
16：空隙 112：导体材料
100：衬底 114：位线
102：底介电层 114a：第一部分
104：导体层 114b：第二部分
104a：源极线 114c：第三部分
106：缓冲结构 116、116a：隔离结构
106a、106c：氧化硅层 118：电荷存储结构
106b：氮化硅层 118U：上部
108：介电层 120、120a：导体层
120b、120c：导体层 D：漏极
122：间隙壁材料 S：源极
122a、122b：间隙壁 L：长度
124：硅化金属层 WL：字线
126、126a：介电层 X、Y、Z：方向
128：漏极线 Vg、Vd、VF、VR：电压
C：通道
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
图1为依照本发明的一实施例所示出的三维存储器的立体示意图。在本实施例中，图1的三维存储器可例如是或非(NOR)闪速存储器。为了清楚起见，图1中仅示出出衬底、底介电层、源极线、隔离结构、存储单元以及漏极线，其他构件请参照后续的剖面示意图。
请参照图1，本实施例提供一种三维存储器，包括：衬底100、底介电层102、多条源极线104a、多个隔离结构116a、多个存储单元、多条位线114、多条字线WL以及多条漏极线128。详细地说，底介电层102位于衬底100上。源极线104a位于底介电层102上，使得底介电层102位于源极线104a与衬底100之间。源极线104a为条状图案，其沿着Y方向延伸。隔离结构116a位于源极线104a之间的底介电层102上，以电性隔离相邻两条源极线104a，进而降低读取时的干扰。在一实施例中，隔离结构116a为条状，其沿着Y方向延伸。
存储单元以阵列方式分别位于源极线104a上。具体来说，每一存储单元包括电荷存储结构118。电荷存储结构118围绕位线114的第二部分114b(如图2L所示)。在一实施例中，位线114可例如是圆柱状结构，而电荷存储结构118呈带状并包围位线114的中央部分。但本发明不以此为限，在其他实施例中，位线114可例如是多边柱状结构。另外，电荷存储结构118相对于衬底100的表面的垂直方向的长度L可视为通道长度。位线114自源极线104a延伸至漏极线128。在一实施例中，位线114沿着Z方向延伸，使得位线114的两端分别连接源极线104a与漏极线128。形成位线114的材料包括P型多晶硅材料，使位于源极线104a与电荷存储结构118之间的位线114的第一部分114a(如图2L所示)可作为源极，被电荷存储结构118所包覆的位线114的第二部分114b可作为有源区或通道区，位于漏极线128与电荷存储结构118之间的位线114的第三部分114c(如图2L所示)可作为漏极。各字线WL覆盖沿同一行(column)排列的多个电荷存储结构118的表面。如图1所示，字线WL沿着Y方向延伸。也就是说，字线WL的延伸方向与源极线104a的延伸方向相同。
每一漏极线128连接排列成同一列(row)的多条位线114。漏极线128沿着X方向延伸。也就是说，漏极线128与源极线104a的延伸方向不同。
图2A至图2L为沿图1的A-A线的制造流程的剖面示意图。图3A至图3P为沿图1的B-B线的制造流程的剖面示意图。
请同时参照图2A与图3A，本实施例提供图1的三维存储器的制造方法，其步骤如下。首先，提供衬底100。在一实施例中，衬底100可例如为半导体衬底、半导体化合物衬底或是绝缘层上有半导体衬底(Semiconductor Over Insulator，SOI)。在本实施例中，衬底100可以是P型硅衬底。
接着，在衬底100上依序形成底介电层102、导体层104、缓冲结构106以及介电层108。在一实施例中，底介电层102可以是氧化硅层，其形成方法可例如是化学气相沈积法。导体层104可以是掺杂多晶硅层。在本实施例中，导体层104可以是N+多晶硅层，其所植入的掺质可例如是磷或是砷，其掺杂浓度可例如是1×1018/cm3至1×1021/cm3。缓冲结构106包括氧化硅层106a、氮化硅层106b以及氧化硅层106c的复合结构，其形成方法可例如是化学气相沈积法。介电层108可以是氮化硅层，其形成方法可例如是化学气相沈积法。
请同时参照图2A-2B与图3A-3B，于导体层104、缓冲结构106以及介电层108中形成隔离层110。隔离层110沿着A-A线方向(也即图1的Y方向)延伸，藉此将导体层104分隔成多条源极线104a。隔离层110的形成方法可例如是在导体层104、缓冲结构106以及介电层108中形成开口10。开口10暴露出底介电层102的顶面。接着，将隔离材料填入开口10中并进行平坦化工艺。在此阶段中，如图3B所示，隔离层110的顶面与介电层108的顶面实质上共平面。在一实施例中，所述平坦化工艺可以是化学机械研磨工艺(CMP)或回蚀刻工艺(Etchingback)。隔离层110的材料可以是氧化硅。
请同时参照图2B-2C与图3B-3C，形成贯穿缓冲结构106以及介电层108的多个开口12，以暴露出源极线104a的顶面。另外，由于开口12是用以定义图1的位线114的位置，因此，开口12是以阵列方式分别形成于源极线104a上。之后，在衬底100上形成导体材料112。导体材料112填入开口12中并覆盖介电层108的顶面。在一实施例中，导体材料112可例如是P型多晶硅材料，其所植入的掺质可例如是硼。
请同时参照图2C-2D与图3C-3D，进行平坦化工艺，以暴露出介电层108的顶面，并在各开口12中形成位线114。在此阶段中，位线114的顶面与介电层108的顶面实质上共平面。在一实施例中，所述平坦化工艺可以是化学机械研磨工艺或回蚀刻工艺。
请同时参照图2D-2E与图3D-3E，凹蚀(recess)隔离层110，使得隔离结构116的顶面与缓冲结构106的顶面实质上共平面。然后，移除介电层108，以暴露出缓冲结构106的顶面。在一实施例中，凹蚀隔离层110的方法可例如是湿式蚀刻法，其可利用对隔离层110与介电层108(或位线114)具有高蚀刻选择比的蚀刻液来进行。相似地，移除介电层108的方法也可以是湿式蚀刻法，其可利用对介电层108与位线114(或隔离结构116)具有高蚀刻选择比的蚀刻液来进行。
请同时参照图2F与图3F，在衬底100上形成电荷存储结构118。电荷存储结构118共形地覆盖位线114的表面、缓冲结构106的顶面以及隔离结构116的顶面。虽然图2F与图3F所示出的电荷存储结构118为单层结构，但实际上电荷存储结构118可包括穿隧介电层、电荷存储层以及电子阻挡层(未示出)。所述电荷存储层位于所述穿隧介电层与所述电子阻挡层之间。在一实施例中，电荷存储结构118可例如是由氧化硅层/氮化硅层/氧化硅层所构成的复合结构。但本发明不以此为限，在其他实施例中，所述电荷存储层的材料可以是高介电常数材料，以提供高电容耦合(capacitive coupling)。高介电常数材料是指介电常数高于4的介电材料。高介电常数材料可例如是氮化硅、氧化铝、二氧化铪、二氧化锆、氧化镧、氧化钇或其组合。相较于現有以掺杂的多晶硅当作浮置栅极的存储器，本实施例的电荷存储结构118可减少穿隧介电层与电子阻挡层的厚度，同时维持存储器的可靠度。另外，本实施例的高介电常数的电荷存储层具有较低的有效氧化物厚度(effective oxide thickness，EOT)，其有利于存储器的尺寸微缩。此外，由于高介电常数材料为电性绝缘材料，因此，电子可分开存储在具有高介电常数的电荷存储层中，以达到将4比特数据存储在单一存储单元的功效。在替代实施例中，所述电荷存储层的材料也可以是相对于穿隧介电层与电子阻挡层的具有较大导带偏移(conduction band offset)的材料，其具有较佳的可靠度。
值得注意的是，在高温的情况下，源极线104a的N型掺质会扩散至位线114的第一部分114a中，藉此形成源极区。位线114的第二部分114b位于位线114的第一部分114a上。在一实施例中，位线114的第二部分114b可以是P型导电型；而位线114的第一部分(或源极区)114a可以是N型导电型。位线114的第一部分114a嵌于缓冲结构106中。电荷存储结构118覆盖且围绕位线114的第二部分114b。为简洁起见，此第一部分114a仅示出于图2F与图3F中，而不再示出于后续附图中。
请同时参照图2G与图3G，于电荷存储结构118上形成导体层120。导体层120围绕电荷存储结构118并覆盖电荷存储结构118的顶面。在一实施例中，导体层120的材料可例如是掺杂多晶硅，其形成方法可以是化学气相沉积法。在替代实施例中，导体层120的材料可以是金属材料，例如铜(Cu)、铝(Al)、钨(W)或其组合。
请同时参照图2G-2H与图3G-3H，对导体层120进行平坦化工艺，以暴露出电荷存储结构118的顶面。在此情况下，如图2H与图3H所示，导体层120a配置在位线114旁，且导体层120a的顶面与电荷存储结构118的顶面可实质上共平面。在一实施例中，所述平坦化工艺可以是化学机械研磨工艺或回蚀刻工艺。
请同时参照图2H-2I与图3H-3I，进行蚀刻工艺，移除部分导体层120a，以暴露出电荷存储结构118的上部118U。在此情况下，如图2I与图3I所示，导体层120b的顶面低于电荷存储结构118(或位线114)的顶面。在一实施例中，所述蚀刻工艺可以是回蚀刻工艺。
请同时参照图3I与图3J，于位线114之间的导体层120b中形成开口14，以形成导体层120c。开口14对应于隔离结构116a。在一实施例中，开口14可以是条状开口，其沿着Y方向(如图1所示)延伸。开口14贯穿导体层120c、电荷存储结构118以及部分缓冲结构106，以暴露出缓冲结构106的氧化硅层106a。在一实施例中，开口14的形成方法包括光刻工艺与蚀刻工艺。所述蚀刻工艺可例如是反应性离子蚀刻工艺(RIE)。
请同时参照图3J与图3K，于衬底100上形成间隙壁材料122。间隙壁材料122共形地覆盖开口14的表面、导体层120c的顶面以及电荷存储结构118的顶面。在一实施例中，间隙壁材料122的材料可例如是氮化硅，其形成方法可以是化学气相沉积法。
请同时参照图3K与图3L，进行干式蚀刻工艺，移除部分间隙壁材料122，以在导体层120c的侧壁形成间隙壁122a并在电荷存储结构118的上部118U的侧壁形成间隙壁122b。在此情况下，开口14的底面的间隙壁材料122也被移除，以暴露出缓冲结构106的氧化硅层106a的顶面(未示出)。在一实施例中，所述干式蚀刻工艺可例如是反应性离子蚀刻工艺(RIE)。之后，进行湿式蚀刻工艺，以移除缓冲结构106的氧化硅层106a，并在缓冲结构106中形成空隙16。空隙16暴露出源极线104a的部分顶面。如图3L所示，空隙16由缓冲结构106的氮化硅层106b、位线114以及源极线104a所定义。
请同时参照图3L与图3M，进行金属硅化工艺，以于外露于空隙16的源极线104a的部分顶面上形成硅化金属层124。如图3M所示，硅化金属层124除了配置在被源极线104a覆盖以外的源极线104a的顶面上，还延伸配置在源极线104a下方的源极线104a中，以降低源极线104a与位线114之间的电阻值，进而提升存储器的速度。金属硅化工艺的步骤包括在源极线104a上形成金属层(未示出)。之后，进行热回火(Anneal)工艺，使得所述金属层与其所接触的源极线104a反应形成硅化金属层124。在一实施例中，硅化金属层124的材料例如是硅化镍(NiSi)、硅化钴(CoSi)、硅化钛(TiSi)、硅化钨(WSi)、硅化钼(MoSi)、硅化铂(PtSi)、硅化钯(PdSi)或其组合。
由于图3J至图3M的层的变化并不会出现在图1的A-A线剖面上，因此，为了简洁起见，本文中并未示出出相对应于图3J至图3M的步骤的A-A线剖面图。也就是说，图2J的步骤是接续于硅化金属层124的形成之后。请同时参照图2J与图3M-3N，于衬底100上形成介电层126。介电层126填入开口14中并填入空隙16中。如图3N所示，介电层126还覆盖电荷存储结构118的顶面。在一实施例中，介电层126的材料包括氧化硅，其形成方法可以是化学气相沉积法。
请同时参照图2J-2K与图3N-3O，对介电层126进行平坦化工艺，移除部分介电层126、部分电荷存储结构118以及部分间隙壁122b，以暴露出位线114的顶面。在此情况下，如图3O所示，位线114的顶面、电荷存储结构118的顶面以及介电层126a的顶面可实质上共平面。在一实施例中，所述平坦化工艺可以是化学机械研磨工艺或回蚀刻工艺。
请同时参照图2L与图3P，于位线114上形成漏极线128。漏极线128沿着B-B线方向(或图1的X方向)延伸，并横越源极线104a与隔离结构116a。在本实施例中，漏极线128可以是N+多晶硅层，其所植入的掺质可例如是磷或是砷，其掺杂浓度可例如是1×1018/cm3至1×1021/cm3。但本发明不限于此，在其他实施例中，漏极线128也可以是金属或其他导体材料。在替代实施例中，亦可对位线114进行离子注入工艺，以将磷掺质或是砷掺质植入位线114的第三部分114c中，藉此形成漏极区。也就是说，如图2L所示，位线114包括第一部分114a、第二部分114b以及第三部分114c。第二部分114b位于第一部分114a与第三部分114c之间。在一实施例中，第二部分114b的导电型与第一部分114a与第三部分114c的导电型不同。在本实施例中，第二部分114b可具有P型导电型，其可视为有源区或通道区。第一部分114a与第三部分114c可具有N型导电型。第一部分114a可视为源极区；而第三部分114c可视为漏极区。
值得注意的是，如图2L与图3P所示，位线114自源极线104a延伸至漏极线128。电荷存储结构118围绕位线114的侧壁，并延伸覆盖缓冲结构106的顶面。导体层120c覆盖电荷存储结构118的表面，使得电荷存储结构118配置于位线114与导体层120c之间。导体层120c至少覆盖位线114的第二部分(或通道区)114b。换言之，导体层120c可视为存储单元的控制栅极或是字线。
在本实施例中，虽然图2L与图3P所示出的源极线104a为源极端；而漏极线128为漏极端，但本发明不以此为限。在其他实施例中，源极线104a也可用以当作漏极端；而漏极线128也可用以当作源极端。
图4A为程序化本发明的一实施例的三维存储器的剖面示意图。图4B为抹除本发明的一实施例的三维存储器的剖面示意图。图4C与图4D分别为读取本发明的一实施例的三维存储器的剖面示意图。
本实施例的三维存储器的操作方法包括程序化、抹除或读取图1的电荷存储结构118。请参照图4A，程序化电荷存储结构118的机制包括通道热电子注入模式(Channel HotElectronInjection)。详细地说，通道热电子注入模式的步骤如下。对字线WL(其对应于图1的导体层120c)施加一正电压Vg，对漏极D(其对应于图1的漏极线128)施加另一正电压Vd，并将源极S(其对应于图1的源极线104a)接地，使得存储单元导通。因此，电流从漏极D流入源极S，而通道C中产生的热电子被吸引并存储在靠近漏极D的电荷存储结构118中，以产生“01”的状态。相似地，对字线WL、漏极D以及源极S施加不同电压，则可分别产生“10”、“11”或是“00”的状态。因此，本实施例的电荷存储结构118可经组态以存储4比特的数据。在一实施例中，电压Vg可介于7伏特至9.5伏特之间；电压Vd可介于3.5伏特至5伏特之间。
请参照图4B，抹除电荷存储结构118的机制包括价带-导带热电洞注入模式(Bandto BandHot Hole Injection)。详细地说，价带-导带热电洞注入模式的步骤如下。对字线WL(其对应于图1的导体层120c)施加一负电压Vg，对漏极D(其对应于图1的漏极线128)施加一正电压Vd，并将源极S(其对应于图1的源极线104a)接地。如此一来，通道C中的热电洞被吸引并注入在靠近漏极D的电荷存储结构118中，使得所述热电洞与所存储的电子耦合。在本实施例中，以价带-导带热电洞注入模式来抹除电荷存储结构118，其可降低电荷存储结构118中的穿隧介电层的损害，进而提升三维存储器的可靠度。在一实施例中，电压Vg可介于-10伏特至-15伏特之间；电压Vd可介于3.5伏特至5伏特之间。
请参照图4C与图4D，读取电荷存储结构118的机制包括正向读取(forward read)模式或反向读取(reverse read)模式。详细地说，正向读取模式的操作的步骤如下。如图4C所示，对字线WL(其对应于图1的导体层120c)施加一读取电压Vg，对漏极D(其对应于图1的漏极线128)施加一正电压VF，并将源极S(其对应于图1的源极线104a)接地，以读取靠近漏极D的电荷存储结构118中的存储状态。因此，当电子已存储在靠近漏极D的电荷存储结构118时，存储单元的阀值升高，存储单元以断开的方式进行操作。在一实施例中，读取电压Vg可介于3.5伏特至4.5伏特之间；电压VF可介于0.7伏特至1.2伏特之间。
反向读取模式的操作的类似上述步骤。如图4D所示，对字线WL(其对应于图1的导体层120c)施加一读取电压，对源极S(其对应于图1的源极线104a)施加一正电压VR，并将漏极D(其对应于图1的漏极线128)接地，以读取靠近源极S的电荷存储结构118中的存储状态。因此，当电子未存储在靠近源极S的电荷存储结构118时，存储单元的阀值降低，存储单元以导通的方式进行操作。在一实施例中，读取电压Vg可介于3.5伏特至4.5伏特之间；电压VR可介于0.7伏特至1.2伏特之间。
综上所述，本发明通过在相邻两条源极线之间配置隔离结构，以电性隔离相邻两条源极线，进而降低读取时的干扰。另外，本发明以高介电常数材料当作电荷存储层，其可在单一存储单元中存储4比特的数据，进而提高整体三维存储器存储能力。此外，本发明通过价带-导带热电洞注入模式来抹除所述存储单元，其可降低穿隧介电层的损害，进而提升三维存储器的可靠度。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (12)

1.一种三维存储器，其特征在于，包括：
多条源极线，位于衬底上；
多个隔离结构，分别位于所述源极线之间，以电性隔离所述源极线；
多条漏极线，位于所述源极线上，其中所述漏极线与所述源极线的延伸方向不同；
多个位线，自所述源极线延伸至所述漏极线；
多个电荷存储结构，分别围绕所述位线；以及
多个导体层，分别覆盖沿各所述源极线排列的所述电荷存储结构的表面。
2.根据权利要求1所述的三维存储器，其特征在于，形成所述位线的材料包括第一型多晶硅材料，形成所述源极线与所述漏极线的材料包括第二型多晶硅材料，且所述第一型多晶硅材料不同于所述第二型多晶硅材料。
3.根据权利要求1所述的三维存储器，其特征在于，各所述位线包括第一部分、第二部分与第三部分，所述第二部分位于所述第一部分与所述第三部分之间，所述第二部分被所述电荷存储结构所包围，所述第一部分连接所述源极线且作为源极，所述第三部分连接所述漏极线且作为漏极。
4.根据权利要求1所述的三维存储器，其特征在于，还包括硅化金属层位于所述源极线上，以降低所述源极线与所述位线之间的电阻值。
5.根据权利要求1所述的三维存储器，其特征在于，所述电荷存储结构是经组态以存储4比特的数据。
6.根据权利要求1所述的三维存储器，其特征在于，所述电荷存储结构包括穿隧介电层、电荷存储层以及电子阻挡层，所述电荷存储层位于所述穿隧介电层与所述电子阻挡层之间。
7.根据权利要求1所述的三维存储器，其特征在于，所述电荷存储层的材料包括氮化硅、氧化铝、二氧化铪、二氧化锆、氧化镧、氧化钇或其组合。
8.一种用于根据权利要求1所述的三维存储器的操作方法，其特征在于，包括程序化、抹除或读取所述电荷存储结构。
9.根据权利要求8项所述的操作方法，其特征在于，程序化所述电荷存储结构的步骤包括对所述导体层施加一正电压，对所述漏极线施加另一正电压，并将所述源极线接地，以将电子存储在靠近所述漏极线的所述电荷存储结构中。
10.根据权利要求8所述的操作方法，其特征在于，抹除所述电荷存储结构的步骤包括对所述导体层施加一负电压，对所述漏极线施加一正电压，并将所述源极线接地，以将电洞吸引至靠近所述漏极线的所述电荷存储结构中。
11.根据权利要求8所述的操作方法，其特征在于，读取所述电荷存储结构的步骤包括对所述导体层施加一读取电压，对所述漏极线施加一正电压，并将所述源极线接地，以读取靠近所述漏极线的所述电荷存储结构中的存储状态。
12.根据权利要求8所述的操作方法，其特征在于，读取所述电荷存储结构的步骤包括对所述导体层施加一读取电压，对所述源极线施加一正电压，并将所述漏极线接地，以读取靠近所述源极线的所述电荷存储结构中的存储状态。
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WO2022067720A1 (zh) * 2020-09-30 2022-04-07 华为技术有限公司 铁电存储器及其制作方法、存储设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622451B1 (en) * 2018-12-07 2020-04-14 National Cheng Kung University Flash memory with multiple control gates and flash memory array device made thereof
KR20210015445A (ko) * 2019-08-02 2021-02-10 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법
US11462282B2 (en) 2020-04-01 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memory structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101490837A (zh) * 2006-07-12 2009-07-22 日本优尼山帝斯电子股份有限公司 非易失性半导体存储器及其驱动方法
US20100142294A1 (en) * 2008-12-05 2010-06-10 Eric Carman Vertical Transistor Memory Cell and Array
CN105097818A (zh) * 2014-05-21 2015-11-25 旺宏电子股份有限公司 存储器装置及其制造方法和操作方法
CN105374824A (zh) * 2014-08-14 2016-03-02 三星电子株式会社 半导体器件
US9679849B1 (en) * 2014-01-17 2017-06-13 Macronix International Co., Ltd. 3D NAND array with sides having undulating shapes

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009200443A (ja) * 2008-02-25 2009-09-03 Toshiba Corp 不揮発性半導体記憶装置、及びその製造方法
JP5288936B2 (ja) * 2008-08-12 2013-09-11 株式会社東芝 不揮発性半導体記憶装置
JP2010251572A (ja) 2009-04-16 2010-11-04 Toshiba Corp 不揮発性半導体記憶装置
SG192371A1 (en) 2012-01-20 2013-08-30 Agency Science Tech & Res A resistive memory arrangement and a method of forming the same
US9559117B2 (en) * 2014-06-17 2017-01-31 Sandisk Technologies Llc Three-dimensional non-volatile memory device having a silicide source line and method of making thereof
US10014317B2 (en) * 2014-09-23 2018-07-03 Haibing Peng Three-dimensional non-volatile NOR-type flash memory
US11956952B2 (en) * 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US10121553B2 (en) * 2015-09-30 2018-11-06 Sunrise Memory Corporation Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101490837A (zh) * 2006-07-12 2009-07-22 日本优尼山帝斯电子股份有限公司 非易失性半导体存储器及其驱动方法
US20100142294A1 (en) * 2008-12-05 2010-06-10 Eric Carman Vertical Transistor Memory Cell and Array
US9679849B1 (en) * 2014-01-17 2017-06-13 Macronix International Co., Ltd. 3D NAND array with sides having undulating shapes
CN105097818A (zh) * 2014-05-21 2015-11-25 旺宏电子股份有限公司 存储器装置及其制造方法和操作方法
CN105374824A (zh) * 2014-08-14 2016-03-02 三星电子株式会社 半导体器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022021307A1 (zh) * 2020-07-31 2022-02-03 华为技术有限公司 存储单元和存储器
WO2022067720A1 (zh) * 2020-09-30 2022-04-07 华为技术有限公司 铁电存储器及其制作方法、存储设备

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