JP2017152541A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2017152541A JP2017152541A JP2016033597A JP2016033597A JP2017152541A JP 2017152541 A JP2017152541 A JP 2017152541A JP 2016033597 A JP2016033597 A JP 2016033597A JP 2016033597 A JP2016033597 A JP 2016033597A JP 2017152541 A JP2017152541 A JP 2017152541A
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Abstract
Description
<検討例>
本願発明者は、不揮発性メモリを有するメモリセル部およびロジック部に、複数のフィン型MISFETを配置した半導体装置を検討している。先ず、半導体装置の形成方法の一部であるフィン型の素子形成領域(活性領域)の形成方法について説明する。なお、フィン型の素子形成領域(活性領域)を、単に、「フィン」または「凸部」と呼ぶ。後述するが、本願発明者が検討している不揮発性メモリを有する半導体装置においては、相対的に、メモリセル部のフィン幅を広くし、ロジック部のフィン幅を狭くした構造が求められている。つまり、ロジック部のフィン幅を、メモリセル部のフィン幅よりも狭くする必要がある。図1〜図9は、検討例である半導体装置の形成工程中の要部断面図であり、特に、フィンの形成工程を示している。
図10は、本実施の形態における半導体装置の要部平面図である。図10において、メモリセル部Aには、複数のメモリセルが行列状に配置されたメモリセルアレイの要部平面図を、ロジック部Bには、ロジック回路形成領域のロジック回路等を構成するトランジスタTrの要部平面図を示している。トランジスタTrとしては、n型のMISFET(Metal Insulator Semiconductor Field Effect Transistor)を例示するが、p型MISFETも同様に形成することができる。図11は、本実施の形態における半導体装置のメモリセル部の要部断面図である。図11には、メモリセル部Aの4つの断面図を示しており、メモリセル部A1は、図10のA1−A1´に沿う断面図、メモリセル部A2は、図10のA2−A2´に沿う断面図、メモリセル部A3は、図10のA3−A3´に沿う断面図、そして、メモリセル部A4は、図10のA4−A4´に沿う断面図である。図12には、ロジック部Bの3つの断面図を示している。ロジック部B1は、図10のB1−B1´に沿う断面図、ロジック部B2は、図10のB2−B2´に沿う断面図、ロジック部B3は、図10のB3−B3´に沿う断面図である。
次に、本実施の形態の半導体装置の製造工程について説明するが、先ず、フィンの形成工程について説明し、その後のメモリセル部のメモリセルおよびロジック部のMISFETの形成方法を説明する。本実施の形態のフィンの形成方法は、前述の検討例を基本とするものであり、前述のフィンの形成工程と異なる部分を主に説明する。図13〜図28は、本実施の形態の半導体装置の形成工程中の要部断面図である。
次に、本実施の形態の主要な特徴と効果について説明する。
変形例は、前記第2の改善の余地に向けられており、前述の検討例とは、ハードマスク膜形成工程(ステップS4)が異なる。図29〜図31は、変形例の半導体装置の製造工程中の要部断面図を示している。
B、B1、B2、B3 ロジック部
BL ビット線
CG 制御ゲート電極
CT コンタクトホール
DG ダミーゲート
EX1、EX2、EX3 n−型半導体領域
FA、FB、F1、F2、F3、F4 フィン
FAa、FBa 主面
FAs、FBs 側面
GE ゲート電極
GIm、GIt、GIL ゲート絶縁膜
HK 絶縁膜
IL1、IL2 層間絶縁膜
LD ドレイン領域
LS ソース領域
MC メモリセル
MD ドレイン領域
ME1、ME2 金属膜
MG メモリゲート電極
MS ソース領域
MW 金属配線
PG プラグ電極
PR1、PR2、PR3、PR4 フォトレジスト膜(マスク膜)
PW1、PW2 p型ウエル
SC シリサイド層
SH 肩部
SL ソース線
SP スペーサ
STM、STL 素子分離膜
SW サイドウォールスペーサ(サイドウォール、側壁絶縁膜)
Tr トランジスタ
1 半導体基板
1a 主面
2、3、5、6、7、9、10、10´、11、11´ 絶縁膜
4、13 マスク膜
5a、5b、5b´ ハードマスク膜
6a、6b 素子分離膜
8、12 導体膜
29a、29b 側壁絶縁膜
31a、31b 側壁絶縁膜
Claims (15)
- (a)主面を有する半導体基板を準備する工程、
(b)前記半導体基板の前記主面の第1領域および第2領域に、夫々、第1マスク膜を形成する工程、
(c)前記第1領域および前記第2領域において、前記第1マスク膜の側壁上に、第2マスク膜を形成する工程、
(d)前記第1マスク膜を除去した後、前記第1領域および前記第2領域において、前記第2マスク膜の外側の前記半導体基板をエッチングして凹部を設け、前記第2マスク膜の下に、第1幅を有する第1凸部を形成する工程、
(e)前記第1領域の前記第1凸部を第3マスク膜で覆った状態で、前記第2領域の前記第1凸部にエッチングを施し、前記第2領域に第2幅を有する第2凸部を形成する工程、
(f)前記第1領域において、前記第1凸部を跨ぐように、第1絶縁膜を介して第1ゲート電極を形成する工程、
(g)前記第2領域において、前記第2凸部を跨ぐように、第2絶縁膜を介して第2ゲート電極を形成する工程、
を有し、
前記第2幅は、前記第1幅よりも狭い、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1絶縁膜および前記第2絶縁膜は、前記第1凸部および前記第2凸部を熱酸化して形成され、前記第1絶縁膜の膜厚は、前記第2絶縁膜の膜厚よりも厚い、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(d)工程と前記(e)工程との間に、さらに、
(h)前記第1領域および前記第2領域において、前記第1凸部の下部において、前記第1凸部の周囲を覆う絶縁膜からなる素子分離膜を形成する工程、
を有する、半導体装置の製造方法。 - 請求項3に記載の半導体装置の製造方法において、
前記(e)工程において、
前記エッチングは等方性エッチングであり、
前記第2領域において、前記第2凸部は、前記素子分離膜から露出した第1部分と、前記素子分離膜に周囲を囲まれた第2部分とを有しており、
前記第2部分の幅は、前記第1部分の幅よりも広い、半導体装置の製造方法。 - 請求項4に記載の半導体装置の製造方法において、
前記(g)工程の後に、さらに、
(i)前記第2ゲート電極の両端において、前記第2凸部の表面にエピタキシャル層を形成する工程、
を有する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(f)工程において、
前記第1絶縁膜は、前記第1凸部の表面に形成された酸化シリコン膜と、前記酸化シリコン膜上に形成された窒化シリコン膜と、
からなる、半導体装置の製造方法。 - (a)主面を有する半導体基板を準備する工程、
(b)前記半導体基板の前記主面の第1領域および第2領域に、夫々、第1マスク膜を形成する工程、
(c)前記第1領域および前記第2領域において、前記第1マスク膜の側壁上に、第2マスク膜を形成する工程、
(d)前記第1領域の前記第2マスク膜は残し、前記第2領域の前記第2マスク膜を除去する工程、
(e)前記第1領域においては、前記第1マスク膜の側壁上に前記第2マスク膜を介して、前記第2領域においては、前記第1マスク膜の側壁上に、直接、第3マスク膜を形成する工程、
(f)前記第1マスク膜を除去した後、前記第1領域においては、前記第2マスク膜および前記第3マスク膜の外側の前記半導体基板をエッチングして第1凹部を設けることで、前記第2マスク膜および前記第3マスク膜の下に、第1幅を有する第1凸部を形成し、前記第2領域においては、前記第3マスク膜の外側の前記半導体基板をエッチングして第2凹部を設けることで、前記第3マスク膜の下に、第2幅を有する第2凸部を形成する工程、
(g)前記第1領域において、前記第1凸部を跨ぐように、第1絶縁膜を介して第1ゲート電極を形成する工程、
(h)前記第2領域において、前記第2凸部を跨ぐように、第2絶縁膜を介して第2ゲート電極を形成する工程、
を有し、
前記第2幅は、前記第1幅よりも狭い、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記第1絶縁膜は、前記第1凸部を熱酸化して形成され、
前記第2絶縁膜は、前記第2凸部を熱酸化して形成され、
前記第1絶縁膜の膜厚は、前記第2絶縁膜の膜厚よりも厚い、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記(f)工程と前記(g)工程との間に、さらに、
(i)前記第1凸部および前記第2凸部の下部において、前記第1凸部および前記第2凸部の周囲を覆う絶縁膜からなる素子分離膜を形成する工程、
を有する、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記(g)工程において、
前記第1絶縁膜は、前記第1凸部の表面に形成された酸化シリコン膜と、前記酸化シリコン膜上に形成された窒化シリコン膜と、
からなる、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記(f)工程において、前記半導体基板のエッチングは、異方性ドライエッチングを用いる、半導体装置の製造方法。 - (a)主面を有する半導体基板を準備する工程、
(b)前記半導体基板の前記主面上に第1マスク膜を形成する工程、
(c)前記第1マスク膜の側壁上に、第2マスク膜を形成する工程、
(d)前記第2マスク膜の外側の前記半導体基板をエッチングして凹部を設け、前記第2マスク膜の下に、凸部を形成する工程、
(e)前記凹部内であって、前記凸部を取り囲むように第1絶縁膜からなる素子分離膜を形成する工程、
(f)前記凸部を跨ぐように、前記凸部上に、第2絶縁膜を介してゲート電極を形成する工程、
(g)前記ゲート電極を挟むように、前記凸部の表面にエピタキシャル層を形成する工程、
を有する、半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記凸部は、前記素子分離膜から露出した第1部分と、前記素子分離膜に周囲を囲まれた第2部分と、前記第1部分と前記第2部分との境界部分であって、その表面が前記素子分離膜から露出した第3部分と、を有し、
前記エピタキシャル層は、前記第1部分および前記第3部分に形成されている、半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記エピタキシャル層は、シリコンからなるエピタキシャル層である、半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記エピタキシャル層は、シリコンゲルマニウムからなるエピタキシャル層である、半導体装置の製造方法。
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US11217682B2 (en) | 2022-01-04 |
US20200111898A1 (en) | 2020-04-09 |
JP6620034B2 (ja) | 2019-12-11 |
US20170243955A1 (en) | 2017-08-24 |
TW201810533A (zh) | 2018-03-16 |
US10546946B2 (en) | 2020-01-28 |
CN107123649B (zh) | 2021-12-24 |
CN107123649A (zh) | 2017-09-01 |
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