WO2022067720A1 - 铁电存储器及其制作方法、存储设备 - Google Patents

铁电存储器及其制作方法、存储设备 Download PDF

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WO2022067720A1
WO2022067720A1 PCT/CN2020/119530 CN2020119530W WO2022067720A1 WO 2022067720 A1 WO2022067720 A1 WO 2022067720A1 CN 2020119530 W CN2020119530 W CN 2020119530W WO 2022067720 A1 WO2022067720 A1 WO 2022067720A1
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metal layer
layer
ferroelectric
semiconductor
ferroelectric memory
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PCT/CN2020/119530
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English (en)
French (fr)
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张瑜
许俊豪
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华为技术有限公司
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Priority to PCT/CN2020/119530 priority Critical patent/WO2022067720A1/zh
Priority to CN202080104470.6A priority patent/CN116097452A/zh
Publication of WO2022067720A1 publication Critical patent/WO2022067720A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors

Definitions

  • the present application relates to the field of memory, and in particular, to a ferroelectric memory, a method for making the same, and a storage device.
  • Ferroelectric field effect transistor has a very broad application prospect in high-density storage technology due to its advantages of high speed, low power consumption, high integration density and non-destructive readout.
  • FeFET uses the reversal of ferroelectric polarization (ie, the generation of electric dipole moment) in the ferroelectric layer to control the switching of channel current to read and write voltage, thereby realizing the storage function, but FeFET is easily caused by the charge trapping effect. Ferroelectric degradation, which in turn results in low endurance of FeFETs.
  • Embodiments of the present application provide a ferroelectric memory, a method for manufacturing the same, and a storage device, which can improve the durability of the ferroelectric memory.
  • the present application provides a ferroelectric memory, which is composed of at least one storage unit, and the storage unit includes: a columnar semiconductor channel portion, a source portion, and a drain portion, wherein the source portion and the drain portion are respectively arranged at two ends of the semiconductor channel portion and connected;
  • the memory cell further includes a first dielectric layer and a first metal layer arranged on the side of the semiconductor channel portion in sequence; a ferroelectric layer and a second metal layer stacked on the surface of the first metal layer, the ferroelectric layer is located on the between a metal layer and a second metal layer.
  • the ferroelectric field effect transistor used in the ferroelectric memory provided by the embodiment of the present application, by arranging a first metal layer around the semiconductor channel portion between the ferroelectric layer and the first dielectric layer, on the one hand, a vertical direction can be formed. channel, reducing the size of the ferroelectric field effect transistor; on the other hand, the first metal layer acts as a floating gate layer, which can trap carriers from the channel (ie, the semiconductor channel portion), thereby avoiding the ferroelectric layer
  • the ferroelectric degradation problem due to the trapping of carriers from the channel increases the durability of the ferroelectric memory.
  • the first dielectric layer covers all sides of the semiconductor channel portion.
  • the projection of the first metal layer on the semiconductor channel portion covers all sides of the semiconductor channel portion, so as to ensure effective control of the entire semiconductor channel portion by the first metal layer.
  • the ferroelectric layer covers only part of the surface of the first metal layer; by reducing the area of the ferroelectric layer, a higher voltage drop across the ferroelectric layer is ensured, sufficient polarization is achieved, and the The energy consumption of the entire ferroelectric field effect tube is reduced to achieve the purpose of energy saving.
  • the projection of the second metal layer on the side of the semiconductor channel portion is in a region of the projection of the ferroelectric layer on the side of the semiconductor channel portion.
  • the ferroelectric layer includes at least one of a ferroelectric material and an antiferroelectric material.
  • the first dielectric layer, the first metal layer, the ferroelectric layer and the second metal layer are sequentially disposed on the surface of the semiconductor channel portion.
  • the source part and the drain part use a heavily doped P-type semiconductor structure, and the semiconductor channel part uses a lightly doped P-type semiconductor structure.
  • the same dopant atoms can be used for the semiconductor channel portion, the source portion, and the drain portion, so that the fabrication process can be simplified and the fabrication cost can be reduced.
  • the source portion and the drain portion may adopt a heavily doped N-type semiconductor structure, and the semiconductor channel portion may adopt a lightly doped N-type semiconductor structure.
  • the same dopant atoms can be used for the semiconductor channel portion, the source portion, and the drain portion, so that the fabrication process can be simplified and the fabrication cost can be reduced.
  • An embodiment of the present application also provides a storage device, including a word line, a source line, a bit line, and a ferroelectric memory;
  • the ferroelectric memory includes: a columnar semiconductor channel portion, a source portion, and a drain portion, and the source portion and the drain portion are respectively set at both ends of the semiconductor channel portion;
  • the ferroelectric memory also includes: a first dielectric layer, a first metal layer and a ferroelectric layer stacked on the surface of the first metal layer, which are arranged in sequence on the side of the semiconductor channel portion.
  • the ferroelectric layer is located between the first metal layer and the second metal layer; the second metal layer of the ferroelectric memory is connected to the word line, the source of the ferroelectric memory is connected to the source line, and the ferroelectric memory The drain is connected to the bit line.
  • a memory device includes a plurality of source lines, a plurality of word lines, a plurality of bit lines, and a plurality of ferroelectric memories arranged in an array; each of the plurality of ferroelectric memories is associated with a source line, a word line and a bit line are connected.
  • the ferroelectric layer covers only part of the surface of the first metal layer.
  • the projection of the second metal layer on the side of the semiconductor channel portion is in a region of the projection of the ferroelectric layer on the side of the semiconductor channel portion.
  • the storage device includes at least one crossbar array structure;
  • the crossbar array structure includes: a plurality of ferroelectric memories arranged in a matrix, a plurality of word lines extending in the same direction, and a plurality of source lines extending in the same direction , a plurality of bit lines with the same extension direction; the second metal layer of the ferroelectric memory located in the same column is connected to the same word line, the source part of the ferroelectric memory located in the same column is connected to the same source line, and the drain of the ferroelectric memory located in the same column is connected to the same word line. are connected to the same bit line.
  • the storage device includes at least one crossbar array structure;
  • the crossbar array structure includes: a plurality of ferroelectric memories arranged in a matrix, a plurality of word lines extending in the same direction, and a plurality of source lines extending in the same direction , a plurality of bit lines with the same extension direction;
  • the second metal layer of the ferroelectric memory located in the same line is connected to the same word line;
  • the source part of the ferroelectric memory located in the same line is connected to the same source line, and the drain of the ferroelectric memory located in the same column is connected to the same word line.
  • the drain parts of the ferroelectric memories located in the same row are connected to the same bit line, and the source parts of the ferroelectric memories located in the same column are connected to the same source line.
  • the cross array structure can further reduce the area of the ferroelectric memory by arranging the ferroelectric memory in a matrix; and the cross array structure can realize parallel read and write operations on the same word line or the same bit line, thereby improving the read and write efficiency.
  • a plurality of crossbar array structures arranged in layers are included.
  • the three-dimensional stacking method is adopted, and the area of the ferroelectric memory can be further reduced; and the ultra-high-density ferroelectric memory using the three-dimensional stacking can provide a storage device with both high density and high performance, which can be applied to all Memory fields that require high performance and high density.
  • An embodiment of the present application provides a method for fabricating a ferroelectric memory, including:
  • a first electrode, a semiconductor column, and a first insulating layer are sequentially formed on the substrate; wherein, the semiconductor types of the two end portions of the semiconductor column and the regions between the two end portions are not identical.
  • a first dielectric layer, a first metal layer, a ferroelectric layer, a second metal layer, and a gate metal layer are sequentially formed on the substrate on which the first electrode, the semiconductor column, and the first insulating layer are formed.
  • the surface of the substrate on which the first dielectric layer, the first metal layer, the ferroelectric layer, the second metal layer and the gate metal layer are formed is planarized to expose the upper surfaces of the semiconductor pillars.
  • the first dielectric layer, the first metal layer, the ferroelectric layer, the second metal layer and the gate metal layer in the planarized substrate are etched, and the first dielectric layer, the first metal layer, the ferroelectric layer are retained.
  • the layer, the second metal layer, and the gate metal layer are on portions of the sides of the semiconductor pillars.
  • the surface of the substrate on which the first dielectric layer, the first metal layer, the ferroelectric layer, the second metal layer and the gate metal layer are formed is planarized to expose the semiconductor pillars After the upper surface of the substrate; after etching the first dielectric layer, the first metal layer, the ferroelectric layer, the second metal layer and the gate metal layer in the planarized substrate, the first dielectric layer, the first A metal layer, a ferroelectric layer, a second metal layer and a gate metal layer are located before the portion of the side surface of the semiconductor pillar; the manufacturing method further includes:
  • the second metal layer and the gate metal layer in the planarized substrate are etched and thinned, so that the upper surfaces of the second metal layer and the gate metal layer on the side surfaces of the semiconductor pillars are lower than the upper surfaces of the semiconductor pillars.
  • the surface of the substrate on which the first dielectric layer, the first metal layer, the ferroelectric layer, the second metal layer and the gate metal layer are formed is planarized to expose the semiconductor pillars After the upper surface of the substrate; after etching the first dielectric layer, the first metal layer, the ferroelectric layer, the second metal layer and the gate metal layer in the planarized substrate, the first dielectric layer, the first A metal layer, a ferroelectric layer, a second metal layer and a gate metal layer are located before the portion of the side surface of the semiconductor pillar; the manufacturing method further includes:
  • the second metal layer, the gate metal layer, and the ferroelectric layer in the planarized substrate are etched and thinned, so that the second metal layer, the second metal layer, the The upper surfaces of the gate metal layer and the ferroelectric layer are lower than the upper surfaces of the semiconductor pillars.
  • the manufacturing method further includes:
  • a second insulating layer is formed on the surface of the substrate, and holes are opened at the positions of the second insulating layer corresponding to the semiconductor pillars and the gate metal layer to expose the upper surfaces of the semiconductor pillars and the gate metal layer; the exposed upper surfaces of the semiconductor pillars are sequentially A second electrode and an electrode connection part are formed, and a gate connection part is formed on the surface of the exposed gate metal layer; wherein, one of the second electrode and the first electrode is a source electrode, and the other is a drain electrode.
  • the above-mentioned substrate includes a metal wiring layer and a first insulating layer disposed on the surface of the metal wiring layer; the first electrode is connected to the metal wiring layer through a metal via on the first insulating layer.
  • FIG. 1 is a schematic structural diagram of a ferroelectric field effect transistor according to an embodiment of the present application.
  • Fig. 2 is the sectional schematic diagram of Fig. 1 along AA' position
  • FIG. 3 is a top view of a ferroelectric field effect transistor according to an embodiment of the present application.
  • FIG. 4 is a top view of a ferroelectric field effect transistor according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a ferroelectric field effect transistor according to an embodiment of the present application.
  • Fig. 6 is the sectional schematic diagram of Fig. 5 along BB' position
  • FIG. 7 is a schematic structural diagram of a ferroelectric field effect transistor according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a capacitor equivalent circuit of a partial structure in a ferroelectric field effect transistor provided by an embodiment of the application;
  • FIG. 9 is a schematic diagram of a writing operation principle of a ferroelectric field effect transistor according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a writing operation principle of a ferroelectric field effect transistor according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a read operation principle of a ferroelectric field effect transistor according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a read operation principle of a ferroelectric field effect transistor according to an embodiment of the present application.
  • V G -ID of a ferroelectric field effect transistor provided by an embodiment of the application
  • FIG. 14 is a schematic diagram of a crossbar array structure provided by an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a crossbar array structure provided by an embodiment of the present application.
  • FIG. 16 provides a graph of the relationship between polarization and applied voltage of a ferroelectric material for an embodiment of the present application
  • FIG. 17 provides a graph of the relationship between polarization and applied voltage of a ferroelectric material for an embodiment of the present application.
  • FIG. 18 is a schematic diagram of a write operation of an interleaved array structure provided by an embodiment of the present application.
  • FIG. 19 is a schematic diagram of a write operation of a crossbar array structure provided by an embodiment of the present application.
  • 20 is a schematic diagram of a write operation of an interleaved array structure provided by an embodiment of the present application.
  • 21 is a schematic diagram of a write operation of an interleaved array structure provided by an embodiment of the present application.
  • 22 is a schematic diagram of a read operation of an interleaved array structure provided by an embodiment of the present application.
  • FIG. 23 is a schematic diagram of a read operation of an interleaved array structure provided by an embodiment of the present application.
  • FIG. 24 is a flowchart of a method for manufacturing a ferroelectric field effect transistor provided by an embodiment of the present application.
  • FIG. 25 is a schematic structural diagram of a ferroelectric field effect transistor in a manufacturing process according to an embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of a ferroelectric field effect transistor in a manufacturing process according to an embodiment of the present application.
  • FIG. 27 is a schematic structural diagram of a ferroelectric field effect transistor in a manufacturing process according to an embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of a ferroelectric field effect transistor in a manufacturing process according to an embodiment of the present application.
  • An embodiment of the present application provides a ferroelectric memory, the ferroelectric memory is provided with at least one storage unit, and each storage unit is provided with at least one ferroelectric field effect transistor; the present application does not have a different number of ferroelectric field effect transistors in the storage unit.
  • 6 ferroelectric field effect transistors can be set in one storage unit
  • 8 ferroelectric field effect transistors can also be set, of course, 1 ferroelectric field effect transistor can be set, in practice, the settings can be selected according to needs.
  • the ferroelectric field effect transistor provided in the embodiment of the present application adopts an MFM (metal-ferroelectric-metal) ferroelectric capacitor and a MOS (metal oxide semiconductor) tube is formed
  • the ferroelectric field effect tube can also be called MFMIS (metal ferroelectric metal insulator semiconductor) transistor; the use of this ferroelectric field effect tube can effectively improve the durability of ferroelectric memory, so as to meet various Memory endurance requirements for computing application scenarios.
  • the ferroelectric field effect transistor 01 includes: a columnar semiconductor channel C, and two ends of the semiconductor channel C are respectively disposed and a source portion S and a drain portion D connected to the semiconductor channel portion C.
  • the source part S is located below the semiconductor channel part C
  • the drain part D is located above the semiconductor channel part C for schematic illustration.
  • the source part S can be set above the semiconductor channel part C
  • the drain part D can be set below the semiconductor channel part C, which is not limited in this application.
  • the drain part D, the source part S and the semiconductor channel can be set as required. Relative position of Dao C.
  • the source portion S, the semiconductor channel portion C, and the drain portion D may be columnar structures as a whole; that is, the source portion S and the drain portion D are also columnar structures.
  • the source portion S, the semiconductor channel portion C, and the drain portion D may have the same diameter and concentric cylindrical structure; for another example, the source portion S and the drain portion D may also have different diameters and the same diameter as the semiconductor channel portion C. Columnar structure set on the axis.
  • the present application does not limit the type of the ferroelectric field effect transistor 01 .
  • the ferroelectric field effect transistor 01 may be of NPN type
  • the semiconductor channel portion C may be of a P-type semiconductor structure
  • the source portion S and the drain portion D may be of an N-type semiconductor structure.
  • the semiconductor channel portion C may adopt a boron (B) doped silicon (Si) semiconductor structure
  • the source portion S and the drain portion D may adopt a phosphorus (P) doped silicon (Si) semiconductor structure.
  • the ferroelectric field effect transistor 01 may be of a PNP type
  • the semiconductor channel portion C may be of an N-type semiconductor structure
  • the source portion S and the drain portion D may be of a P-type semiconductor structure.
  • the semiconductor channel portion C may be of a phosphorus-doped silicon semiconductor structure
  • the source portion S and the drain portion D may be of a boron-doped silicon semiconductor structure.
  • the semiconductor channel portion C of the ferroelectric field effect transistor 01 may adopt an N-type semiconductor structure, one of the source portion S and the drain portion D adopts a P-type semiconductor structure, and the other adopts a metal structure; for example,
  • the conductor channel portion C may be of a phosphorus-doped silicon semiconductor structure, the source portion S may be of a boron-doped silicon semiconductor structure, and the drain portion D may be of a copper metal structure.
  • the semiconductor channel portion C of the ferroelectric field effect transistor 01 may adopt a P-type semiconductor structure, one of the source portion S and the drain portion D adopts an N-type semiconductor structure, and the other adopts a metal structure; for example,
  • the conductor channel portion C may be of a boron-doped silicon semiconductor structure, the source portion S may be of a phosphorus-doped silicon semiconductor structure, and the drain portion D may be of a copper metal structure.
  • the ferroelectric field effect transistor 01 may be of an N+/N/N+ type structure, and the source part S and the drain part D may use a heavily doped N type semiconductor structure (that is, an N+ type semiconductor), and the semiconductor
  • the channel portion C may adopt a lightly doped N-type semiconductor structure; for illustration, the doping concentration of the N+-type semiconductor may be 1e20 cm ⁇ 3 ; the doping concentration of the N-type semiconductor structure may be less than or equal to 1e18 cm ⁇ 3 .
  • the semiconductor channel portion C, the source portion S, and the drain portion D may adopt a phosphorus-doped silicon semiconductor structure, and the phosphorus doping concentration in the source portion S and the drain portion D is higher than that in the semiconductor channel portion C. concentration.
  • the semiconductor channel portion C, the source portion S, and the drain portion D use the same dopant atoms (for example, phosphorus), so that the fabrication process can be simplified and the fabrication cost can be reduced.
  • the ferroelectric field effect transistor 01 can be of a P+/P/P+ type structure, and the source part S and the drain part D can use a heavily doped P-type semiconductor structure (that is, a P+-type semiconductor), and the semiconductor
  • the channel portion C may adopt a lightly doped P-type semiconductor structure.
  • the semiconductor channel portion C, the source portion S, and the drain portion D may adopt a boron-doped silicon semiconductor structure, and the boron doping concentration in the source portion S and the drain portion D is higher than that in the semiconductor channel portion C. concentration.
  • the same dopant atoms eg, boron
  • the fabrication process can be simplified and the fabrication cost can be reduced.
  • the ferroelectric field effect transistor 01 further includes: a first dielectric layer D1, a first metal layer D1, a first metal layer D1, a first metal layer D1 and a layer M1, and a ferroelectric layer (FE layer for short) F and a second metal layer M2 stacked on the surface of the first metal layer M1; wherein, the ferroelectric layer F is located in the first metal layer M1 and the second metal layer Between M2, the second metal layer M2 can be regarded as the gate G of the ferroelectric field effect transistor 01 .
  • the first dielectric layer D1, the first metal layer M1, the ferroelectric layer F, and the second metal layer M2 may all adopt a ring structure
  • the first dielectric layer D1 is arranged around the outer surface of the semiconductor channel portion C
  • the first metal layer M1 is arranged around the outer surface of the first dielectric layer D1
  • the ferroelectric layer F is arranged around the first metal layer M1
  • the second metal layer M2 is arranged around the outer side of the ferroelectric layer F; thus, a plurality of concentric annular structures with diameters increasing sequentially are formed on the side surface of the semiconductor channel portion.
  • the first dielectric layer D1 may cover all sides of the semiconductor channel portion C; of course, the first dielectric layer D1 may also extend to cover the source portion S.
  • the drain portion D is connected to the side surface of one end of the semiconductor channel portion C.
  • the projection of the first metal layer M1 on the semiconductor channel portion C may cover all sides of the semiconductor channel portion C; of course, the first metal layer M1 may also be arranged in the direction of It extends to above the side surfaces of the source part S and the drain part D, and the edge of the first metal layer M1 does not exceed the edge of the first dielectric layer D1 located therebelow.
  • the edge of the second metal layer M1 can generally be set not to exceed the edge of the ferroelectric layer F, and also That is, the projection of the second metal layer M2 on the side surface of the semiconductor channel portion C is located in the region where the ferroelectric layer F is projected on the side surface of the semiconductor channel portion C; for the size and shape of the ferroelectric layer F and the second metal layer M2 , position, etc., can be set as needed, as long as it is ensured that the channel threshold voltage can be regulated by the polarization of the ferroelectric layer F, so as to realize the on state (ie 0 state) and the off state (ie 1 state) of the ferroelectric field effect transistor 01 state) control to achieve the purpose of storage.
  • the ferroelectric layer F may be an acyclic structure (such as a semi-circular ring structure, a bulk structure, etc.) covering a partial surface of the first metal layer M1 , and the second metal layer M1 covers the ferroelectric layer
  • the surface of F is substantially the same as the shape of the ferroelectric layer F.
  • the ferroelectric layer F may be an annular structure covering the entire surface of the first metal layer M1, and the second metal layer M2 may be an acyclic structure covering only a partial surface of the first metal layer M1 Structure (such as semi-circular structure, block structure, etc.).
  • the ferroelectric layer F may only cover the annular structure of the partial surface of the first metal layer M1, and the second metal layer M1 is a ring-shaped structure covering the surface.
  • the ferroelectric layer F may be a ring-shaped structure covering only a partial surface of the first metal layer M1, and the second metal layer M1 is a ring-shaped structure covering a partial surface of the ferroelectric layer F. Ring structure on the surface.
  • the ferroelectric layer F is only located between the first metal layer M1 and the second metal layer M2
  • the part (F' region as shown in Figure 7) is used as an effective ferroelectric layer, that is, the ferroelectric layer F located between the first metal layer M1 and the second metal layer M2 is used as an effective ferroelectric layer, this part of the ferroelectric layer
  • the layers can be normally polarized under the action of the electric field formed by the first metal layer M1 and the second metal layer M2.
  • the ferroelectric layer F and the second metal layer M2 located on the surface of the ferroelectric layer F are correspondingly disposed in the upper region of the semiconductor channel portion C (that is, on the side close to the drain portion). area) is illustrated as an example, but the application is not limited to this. In some possible implementations, the ferroelectric layer F and the second metal layer M2 located on the surface of the ferroelectric layer F can also be correspondingly disposed in the semiconductor trench.
  • the lower region of the channel portion C that is, the region on the side close to the source portion S
  • the ferroelectric layer F may use a ferroelectric material; for example, Hf 0.5 Zr 0.5 O 2 ; in some possible implementations, the ferroelectric The layer F can use an antiferroelectric material; for example, ZrO 2 ; in some possible implementations, the ferroelectric layer F can use HZO (ie, Hf (1-x) Zr x O 2 ), where the Hf and Zr The component ratio is adjustable.
  • a ferroelectric material for example, Hf 0.5 Zr 0.5 O 2 ; in some possible implementations, the ferroelectric The layer F can use an antiferroelectric material; for example, ZrO 2 ; in some possible implementations, the ferroelectric layer F can use HZO (ie, Hf (1-x) Zr x O 2 ), where the Hf and Zr The component ratio is adjustable.
  • a ferroelectric field effect transistor is used.
  • a first metal layer By arranging a first metal layer around the semiconductor channel portion between the ferroelectric layer and the first dielectric layer, on the one hand, a channel in the vertical direction can be formed.
  • the first metal layer acts as a floating gate layer, which can trap carriers from the channel (that is, the semiconductor channel portion), thereby avoiding
  • the ferroelectric layer has the problem of ferroelectric degradation due to the trapping of carriers from the channel, which improves the durability of the ferroelectric memory.
  • the voltage drop (that is, the potential difference) on the metal layers (M1, M2) disposed on both sides of the ferroelectric layer F can be increased.
  • C F , C I , and C S represent the equivalent capacitances on the ferroelectric layer F, the first dielectric layer D1, and the semiconductor channel portion C, respectively.
  • C ⁇ S/4 ⁇ kd
  • ⁇ represents the dielectric constant of the capacitor
  • S represents the facing area of the capacitor plates
  • d represents the distance between the capacitor plates
  • k is the electrostatic force constant
  • the first dielectric layer D1 can be increased by increasing The dielectric constant ⁇ I of D1 is achieved.
  • the first dielectric layer D1 can be made of materials with high dielectric constants such as HfO 2 , HZO, Al 2 O 3 , etc.
  • the layer D1 can use HfO 2 ; for another example, the first dielectric layer D1 can use HZO; for another example, the first dielectric layer D1 can use a double-layer structure formed by a HfO 2 dielectric layer and a SiO 2 dielectric layer.
  • Increasing the ratio of the thickness d F of the ferroelectric layer F to the thickness d I of the first dielectric layer D1 can be achieved by increasing the thickness d F of the ferroelectric layer F.
  • the thickness d F of the ferroelectric layer F can be set to be about 10 nm
  • the thickness d I of the first dielectric layer D1 can be set to be about 2 nm.
  • the area S of the ferroelectric layer F can be reduced by reducing the area S
  • the area S F of the ferroelectric layer F is the area of the effective ferroelectric layer, that is, the area of the ferroelectric layer sandwiched between the first metal layer M1 and the second metal layer M2, For details, reference may be made to the foregoing related descriptions.
  • the ferroelectric layer F may only cover part of the surface of the first metal layer M1, that is, the ferroelectric layer F is on the side of the semiconductor channel portion C.
  • the projection only covers part of the side surface of the semiconductor channel portion C; for example, the height of the ferroelectric layer F may only account for 1/50-1/2 of the height of the first metal layer M1, and the area of the ferroelectric layer F is approximately the same as that of the first metal layer M1. 1/50 to 1/2 of the area of the layer M1.
  • the polarization state of the ferroelectric material in the ferroelectric layer F determines the non-volatile memory function of the ferroelectric field effect transistor 01, and the response of the ferroelectric material to the applied electric field is counterclockwise When the electric field is removed, the ferroelectric material will maintain a positive/negative polarization state, that is, the remanent polarization, and the threshold voltage of the channel can be regulated by the positive/negative remanent polarization. , to realize the storage function to the "0"/"1" state.
  • the ferroelectric field effect transistor 01 is a P-type field effect transistor
  • the semiconductor channel portion C can be an N-type Si semiconductor structure
  • the source portion S and the drain portion D A heavily doped P+ type Si semiconductor structure can be used.
  • the ferroelectric field effect transistor 01 is hereinafter adjusted by changing the polarization direction or polarization intensity of the ferroelectric layer F to adjust the electron accumulation or inversion on the surface of the channel, so as to change the ferroelectric field effect transistor.
  • the threshold voltage (threshold voltage) Vt of 01 is schematically illustrated.
  • the state with a low threshold voltage Vt is the "0" state
  • the state with a high threshold voltage Vt is the "1" state.
  • the three-terminal structure (ie, source, drain, gate) of the effect transistor 01 regulates the threshold voltage Vt, and the read and write operations of the "0" state and the "1" state are schematically illustrated.
  • the source part S and the drain part D of the ferroelectric field effect transistor 01 are connected to the ground terminal, and a forward bias voltage is applied to the gate part (ie M2). (+Vw), electrons are accumulated in the channel region, and the threshold voltage Vt of the ferroelectric field effect transistor 01 is high.
  • the source part S and the drain part D of the ferroelectric field effect transistor 01 are connected to the ground terminal, and a negative bias voltage is applied to the gate part (ie, M2 ). (-Vw), the channel is inversion, and the threshold voltage Vt of the ferroelectric field effect transistor 01 is low.
  • the source S of the ferroelectric field effect transistor 01 is connected to the ground terminal, the drain D applies a voltage V D , and the gate (ie, M2) applies a voltage V G .
  • the read current is ID_1 (refer to FIG. 13 )
  • the embodiments of the present application also provide a storage device, the storage device includes the ferroelectric memory provided in any of the foregoing possible implementation manners; at the same time, the storage device is also provided with a word line (word line), a source line (source line), bit line (bit line); the second metal layer M2 (that is, the gate part G) of the ferroelectric memory is connected to the word line, the source part S of the ferroelectric memory is connected to the source line, and the drain part of the ferroelectric memory D is connected to the bit line.
  • word line word line
  • source line source line
  • bit line bit line
  • the following further describes the arrangement between the ferroelectric memory and the word lines, source lines, and bit lines in the storage device.
  • the storage device may be provided with a crossbar structure 02; the crossbar structure 02 is provided with a plurality of ferroelectric memories 01 arranged in a matrix, a plurality of Word lines WL with the same extension direction, a plurality of source lines SL with the same extension direction, and a plurality of bit lines BL with the same extension direction.
  • 14 and 15 are only based on the fact that there are 9 ferroelectric memories 01 arranged in the cross array structure 02, and the 9 ferroelectric memories 01 are arranged in a matrix arrangement of 3 rows and 3 columns (that is, 3 ⁇ 3) as An example is used to illustrate, but the present application is not limited to this.
  • the number of ferroelectric memories 01 and the matrix arrangement can be set as required.
  • rows and columns are only a set of two relatively vertical (90°) directions, not absolute two directions; in some cases, rows can be regarded as columns, and columns can be regarded as Rows, that is, rows and columns are interchangeable.
  • connection between the three terminals (ie, G, S, D) of the ferroelectric memory 01 and the word line WL, the source line SL, and the bit line BL in the crossbar array structure 02 will be schematically described below through a specific arrangement.
  • the gate portion G (ie, the second metal layer M2 ) of the ferroelectric memory 01 located in the same row is connected to the same word line WL, and the gate portion G of the ferroelectric memory 01 located in a different row is connected to the same word line WL.
  • the gate part G is connected to different word lines WL;
  • the source parts S of the ferroelectric memories 01 located in the same column are connected to the same source line SL, and the source parts S of the ferroelectric memories 01 located in different columns are connected to different source lines SL;
  • the drains D of the ferroelectric memories 01 are connected to the same bit line BL, and the drains D of the ferroelectric memories 01 located in different columns are connected to different bit lines BL.
  • the source line SL is parallel to the bit line BL, and both the source line SL and the bit line BL are perpendicular to the word line WL.
  • the gate portion G (ie, the second metal layer M2 ) of the ferroelectric memory 01 located in the same row is connected to the same word line WL, and the gate portion G of the ferroelectric memory 01 located in a different row is connected to the same word line WL.
  • the gate part G is connected to different word lines WL;
  • the source parts S of the ferroelectric memories 01 located in the same row are connected to the same source line SL, and the source parts S of the ferroelectric memories 01 located in different rows are connected to different source lines SL;
  • the drains D of the ferroelectric memories 01 are connected to the same bit line BL, and the drains D of the ferroelectric memories 01 located in different columns are connected to different bit lines BL.
  • the source line SL is parallel to the word line WL, and both the source line SL and the word line WL are perpendicular to the bit line BL.
  • the positions of the bit line BL and the source line SL in FIG. 15 can be interchanged, that is, the source part S of the ferroelectric memory 01 located in the same column is connected to the same source line SL, and the source part S located in the same column is connected to the same source line SL.
  • the drain S of the ferroelectric memory 01 is connected to the same bit line BL.
  • the area of the ferroelectric memories 01 can be further reduced to 4F 2 .
  • a plurality of crossbar array structures 01 can be stacked (in other words, stacked up and down); in this case, compared with the SRAM
  • the unit area is above 140F 2
  • the unit area of DRAM is 8F 2
  • the unit area of STT-MRAM is 60F 2
  • the three-dimensional stacking method is adopted in this application, and the area of ferroelectric memory 01 can be further reduced to 2F 2 , 1.33F 2 , 1F 2 ; based on this, the application of the three-dimensional superimposed ultra-high-density ferroelectric memory 01 can provide a storage device with both high density and high performance, which can be applied to all memory fields that require high performance and high density .
  • the use of the cross array structure 01 can realize parallel read and write operations of the ferroelectric memory on the same word line WL or the same bit line BL, thereby improving the read and write efficiency.
  • the voltage of the write operation is determined by the potential difference between the word line WL and the bit line BL.
  • the ferroelectric memory 01 is written as "1" state; when the voltage difference between the word line WL and the bit line BL is -Vw, the ferroelectric memory 01 is written as "0" state; when the word line When the absolute value of the voltage difference between WL and the bit line BL is less than or equal to 1/2Vw, the state of the ferroelectric memory 01 remains unchanged.
  • the actual biasing scheme may be carried out on the basis of the following control voltage shift.
  • the Vw involved in this embodiment is a write voltage (write voltage), which is related to the structural setting of the ferroelectric memory 01 .
  • a 1/2Vw control method can be used. As shown in FIG. 18 , 1/2Vw and -1/2Vw are alternately applied to the word line WL connected to the ferroelectric memory 01 that is selected (ie, needs to be written)
  • the changed pulse signal for the ferroelectric memory 01 that wants to write the "1" state (the ferroelectric memory 01 marked with a black five-pointed star in Figure 18), the bit line BL and the source line connected to the ferroelectric memory 01
  • the voltage applied on SL is -1/2Vw, when the signal on the word line WL is 1/2Vw, the voltage drop on the ferroelectric memory 01 is Vw, and the ferroelectric memory 01 is written as "1" state.
  • the voltage applied on the bit line BL and the source line SL is +1/2Vw, when the word line WL
  • the voltage drop on the ferroelectric memory 01 is -Vw, and the ferroelectric memory 01 is written as "0" state.
  • the voltage applied to the bit line BL and the source line SL is 0, and the state is not rewritten. The state is also not overwritten.
  • this operation mode can realize the writing operation of a single ferroelectric memory 01 in the crossbar array structure 02, and can also perform the operation of simultaneously writing "0" and writing "1" to all the ferroelectric memories 01 connected by the selected word line WL .
  • the 1/3Vw control method can be used.
  • 1/3Vw and -1/3Vw alternate pulse signal is applied to the word line WL of , for the ferroelectric memory 01 that wants to write the "1" state (such as the ferroelectric memory 01 marked with a black pentagram in Figure 19),
  • the voltage applied to the bit line BL and the source line SL connected to the ferroelectric memory 01 is -1/3Vw, when the signal on the word line WL is 2/3Vw, the voltage drop on the ferroelectric memory 01 is Vw, the The ferroelectric memory 01 is written in the "1" state.
  • the ferroelectric memory 01 that wants to write the "0" state (the ferroelectric memory 01 marked with a gray five-pointed star in Fig. 19 )
  • the voltage applied to the bit line BL and the source line SL connected to the ferroelectric memory 01 is +1/3Vw, when the signal on the word line WL is -2/3Vw, the voltage drop on the ferroelectric memory 01 is -Vw, and the ferroelectric memory 01 is written as "0" state.
  • the state of all ferroelectric memories 01 on the unselected word line WL will not be rewritten.
  • This operation mode can simultaneously write "0" and write "1" to all the ferroelectric memories 01 connected to the selected word line WL.
  • the 1/2Vw control method can be used. As shown in FIG. 20, the bias voltage +1/2Vw can be applied to all the source lines SL; The word line WL connected by 01 applies a pulse signal of 1/2Vw and -1/2Vw alternately; for the ferroelectric memory 01 that wants to write the "1" state (the ferroelectric memory 01 marked with a black five-pointed star in Figure 20) and In other words, apply a voltage -1/2Vw to the bit line BL connected to it, when the signal on the word line WL is 1/2Vw, the voltage drop on the ferroelectric memory 01 is Vw, the ferroelectric memory 01 is written as " 1" state; for the ferroelectric memory 01 that wants to write the "0" state (the ferroelectric memory 01 marked with a gray five-pointed star in Figure 20), apply a voltage +1/2Vw to the bit line BL connected to it, when When the signal on the word line WL is -1/2Vw, the voltage drop on the ferroelectric memory 01 is
  • the voltage applied on the bit line BL is 0, and the state is not rewritten.
  • the state is also not changed. rewrite.
  • This operation mode can realize the write operation of a single ferroelectric memory 01 in the crossbar array structure 02, and can also simultaneously write "0" and write "1" to all the ferroelectric memories 01 connected by the word line WL.
  • the 1/3Vw control method can be used.
  • the bias voltage +1/3Vw can be applied to all the source lines SL;
  • the word line WL connected by 01 applies a pulse signal of 2/3Vw and -2/3Vw alternately; for the ferroelectric memory 01 that wants to write the "1" state (such as the ferroelectric memory 01 marked with a black five-pointed star in Figure 21) and
  • apply a voltage -1/3Vw to the bit line BL connected to it when the signal on the word line WL is 2/3Vw, the voltage drop on the ferroelectric memory 01 is Vw, the ferroelectric memory 01 is written as " 1" state; for the ferroelectric memory 01 that wants to write the "0" state (such as the ferroelectric memory 01 marked with a gray five-pointed star in Figure 21), apply a voltage +1/3Vw to the bit line BL connected to it, when When the signal on the word line WL is -2/3Vw, the voltage drop on
  • This operation mode can realize the write operation of a single ferroelectric memory 01 in the crossbar structure 02, and can also perform the operation of simultaneously writing "0" and "1" to all the ferroelectric memories 01 connected by the word line WL.
  • the voltages applied to all source lines SL are 0V, and the selected (that is, the read operation) ferroelectric memory 01 (marked in black in FIG. 22 ) is 0V.
  • the voltage V G is applied to the word line WL connected to the ferroelectric memory 01) of the five-pointed star, and the remaining word lines WL are all connected to 0V;
  • the voltage VR is applied to the bit line BL connected to the selected ferroelectric memory 01, and the remaining bit lines BL are all connected to 0V .
  • all bit lines BL are connected to the bias voltage VR , and the selected (that is, the read operation) ferroelectric memory 01 (marked with black pentagons in FIG. 22)
  • the source line SL connected to the star's ferroelectric memory 01) is connected to 0V voltage, and the remaining source lines SL are all applied with voltage VR ;
  • the word line WL connected to the selected ferroelectric memory 01 is connected to voltage VG , and the rest are connected to 0V voltage; In this case, all the ferroelectric memories 01 connected to the word line WL are turned on, and data reading is performed.
  • the embodiment of the present application also provides a method for fabricating a ferroelectric memory 01. Using this fabrication method, one ferroelectric memory 01 can be fabricated in one process, and multiple ferroelectric memories 01 can also be fabricated at the same time.
  • the following implementations The example is only for illustrative illustration by taking one of the plurality of ferroelectric memories 01 as an example.
  • the manufacturing method of the ferroelectric memory 01 may include:
  • Step 01. Referring to FIG. 25 (a), a first electrode 2, a semiconductor column 3, and a first insulating layer 4 are formed in sequence on the substrate 1; wherein, the two ends of the semiconductor column 3 and the two ends The semiconductor types in the regions are not exactly the same.
  • This application does not limit the specific setting form of the substrate 1, which can be set according to the application scenario of the ferroelectric memory in practice; for example, in some possible implementations, as shown in (a) of FIG.
  • a substrate such as a silicon substrate, not shown in FIG. 25 ), a metal wiring layer 11 and a second insulating layer 12 arranged on the surface of the substrate in sequence; the first electrode 2 passes through a metal via located on the second insulating layer 13 V is connected to the metal wiring layer 12 .
  • the aforementioned first insulating layer 11 and second insulating layer 12 can be made of oxides, nitrides, etc., such as silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the first insulating layer 11 disposed on the upper surface of the semiconductor column 3 serves as an etching barrier layer, which can protect the upper surface of the semiconductor column 3 in the subsequent fabrication process.
  • the aforementioned metal vias V may be formed by first forming through holes on the insulating layer 13, and then depositing metals such as copper and tungsten in the through holes.
  • the two end portions of the semiconductor pillar 3 may use a P-type semiconductor, and the region between the two end portions may use an N-type semiconductor.
  • the above step 01 may include: forming a metal wiring layer 11 and an insulating layer 12 on the silicon substrate in sequence, and forming a metal via V on the insulating layer 12;
  • the first electrode 2 , the semiconductor column 3 , and the first insulating layer 4 are formed in sequence at the positions corresponding to the metal vias V by using a patterning process.
  • the "patterning process" involved in the embodiments of the present application may refer to including a photolithography process, or including a photolithography process and an etching step, wherein the etching step may be dry etching Etching (dry etch), can also be wet etching (wet etch), etc.; lithography process refers to the use of photoresist, mask, exposure machine, etc. Process; in practice, a corresponding patterning process can be selected according to the structure formed in the present application.
  • Step 02 Referring to FIG. 25(b), on the substrate 1 formed with the first electrode 2, the semiconductor column 3, and the first insulating layer 4, the first dielectric layer 5, the first metal layer 6, the iron layer 4 are sequentially formed Electrical layer 7 , second metal layer 8 and gate metal layer 9 .
  • the above step 02 may include: using a deposition process, a sputtering process or an electroplating process, etc., to sequentially prepare a certain thickness of the first dielectric layer 5 , the first metal layer 6 , Ferroelectric layer 7 , second metal layer 8 and gate metal layer 9 . It should be noted here that when the gate metal layer 9 is fabricated, it should be ensured that the thickness of the gate metal layer 9 covers the height of the entire semiconductor pillar 3 .
  • ferroelectric layer 7 it is generally necessary to perform high-temperature annealing after depositing the ferroelectric material, so as to crystallize the ferroelectric material. After (5, 6, 7, 8), an annealing process is used to form the crystallized ferroelectric layer 7 .
  • Step 03. Referring to FIG. 25(c), the surface of the substrate 1 on which the first dielectric layer 5, the first metal layer 6, the ferroelectric layer 7, the second metal layer 8 and the gate metal layer 9 are formed A planarization process is performed to expose the upper surfaces of the semiconductor pillars 3 .
  • the above step 03 may include: chemical mechanical planarization (CMP) is used to form the first dielectric layer 5 , the first metal layer 6 , the ferroelectric
  • CMP chemical mechanical planarization
  • the surface of the substrate 1 of the layer 7, the second metal layer 8 and the gate metal layer 9 is planarized to remove the first insulating layer 4, the first dielectric layer 5, the first metal layer 6,
  • the ferroelectric layer 7 , the second metal layer 8 and the gate metal layer 9 to expose the upper surface of the semiconductor pillar 3 .
  • a part of the thickness of the first insulating layer 4 may be retained, and then removed in a subsequent manufacturing process.
  • Step 04 Referring to FIG. 25(d), for the first dielectric layer 5, the first metal layer 6, the ferroelectric layer 7, the second metal layer 8 and the gate metal layer in the planarized substrate 1 9. Etching is performed, and the portions of the first dielectric layer 5, the first metal layer 6, the ferroelectric layer 7, the second metal layer 8 and the gate metal layer 9 located on the side surfaces of the semiconductor pillar 3 are retained.
  • a patterning process is used to perform a patterning process on the first dielectric layer 5, the first metal layer 6, the ferroelectric layer 7, and the second metal layer 8 in the planarized substrate 1.
  • the gate metal layer 9 is etched, and the part located on the side of the semiconductor column 3 is reserved (of course, the part extending from the side to the surface of the substrate 1 can also be appropriately reserved), so as to form the core part of the single ferroelectric memory. Reference may be made to the aforementioned ferroelectric memory 01 shown in FIG. 1 .
  • the method for fabricating the ferroelectric memory may further include: as shown in FIG. 26 , for the second metal layer 8, The gate metal layer 9 is etched and thinned, so that the upper surfaces of the second metal layer 8 and the gate metal layer 9 on the side surfaces of the semiconductor pillar 3 are lower than the upper surface of the semiconductor pillar 3 .
  • the method for fabricating the ferroelectric memory may further include: as shown in FIG. 27 , for the gate metal layer in the planarized substrate 1 9.
  • the second metal layer 8 and the ferroelectric layer 7 are etched and thinned, so that the upper surfaces of the gate metal layer 9 , the second metal layer 8 and the ferroelectric layer 7 on the side of the semiconductor column 3 are lower than the semiconductor column 3 the upper surface.
  • the above-mentioned etching and thinning process of the gate metal layer 9 and the second metal layer 8, or the gate metal layer 9, the second metal layer 8, and the ferroelectric layer 7 may be a single etching process, or may be a single etching process. Multiple etching processes are not limited in this application. In practice, a suitable process can be selected according to needs.
  • ferroelectric layer 7 located on the side of the semiconductor pillar 3, only the part sandwiched between the first metal layer 6 and the second metal layer 8 is used as an effective ferroelectric layer.
  • the layer 6 and the second metal layer 8 are normally polarized under the action of the electric field.
  • reducing the area of the effective ferroelectric layer 7 a higher voltage drop can be obtained on the ferroelectric layer F, so that the ferroelectric material is fully polarized; for details, please refer to the corresponding description in the foregoing embodiment of the ferroelectric field effect transistor 01.
  • the method for fabricating the above-mentioned ferroelectric memory may further include:
  • Step 05 Referring to FIG. 28, an insulating layer 13 is formed on the surface of the substrate 1, and holes are opened at the positions of the insulating layer 13 corresponding to the semiconductor pillars 3 and the gate metal layer 9 to expose the semiconductor pillars 3 and the gate metal layer 9.
  • the second electrode 31 and the electrode connecting portion 32 are sequentially formed on the upper surface of the exposed semiconductor pillar 3 , and the gate connecting portion 91 is formed on the surface of the exposed gate metal layer 9 .
  • the second electrode 31 formed in the above step 05 and the first electrode 2 formed in the above step 01 one is the source electrode, and the other is the drain electrode; for example, the first electrode 2 can be the source electrode, the first electrode The second electrode 31 is a drain.
  • the above step 05 may include forming an insulating layer 13 on the surface of the substrate 1 formed in step 04, and performing a planarization process on the surface of the insulating layer 13 through a chemical mechanical planarization process; then , the insulating layer 13 is etched (such as a photolithography process), and holes are opened at the positions of the insulating layer 13 corresponding to the semiconductor column 3 and the gate metal layer 9 to expose the upper surface of the semiconductor column 3 and the gate metal layer 9; Next, a second electrode 31 is formed on the surface of the exposed semiconductor pillar 3 through a patterning process using metals such as nickel (Ni) and titanium (Ti); The patterning process forms the electrode connecting portion 32 on the surface of the second electrode 31 , and forms the gate connecting portion 91 on the surface where the gate metal layer 9 is exposed.

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Abstract

本申请提供了一种铁电存储器及其制作方法、存储设备，涉及存储器领域，能够提高铁电存储器的耐用性。铁电存储器由至少一个存储单元构成，存储单元包括：柱状的半导体沟道部、源部、漏部；源部和漏部分别设置于半导体沟道部的两端；该存储单元还包括在半导体沟道部的侧面上依次环绕设置的第一介电层、第一金属层；层叠设置在第一金属层表面的铁电层和第二金属层；铁电层位于第一金属层和第二金属层之间。

Description

铁电存储器及其制作方法、存储设备 技术领域
本申请涉及存储器领域，尤其涉及一种铁电存储器及其制作方法、存储设备。
背景技术
铁电场效应晶体管(ferroelectric field effect transistor，FeFET)因具有高速、低功耗、高集成密度和非破坏性读出等优点，在高密度存储技术中具有非常广阔的应用前景。FeFET利用铁电层中铁电极化(也即产生电偶极矩)的翻转来控制沟道电流的开关以进行电压的读写，从而实现存储功能，但是FeFET容易因电荷俘获(charge trapping)效应导致铁电退化，进而造成FeFET的耐用性(endurance)低。
发明内容
本申请实施例提供一种铁电存储器及其制作方法、存储设备，能够提高铁电存储器的耐用性。
本申请提供一种铁电存储器，由至少一个存储单元构成，存储单元包括：柱状的半导体沟道部、源部、漏部，源部和漏部分别设置于半导体沟道部的两端连；该存储单元还包括在半导体沟道部的侧面上依次设置有第一介电层、第一金属层；层叠设置在第一金属层表面的铁电层和第二金属层，铁电层位于第一金属层和第二金属层之间。
本申请实施例提供的铁电存储器中采用的铁电场效应管，通过在铁电层与第一介电层之间环绕半导体沟道部设置第一金属层，一方面，能够形成垂直方向上的沟道，降低铁电场效应管的尺寸；另一方面，该第一金属层作为浮栅层，能够俘获来自沟道(也即半导体沟道部)处的载流子，从而避免了铁电层因俘获来自沟道处的载流子而产生铁电退化问题，提高了铁电存储器的耐用性。
在一些可能实现的方式中，第一介电层覆盖半导体沟道部的全部侧面。
在一些可能实现的方式中，第一金属层在半导体沟道部上的投影覆盖半导体沟道部的全部侧面；以保证第一金属层对整个半导体沟道部的有效控制。
在一些可能实现的方式中，铁电层仅覆盖第一金属层的部分表面；通过减小铁电层的面积，保证铁电层上获得更高的电压降，进行充分极化，并且还能够降低整个铁电场效应管的能耗，达到节能的目的。
在一些可能实现的方式中，第二金属层在半导体沟道部侧面上的投影位于铁电层在半导体沟道部侧面上的投影的区域内。
在一些可能实现的方式中，铁电层包括铁电材料、反铁电材料中的至少一种。
在一些可能实现的方式中，第一介电层、第一金属层、铁电层和第二金属层依次环绕设置在半导体沟道部的表面。
在一些可能实现的方式中，源部和漏部采用重掺杂的P型半导体结构，半导体沟道部采用轻掺杂的P型半导体结构。在此情况下，半导体沟道部、源部、漏部可以采用相同的 掺杂原子，从而能够简化制作工艺，降低制作成本。
在一些可能实现的方式中，源部和漏部可以采用重掺杂的N型半导体结构，半导体沟道部可以采用轻掺杂的N型半导体结构。在此情况下，半导体沟道部、源部、漏部可以采用相同的掺杂原子，从而能够简化制作工艺，降低制作成本。
本申请实施例还提供一种存储设备，包括字线、源线、位线以及铁电存储器；铁电存储器包括：柱状的半导体沟道部、源部和漏部，源部和漏部分别设于半导体沟道部的两端；铁电存储器还包括：在半导体沟道部的侧面上依次环绕设置的第一介电层、第一金属层，以及层叠设置在第一金属层表面的铁电层和第二金属层；铁电层位于第一金属层和第二金属层之间；铁电存储器的第二金属层与字线连接，铁电存储器的源部与源线连接，铁电存储器的漏部与位线连接。
在一些可能实现的方式中，存储设备包括多条源线、多条字线、多条位线，以及呈阵列排布的多个铁电存储器；多个铁电存储器中的每一个与一条源线、一条字线和一条位线相连。
在一些可能实现的方式中，铁电层仅覆盖第一金属层的部分表面。
在一些可能实现的方式中，第二金属层在半导体沟道部侧面上的投影位于铁电层在半导体沟道部侧面上的投影的区域内。
在一些可能实现的方式中，存储设备包括至少一个交叉阵列结构；交叉阵列结构包括：成矩阵排布的多个铁电存储器、多条延伸方向相同的字线、多条延伸方向相同的源线、多条延伸方向相同的位线；位于同行的铁电存储器的第二金属层与同一字线连接，位于同列的铁电存储器的源部与同一源线连接，位于同列的铁电存储器的漏部与同一位线连接。
在一些可能实现的方式中，存储设备包括至少一个交叉阵列结构；交叉阵列结构包括：成矩阵排布的多个铁电存储器、多条延伸方向相同的字线、多条延伸方向相同的源线、多条延伸方向相同的位线；位于同行的铁电存储器的第二金属层与同一字线连接；位于同行的铁电存储器的源部与同一源线连接，位于同列的铁电存储器的漏部与同一位线连接；或者，位于同行的铁电存储器的漏部与同一位线连接，位于同列的铁电存储器的源部与同一源线连接。
交叉阵列结构通过将铁电存储器矩阵排布，能够进一步的将铁电存储器的面积微缩；并且采用交叉阵列结构可以实现同字线或同位线的并行读写操作，从而能够提高读写效率。
在一些可能实现的方式中，包括层叠设置的多个交叉阵列结构。
本申请中采用三维叠加的方式，铁电存储器的面积可以进一步微缩；并且采用三维叠加的超高密度的铁电存储器可以提供一种兼具高密度和高性能的存储设备，进而能够应用于所有需要高性能和高密度的存储器领域。
本申请实施例提供一种铁电存储器的制作方法，包括：
在基板上依次形成第一电极、半导体柱、第一绝缘层；其中，半导体柱的两个端部、以及两个端部之间的区域的半导体类型不完全相同。
在形成有第一电极、半导体柱、第一绝缘层的基板上，依次形成第一介电层、第一金属层、铁电层、第二金属层和栅极金属层。
对形成有第一介电层、第一金属层、铁电层、第二金属层和栅极金属层的基板的表面 进行平坦化处理，露出半导体柱的上表面。
对平坦化后的基板中的第一介电层、第一金属层、铁电层、第二金属层和栅极金属层进行刻蚀，保留第一介电层、第一金属层、铁电层、第二金属层和栅极金属层位于半导体柱侧面的部分。
在一些可能实现的方式中，在对形成有第一介电层、所述第一金属层、铁电层、第二金属层和栅极金属层的基板的表面进行平坦化处理，露出半导体柱的上表面之后；在对平坦化后的基板中的第一介电层、第一金属层、铁电层、第二金属层和栅极金属层进行刻蚀，保留第一介电层、第一金属层、铁电层、第二金属层和栅极金属层位于半导体柱侧面的部分之前；该制作方法还包括：
对平坦化后的基板中的第二金属层、栅极金属层进行刻蚀减薄，以使得位于半导体柱侧面的第二金属层和栅极金属层的上表面低于半导体柱的上表面。
在一些可能实现的方式中，在对形成有第一介电层、所述第一金属层、铁电层、第二金属层和栅极金属层的基板的表面进行平坦化处理，露出半导体柱的上表面之后；在对平坦化后的基板中的第一介电层、第一金属层、铁电层、第二金属层和栅极金属层进行刻蚀，保留第一介电层、第一金属层、铁电层、第二金属层和栅极金属层位于半导体柱侧面的部分之前；该制作方法还包括：
对平坦化后的基板中的所述第二金属层、所述栅极金属层、所述铁电层进行刻蚀减薄，以使得位于所述半导体柱侧面的所述第二金属层、所述栅极金属层、所述铁电层的上表面低于所述半导体柱的上表面。
在一些可能实现的方式中，在对平坦化后的基板中的第一介电层、第一金属层、铁电层、第二金属层和栅极金属层进行刻蚀，保留第一介电层、第一金属层、铁电层、第二金属层和栅极金属层位于半导体柱侧面的部分之后，该制作方法还包括：
在基板的表面形成第二绝缘层，并在第二绝缘层对应半导体柱以及栅极金属层的位置开孔，露出半导体柱以及栅极金属层的上表面；在露出的半导体柱的上表面依次形成第二电极和电极连接部，在露出的栅极金属层的表面形成栅极连接部；其中，第二电极和第一电极一个为源极，另一个为漏极。
在一些可能实现的方式中，上述基板包括金属布线层、设置在金属布线层表面的第一绝缘层；第一电极通过位于第一绝缘层上的金属过孔与金属布线层连接。
附图说明
图1为本申请实施例提供的一种铁电场效应管的结构示意图；
图2为图1沿AA’位置的剖面示意图；
图3为本申请实施例提供的一种铁电场效应管的俯视图；
图4为本申请实施例提供的一种铁电场效应管的俯视图；
图5为本申请实施例提供的一种铁电场效应管的结构示意图；
图6为图5沿BB’位置的剖面示意图；
图7为本申请实施例提供的一种铁电场效应管的结构示意图；
图8为申请实施例提供的一种铁电场效应管中的部分结构的电容等效电路示意图；
图9为本申请实施例提供的一种铁电场效应管的写操作原理示意图；
图10为本申请实施例提供的一种铁电场效应管的写操作原理示意图；
图11为本申请实施例提供的一种铁电场效应管的读操作原理示意图；
图12为本申请实施例提供的一种铁电场效应管的读操作原理示意图；
图13为本申请实施例提供的一种铁电场效应管的V G-I D的曲线图；
图14为本申请实施例提供的一种交叉阵列结构的示意图；
图15为本申请实施例提供的一种交叉阵列结构的示意图；
图16为本申请实施例提供一种关于铁电材料的极化强度与外加电压关系的曲线图；
图17为本申请实施例提供一种关于铁电材料的极化强度与外加电压关系的曲线图；
图18为本申请实施例提供的一种交叉阵列结构的写操作的示意图；
图19为本申请实施例提供的一种交叉阵列结构的写操作的示意图；
图20为本申请实施例提供的一种交叉阵列结构的写操作的示意图；
图21为本申请实施例提供的一种交叉阵列结构的写操作的示意图；
图22为本申请实施例提供的一种交叉阵列结构的读操作的示意图；
图23为本申请实施例提供的一种交叉阵列结构的读操作的示意图；
图24为本申请实施例提供的一种铁电场效应管的制作方法流程图；
图25为本申请实施例提供的一种铁电场效应管制作过程中的结构示意图；
图26为本申请实施例提供的一种铁电场效应管制作过程中的结构示意图；
图27为本申请实施例提供的一种铁电场效应管制作过程中的结构示意图；
图28为本申请实施例提供的一种铁电场效应管制作过程中的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种铁电存储器，该铁电存储器中设置有至少一个存储单元，每一存储单元中设置有至少一个铁电场效应管；本申请对于存储单元中铁电场效应管的个数不做限制，例如，一个存储单元中可以设置6个铁电场效应管，也可以设置8个铁电场效应管，当然也可以设置1个铁电场效应管，实际中可以根据需要选择设置即可。
相比于现有技术中的铁电场效应管的耐用性低(一般在10 6以下)而言，本申请实施例提供的铁电场效应管采用一个MFM(metal-ferroelectric-metal)铁电容和一个MOS(metal  oxide semiconductor)管形成，该铁电场效应管也可以称为MFMIS(metal ferroelectric metal insulator semiconductor)晶体管；采用该铁电场效应管能够有效的提高铁电存储器的耐用性，从而能够满足各种计算应用场景对存储器耐用性的要求。
以下对本申请实施例提供的铁电场效应管的具体设置方式进行具体说明。
如图1和图2(图1沿AA’位置的剖面示意图)所示，该铁电场效应管01包括：柱状的半导体沟道部(channel)C，以及分别设置在半导体沟道部C两端、且与半导体沟道部C连接的源部(source)S和漏部(drain)D。其中，图2中仅是示意的以源部S位于半导体沟道部C的下方，漏部D位于半导体沟道部C的上方为例进行示意说明的，在另一些可能实现的方式中，也可以设置源部S位于半导体沟道部C的上方，漏部D位于半导体沟道部C的下方，本申请对此不做限制，实际中可以根据需要设置漏部D、源部S与半导体沟道部C的相对位置。
在一些可能实现的方式中，参考图2所示，源部S、半导体沟道部C、漏部D整体可以为柱状结构；也即，源部S和漏部D也为柱状结构。例如，源部S、半导体沟道部C、漏部D可以直径相同、且同轴心的圆柱结构；又例如，源部S和漏部D也可以与半导体沟道部C的直径不同、同轴心设置的柱状结构。
另外，本申请对于该铁电场效应管01的类型不做限制。
在一些可能实现的方式中，该铁电场效应管01可以为NPN型，半导体沟道部C可以采用P型半导体结构，源部S和漏部D可以采用N型半导体结构。例如，半导体沟道部C可以采用硼(B)掺杂的硅(Si)半导体结构，源部S和漏部D可以采用磷(P)掺杂的硅(Si)半导体结构。
在一些可能实现的方式中，该铁电场效应管01可以为PNP型，半导体沟道部C可以采用N型半导体结构，源部S和漏部D可以采用P型半导体结构。例如，半导体沟道部C可以磷掺杂的硅半导体结构，源部S和漏部D可以采用硼掺杂的硅半导体结构。
在一些可能实现的方式中，该铁电场效应管01的半导体沟道部C可以采用N型半导体结构，源部S和漏部D中一个采用P型半导体结构，另一个采用金属结构；例如，导体沟道部C可以磷掺杂的硅半导体结构，源部S采用硼掺杂的硅半导体结构，漏部D采用铜材质的金属结构。
在一些可能实现的方式中，该铁电场效应管01的半导体沟道部C可以采用P型半导体结构，源部S和漏部D中一个采用N型半导体结构，另一个采用金属结构；例如，导体沟道部C可以硼掺杂的硅半导体结构，源部S采用磷掺杂的硅半导体结构，漏部D采用铜材质的金属结构。
在一些可能实现的方式中，该铁电场效应管01可以为N+/N/N+型结构，源部S和漏部D可以采用重掺杂的N型半导体结构(也即N+型半导体)，半导体沟道部C可以采用轻掺杂的N型半导体结构；示意的，N+型半导体的掺杂浓度可以为1e20cm -3；N型半导体结构的掺杂浓度可以小于等于1e18cm -3。例如，半导体沟道部C、源部S、漏部D可以采用磷掺杂的硅半导体结构，源部S、漏部D中的磷掺杂浓度高于半导体沟道部C中的磷掺杂浓度。在此情况下，半导体沟道部C、源部S、漏部D采用相同的掺杂原子(例如磷)，从而能够简化制作工艺，降低制作成本。
在一些可能实现的方式中，该铁电场效应管01可以为P+/P/P+型结构，源部S和漏部 D可以采用重掺杂的P型半导体结构(也即P+型半导体)，半导体沟道部C可以采用轻掺杂的P型半导体结构。例如，半导体沟道部C、源部S、漏部D可以采用硼掺杂的硅半导体结构，源部S、漏部D中的硼掺杂浓度高于半导体沟道部C中的硼掺杂浓度。在此情况下，半导体沟道部C、源部S、漏部D采用相同的掺杂原子(例如硼)，从而能够简化制作工艺，降低制作成本。
在此基础上，参考图1和图2所示，该铁电场效应管01还包括：在半导体沟道部C的侧面上依次环绕设置的第一介电层(dielectric layer)D1、第一金属层M1，以及层叠设置在第一金属层M1表面的铁电层(ferroelectric layer，简称FE layer)F和第二金属层M2；其中，铁电层F位于第一金属层M1和第二金属层M2之间，该第二金属层M2可视为该铁电场效应管01的栅部(gate)G。
示意的，在一些可能实现的方式中，在该铁电场效应管01中，第一介电层D1、第一金属层M1、铁电层F、第二金属层M2可以均采用环状结构，第一介电层D1环绕设置在半导体沟道部C的外侧面上，第一金属层M1环绕设置在第一介电层D1的外侧面上，铁电层F环绕设置在第一金属层M1的外侧面上，第二金属层M2环绕设置在铁电层F的外侧面上；从而在半导体沟道部的侧面形成直径依次增大的多个同心环状结构。
示意的，参考图2所示，在该铁电场效应管01中，第一介电层D1可以覆盖半导体沟道部C的全部侧面；当然，第一介电层D1也可以延伸覆盖至源部S、漏部D连接半导体沟道部C一端的侧面。
在此基础上，示意的，参考图2所示，第一金属层M1在半导体沟道部C上的投影可以覆盖半导体沟道部C的全部侧面；当然，第一金属层M1也可以向设置延伸至源部S和漏部D侧面的上方，且第一金属层M1的边缘不超出位于其下方的第一介电层D1的边缘。
另外，在该铁电场效应管01中，对于铁电层F、第二金属层M2的设置而言，实际中可以一般可以设置第二金属层M1的边缘不超出铁电层F的边缘，也即第二金属层M2在半导体沟道部C侧面上的投影位于铁电层F在半导体沟道部C侧面上的投影的区域内；对于铁电层F、第二金属层M2的大小、形状、位置等，可以根据需要进行设置，只要保证能够通过对铁电层F的极化来调控沟道阈值电压，实现对铁电场效应管01的开启状态(即0状态)、关闭状态(即1状态)的控制，达到存储的目的即可。
例如，如图3所示，铁电层F可以为覆盖第一金属层M1的局部表面的非环状结构(如半圆环结构、块状结构等)，第二金属层M1覆盖铁电层F表面、且与铁电层F的形状基本一致。
又例如，如图4所示，铁电层F可以为覆盖第一金属层M1的全部表面的环状结构，第二金属层M2可以为仅覆盖第一金属层M1的局部表面的非环状结构(如半圆环结构、块状结构等)。
再例如，如图5和图6(图5沿BB’位置的剖面示意图)所示，铁电层F可以仅覆盖第一金属层M1的局部表面的环状结构，第二金属层M1为覆盖在铁电层F表面、且与铁电层F的形状基本一致的环状结构。
再例如，如图7所示，在一些可能实现的方式中，铁电层F可以仅覆盖第一金属层M1的局部表面的环状结构，第二金属层M1为覆盖在铁电层F局部表面的环状结构。
此处应当理解的是，对于图4和图7中第二金属层M1覆盖铁电层F局部表面的情况 下，铁电层F中仅位于第一金属层M1和第二金属层M2之间的部分(如图7中示意的F’区域)作为有效铁电层，也即位于第一金属层M1和第二金属层M2之间的铁电层F作为有效铁电层，该部分铁电层能够在第一金属层M1和第二金属层M2形成的电场作用下被正常极化。
还需要说明的是，图6和图7中均是铁电层F以及位于铁电层F表面的第二金属层M2对应设置于半导体沟道部C的上部区域(也即靠近漏部一侧的区域)为例进行说明的，但本申请并不限制于此，在一些可能实现的方式中，铁电层F以及位于铁电层F表面的第二金属层M2也可以对应设置于半导体沟道部C的下部区域(也即靠近源部S一侧的区域)，或者设置于半导体沟道部C的中部区域；本申请对此不做限制，实际中可以根据需要进行设置。
另外，对于形成铁电层F的材料而言，在一些可能实现的方式中，铁电层F可以采用铁电材料；例如，Hf 0.5Zr 0.5O 2；在一些可能实现的方式中，铁电层F可以采用反铁电材料；例如，ZrO 2；在一些可能实现的方式中，铁电层F可以采用HZO(也即Hf (1-x)Zr xO 2)，其中，Hf和Zr的组分比可调。
本申请实施例提供的铁电存储器中采用铁电场效应管，通过在铁电层与第一介电层之间环绕半导体沟道部设置第一金属层，一方面，能够形成垂直方向上的沟道，降低铁电场效应管的尺寸；另一方面，该第一金属层作为浮栅层(floating gate)，能够俘获来自沟道(也即半导体沟道部)处的载流子，从而避免了铁电层因俘获来自沟道处的载流子而产生铁电退化问题，提高了铁电存储器的耐用性。
在此基础上，为了使铁电层F中的铁电材料能够充分极化，可以通过提高设置在铁电层F两侧的金属层(M1、M2)上的电压降(也即电势差)来实现。示意的，根据U＝Q/C(该公式中U表示电容器两极板间电势差，Q表示电容器所带的电荷量，C表示电容器的电容)可知，实际中可以通过降低铁电层F上的电容，来使得铁电层F上获得足够的电压降。
参考图8所示，C F、C I、C S分别表示铁电层F、第一介电层D1、半导体沟道部C上的等效电容，根据C＝εS/4πkd(该公式中C表示电容器的电容，ε表示电容器的介电常数，S表示电容器极板的正对面积，d表示电容器极板间的距离，k是静电力常量)可知，可以通过设计铁电层F的介电常数ε F与第一介电层D1的介电常数ε I的比值减小(即ε F/ε I减小)、铁电层F的面积S F与第一介电层D1的面积S I的比值减小(即S F/S I减小)、铁电层F的厚度d F与第一介电层D1的厚度d I的比值增加(即d F/d I增加)中的一种或多种等来降低铁电层F上的电容，以满足铁电层F进行充分极化的电压降需求。
对于上述减小铁电层F的介电常数ε F与第一介电层D1的介电常数ε I的比值(即减小ε F/ε I)而言，可以通过增加第一介电层D1的介电常数ε I来实现，在一些可能实现的方式中，第一介电层D1可以采用包含HfO 2、HZO、Al 2O 3等高介电常数的材料，例如，第一介电层D1可以采用HfO 2；又例如，第一介电层D1可以采用HZO；再例如，第一介电层D1可以采用HfO 2介电层与SiO 2介电层形成的双层结构。
对于上述增加铁电层F的厚度d F与第一介电层D1的厚度d I的比值(即增加d F/d I)而言，可以通过增加铁电层F的厚度d F来实现。例如，在一些可能实现的方式中，可以设置铁电层F的厚度d F在10nm左右，第一介电层D1的厚度d I在2nm左右。
对于上述减小铁电层F的面积S F与第一介电层D1的面积的S I的比值(即减小S F/S I)而言，可以通过减小铁电层F的面积S F来实现；应当理解到，此处的铁电层F的面积S F是有效铁电层的面积，也即夹在第一金属层M1和第二金属层M2之间的铁电层面积，具体可以参考前述的相关描述。
示意的，如图5和图6所示，在一些可能实现的方式中，铁电层F可以仅覆盖第一金属层M1的部分表面，也即铁电层F在半导体沟道部C侧面的投影仅覆盖部分半导体沟道部C的侧面；例如，铁电层F的高度可以仅占第一金属层M1的高度的1/50～1/2，铁电层F的面积大约为第一金属层M1的面积的1/50～1/2。
此处需要说明的是，通过设置铁电层F仅覆盖第一金属层M1的部分表面(也即减小铁电层F的面积)，能够在保证铁电层F上获得更高的电压降，使得铁电材料充分极化的基础上，还能够降低整个铁电场效应管01的能耗，达到节能的目的。
另外，本领域的技术人员应当理解到，铁电层F中铁电材料的极化状态决定了铁电场效应管01的非易失性存储功能，并且基于铁电材料对外加电场的响应为逆时针方向的电滞回线，当撤掉电场后，铁电材料会保持一个正/负的极化状态，即剩余极化强度，通过正/负剩余极化强度对沟道的阈值电压有调控作用，来实现到“0”/“1”态的存储功能。
以图6中示出的铁电场效应管01为例，该铁电场效应管01为P型场效应管，半导体沟道部C可以为采用N型的Si半导体结构，源部S和漏部D可以采用重掺杂的P+型Si半导体结构。以下结合图9至图13，以下对该铁电场效应管01利用铁电层F的极化方向或极化强度的改变，来调节沟道表面的电子积累或反型，以改变铁电场效应管01的阈值电压(threshold voltage)Vt进行示意说明。此处可以理解的是，对于P型的铁电场效应管01而言，阈值电压Vt低的状态为“0”态，阈值电压Vt高的状态是“1”态，以下结合P型的铁电场效应管01的三端结构(即源、漏、栅)调控阈值电压Vt，对“0”态和“1”态的读、写操作进行示意说明。
参考图9所示，在向铁电场效应管01中写“1”时，铁电场效应管01的源部S、漏部D与接地端连接，向栅部(即M2)施加正向偏压(+Vw)，沟道区域电子累积，铁电场效应管01的阈值电压Vt为高。
参考图10所示，在向铁电场效应管01中写“0”时，铁电场效应管01的源部S、漏部D与接地端连接，向栅部(即M2)施加负向偏压(-Vw)，沟道反型，铁电场效应管01的阈值电压Vt为低。
参考图11、图12所示，铁电场效应管01的源部S与接地端连接，漏部D施加电压V D，栅部(即M2)施加电压V G，在此情况下，在从铁电场效应管01的漏部D进行“1”的读取时，读取电流为I D_1(参考图13)，在从铁电场效应管01的漏部D进行“0”的读取时，读取电流为I D_0(参考图13)。
本申请实施例还提供一种存储设备，该存储设备包括如前述的任一种可能实现的方式中提供的铁电存储器；同时该存储设备中还设置有字线(word line)、源线(source line)、位线(bit line)；铁电存储器的第二金属层M2(也即栅部G)与字线连接，铁电存储器的源部S与源线连接，铁电存储器的漏部D与位线连接。
以下对存储设备中铁电存储器与字线、源线、位线之间的设置方式做进一步的说明。
如图14、图15所示，在一些可能实现的方式中，存储设备中可以设置包括交叉阵列 结构02；该交叉阵列结构02中设置有多个成矩阵排布的铁电存储器01、多条延伸方向相同的字线WL、多条延伸方向相同的源线SL、多条延伸方向相同的位线BL。其中，图14和图15仅是以交叉阵列结构02中设置有9个铁电存储器01，且9个铁电存储器01按照3行3列的矩阵排布(也即3×3)方式排列为例进行说明的，但本申请并不限制于此，实际中可以根据需要进行设置铁电存储器01的数量以及矩阵排布方式。另外，可以理解的是，行、列仅是一组相对垂直(90°)的两个方向，并不指绝对的两个方向；在某些情况，行可以视为列，而列可以视为行，也即行、列可互换。
以下通过具体的设置方式对交叉阵列结构02中，铁电存储器01的三端(即G、S、D)与字线WL、源线SL、位线BL之间的连接进行示意的说明。
设置方式一
如图14所示，在一些可能实现的方式中，位于同行的铁电存储器01的栅部G(也即第二金属层M2)与同一字线WL连接，位于不同行的铁电存储器01的栅部G连接不同的字线WL；位于同列的铁电存储器01的源部S与同一源线SL连接，位于不同列的铁电存储器01的源部S连接不同的源线SL；位于同列的铁电存储器01的漏部D与同一位线BL连接，位于不同列的铁电存储器01的漏部D连接不同的位线BL。
也即在该设置方式一中，源线SL与位线BL平行，源线SL、位线BL均与字线WL垂直。
设置方式二
如图15所示，在一些可能实现的方式中，位于同行的铁电存储器01的栅部G(也即第二金属层M2)与同一字线WL连接，位于不同行的铁电存储器01的栅部G连接不同的字线WL；位于同行的铁电存储器01的源部S与同一源线SL连接，位于不同行的铁电存储器01的源部S连接不同的源线SL；位于同列的铁电存储器01的漏部D与同一位线BL连接，位于不同列的铁电存储器01的漏部D连接不同的位线BL。
也即在该设置方式二中，源线SL与字线WL平行，源线SL、字线WL均与位线BL垂直。
当然，在一些可能实现的方式中，图15中的位线BL可以与源线SL的位置互换，也即位于同列的铁电存储器01的源部S与同一源线SL连接，位于同行的铁电存储器01的漏部S与同一位线BL连接。
上述两种设置方式的交叉阵列结构02中，通过设置铁电存储器01矩阵排布，能够进一步的将铁电存储器01的面积微缩至4F 2。
相比于静态随机存取存储器(static random access memory，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、STT-MRAM(新型磁性随机存储器)中的存储单元均无法通过金属连接层进行三维叠加(3D stacking)而言，本申请实施例提供的存储设备中，可以将多个交叉阵列结构01层叠设置(也可以说，上下堆叠设置)；在此情况下，相比于SRAM的单元面积在140F 2以上，DRAM的单元面积8F 2，STT-MRAM的单元面积60F 2而言，本申请中采用三维叠加的方式，铁电存储器01的面积可以进一步微缩至2F 2，1.33F 2，1F 2；基于此，本申请采用三维叠加的超高密度的铁电存储器01可以提供一种兼具高密度和高性能的存储设备，进而能够应用于所有需要高性能和高密度的存储器领域。
另外，采用交叉阵列结构01可以实现同字线WL或同位线BL的铁电存储器的并行读写操作，从而能够提高读写效率。
以下对交叉阵列结构02中铁电存储器01的读、写操作做进一步的说明。
对于交叉阵列结构02中铁电存储器01写操作而言，写操作的电压由字线WL和位线BL之间的电位差决定，参考图16和图17所示，当字线WL和位线BL的电压差为Vw时，铁电存储器01被写为“1”态；当字线WL和位线BL的电压差为-Vw时，铁电存储器01被写为“0”态；当字线WL和位线BL的电压差的绝对值小于或等于1/2Vw时，铁电存储器01的状态保持不变，考虑到实际应用中以正压居多，实际偏置方案可能在以下控制基础上进行电压平移。此处可以理解的是，本实施例中所涉及的Vw为写入电压(write votage)，与铁电存储器01的结构设置相关。
针对前述的设置方式一中的交叉阵列结构02的写操作而言：
在一些写操作方法中，可以采用1/2Vw控制法，如图18所示，对选中(即需要进行写操作)的铁电存储器01连接的字线WL施加1/2Vw和-1/2Vw交替变化的脉冲信号，对于想要写“1”状态的铁电存储器01(如图18中标注黑色五角星的铁电存储器01)而言，与该铁电存储器01连接的位线BL和源线SL上施加的电压为-1/2Vw，当字线WL上的信号为1/2Vw时，该铁电存储器01上的电压降为Vw，该铁电存储器01被写为“1”态。对于想要写“0”状态的铁电存储器01(如图18中标注灰色五角星的铁电存储器01)，位线BL和源线SL上施加的电压为+1/2Vw，当字线WL上的信号为-1/2Vw时，该铁电存储器01上的电压降为-Vw，该铁电存储器01被写为“0”态。对于未选中的铁电存储器01而言，位线BL和源线SL上施加的电压为0，状态不被改写，当然对于整个阵列中其他电压降为1/2Vw的铁电存储器01而言，状态同样不被改写。可以看出，该操作方式可以实现交叉阵列结构02中单个铁电存储器01的写操作，也可以对于选中字线WL连接的所有铁电存储器01进行同时写“0”和写“1”的操作。
在一些写操作方法中，为了进一步降低铁电存储器01被误写的可能性，可以采用1/3Vw控制法，如图19所示，对选中(即需要进行写操作)的铁电存储器01连接的字线WL施加1/3Vw和-1/3Vw交替变化的脉冲信号，对于想要写“1”状态的铁电存储器01(如图19中标注黑色五角星的铁电存储器01)而言，与该铁电存储器01连接的位线BL和源线SL施加的电压为-1/3Vw，当字线WL上的信号为2/3Vw时，该铁电存储器01上的电压降为Vw，该铁电存储器01被写为“1”态。对于想要写“0”状态的铁电存储器01(如图19中标注灰色五角星的铁电存储器01)而言，与该铁电存储器01连接的位线BL和源线SL施加的电压为+1/3Vw，当字线WL上的信号为-2/3Vw时，该铁电存储器01上的电压降为-Vw，该铁电存储器01被写为“0”态。在该操作方式下，未被选中的字线WL上的所有铁电存储器01的状态都将不会被改写，当然对于整个阵列中其他电压降为1/3Vw的铁电存储器01而言，状态同样不会被改写。该操作方式能够对选中字线WL连接的所有铁电存储器01进行同时写“0”和写“1”的操作。
针对前述的设置方式二中的交叉阵列结构02的写操作而言：
在一些写操作方法中，可以采用1/2Vw控制法，如图20所示，可以向所有的源线SL施加偏置电压+1/2Vw；对选中(即需要进行写操作)的铁电存储器01连接的字线WL施加1/2Vw和-1/2Vw交替变化的脉冲信号；对于想要写“1”状态的铁电存储器01(如图 20中标注黑色五角星的铁电存储器01)而言，向与其连接的位线BL施加电压-1/2Vw，当字线WL上的信号为1/2Vw时，该铁电存储器01上的电压降为Vw，该铁电存储器01被写为“1”态；对于想要写“0”状态的铁电存储器01(如图20中标注灰色五角星的铁电存储器01)而言，向与其连接的位线BL施加电压+1/2Vw，当字线WL上的信号为-1/2Vw时，该铁电存储器01上的电压降为-Vw，该铁电存储器01被写为“0”态。对于未选中的铁电存储器01而言，位线BL上施加的电压为0，状态不被改写，当然对于整个阵列中其他电压降为1/2Vw的铁电存储器01而言，状态同样不被改写。该操作方式可以实现交叉阵列结构02中单个铁电存储器01的写操作，也可以对于字线WL连接的所有铁电存储器01进行同时写“0”和写“1”的操作。
在一些写操作方法中，可以采用1/3Vw控制法，如图21所示，可以向所有的源线SL施加偏置电压+1/3Vw；对选中(即需要进行写操作)的铁电存储器01连接的字线WL施加2/3Vw和-2/3Vw交替变化的脉冲信号；对于想要写“1”状态的铁电存储器01(如图21中标注黑色五角星的铁电存储器01)而言，向与其连接的位线BL施加电压-1/3Vw，当字线WL上的信号为2/3Vw时，该铁电存储器01上的电压降为Vw，该铁电存储器01被写为“1”态；对于想要写“0”状态的铁电存储器01(如图21中标注灰色五角星的铁电存储器01)而言，向与其连接的位线BL施加电压+1/3Vw，当字线WL上的信号为-2/3Vw时，该铁电存储器01上的电压降为-Vw，该铁电存储器01被写为“0”态。在该操作方式下，被选中字线WL上的所有铁电存储器01的状态都将会被改写。在整个阵列中，未选中的铁电存储器01感受到的电压降为1/3Vw。该操作方式可以实现交叉阵列结构02中单个铁电存储器01的写操作，也可以对于字线WL连接的所有铁电存储器01进行同时写“0”和写“1”的操作。
针对前述的设置方式一中的交叉阵列结构02的读操作而言：
在一些读操作的控制方法中，如图22所示，所有的源线SL施加的电压均为0V，对选中的(也即需要进行读操作的)铁电存储器01(如图22中标注黑色五角星的铁电存储器01)连接的字线WL施加电压V G，其余的字线WL均接0V；对选中的铁电存储器01连接的位线BL施加电压V R，其余的位线BL均接0V；在此情况下，对于选中的铁电存储器01而言，当栅部G的电压为V G，漏端D的电压为V R时，该铁电存储器01打开，可以进行数据读取；对于未选中的铁电存储器01，由于缺少栅部G和漏端D的电压，处于关闭状态；对于“1”态和“0”态的数据读取可以参考图13以及前述的相关描述，此处不再赘述。该设置方式下，可以实现单独铁电存储器01的数据读取，也可以实现整条字线WL上的铁电存储器01的数据一起读取(也即将所有的位线BL全都偏置成V R)。
针对前述的设置方式二中的交叉阵列结构02的读操作而言：
在一些读操作的控制方法中，如图23所示，所有的位线BL均接偏压V R，选中的(也即需要进行读操作的)铁电存储器01(如图22中标注黑色五角星的铁电存储器01)连接的源线SL接0V电压，其余的源线SL均施加电压V R；选中的铁电存储器01连接的字线WL接电压V G，其余的均接0V电压；在此情况下，与字线WL连接的所有铁电存储器01均开启，并进行数据读取。
也就是说，在该操作方式中，能够实现与选中的字线WL连接的所有铁电存储器01的数据读取，不能实现单个铁电存储器01的数据读取。另外，对于未选中的铁电存储器 01，栅部G上收到V R的压降，但是由于读取电压V R偏小，不会对器件造成误写和误读。对于“1”态和“0”态的数据读取可以参考图13以及前述的相关描述，此处不再赘述。
另外，本申请实施例还提供一种铁电存储器01的制作方法，采用该制作方法的一次制程可以完成一个铁电存储器01的制作，也可以同时完成多个铁电存储器01的制作，以下实施例仅是以制作多个铁电存储器01中的一个为例进行示意说明的。
如图24所示，铁电存储器01的制作方法可以包括：
步骤01、参考图25中(a)所示，在基板1上依次形成第一电极2、半导体柱3、第一绝缘层4；其中，半导体柱3的两个端部、以及两个端部之间的区域的半导体类型不完全相同。
本申请对于基板1的具体设置形式不做限制，实际中可以根据铁电存储器的应用场景进行设置；例如，在一些可能实现的方式，参考图25中(a)所示，上述基板1可以包括衬底(如硅衬底，图25中未示出)、依次设置在衬底表面的金属布线层11、第二绝缘层12；第一电极2通过位于第二绝缘层13上的金属过孔V与金属布线层12连接。
示意的，前述的第一绝缘层11、第二绝缘层12可以采用氧化物、氮化物等，如氧化硅、氮化硅、氮氧化硅等。其中，设置在半导体柱3上表面的第一绝缘层11作为刻蚀阻挡层，能够在后续的制作过程中，起到对半导体柱3的上表面进行保护的作用。
示意的，前述的金属过孔V可以先在绝缘层13上形成通孔，然后在通孔中沉积铜、钨等金属形成。
对于半导体柱3中两个端部、以及两个端部之间的区域的半导体类型以及相关设置可以参考前述铁电存储器中相应的说明，此处不再赘述。例如，半导体柱3的两个端部(分别作为源部和漏部)可以采用P型半导体，两个端部之间的区域可以采用N型半导体。
示意的，参考图25中(a)所示，上述步骤01可以包括：在硅衬底上依次形成金属布线层11、绝缘层12，并在绝缘层12上形成金属过孔V；然后，在对应金属过孔V的位置采用图案化工艺依次形成第一电极2、半导体柱3、第一绝缘层4。
此处需要说明的是，本申请实施例中所涉及的“图案化工艺”可以指，包括光刻工艺，或，包括光刻工艺以及刻蚀步骤等，其中，刻蚀步骤可以是干法刻蚀(dry etch)，也可以是湿法刻蚀(wet etch)等；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺；实际中，可根据本申请中所形成的结构选择相应的图案化工艺即可。
步骤02、参考图25中(b)所示，在形成有第一电极2、半导体柱3、第一绝缘层4的基板1上依次形成第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9。
示意的，参考图25中(b)所示，上述步骤02可以包括：采用沉积工艺、溅射工艺或者电镀工艺等工艺，依次制备一定厚度的第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9。此处需要说明的是，在制作栅极金属层9时，应保证栅极金属层9的厚度覆盖整个半导体柱3的高度。
此处需要说明的是，对于铁电层7的形成而言，一般需要在沉积铁电材料后进行高温退火，以使得铁电材料晶化；示意的，上述步骤02可以在依次形成各膜层(5、6、7、8)之后，采用退火工艺形成晶化的铁电层7。
步骤03、参考图25中(c)所示，对形成有第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9的基板1的表面进行平坦化处理，露出半导体柱3的上表面。
示意的，参考图25中(c)所示，上述步骤03可以包括：采用化学机械平坦化(chemical mechanical planarization，CMP)，对形成有第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9的基板1的表面进行平坦化处理，去除位于半导体柱3上方的第一绝缘层4、第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9，以露出半导体柱3的上表面。当然，在一些可能实现的方式中，可能会保留部分厚度的第一绝缘层4，在后续制作过程中再进行去除。
步骤04、参考图25中(d)所示，对平坦化后的基板1中的第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9进行刻蚀，保留第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9位于半导体柱3侧面的部分。
示意的，参考图25中(d)所示，采用图案化工艺，对平坦化后的基板1中的第一介电层5、第一金属层6、铁电层7、第二金属层8和栅极金属层9进行刻蚀，保留位于半导体柱3侧面的部分(当然，也可以适当保留从侧面延伸至基板1表面的部分)，从而形成单个的铁电存储器的核心部分的制作，对应可以参考前述的图1中示出的铁电存储器01。
在一些可能实现的方式中，在前述步骤03和步骤04之间，该铁电存储器的制作方法还可以包括：如图26所示，对平坦化后的基板1中的第二金属层8、栅极金属层9进行刻蚀减薄，以使得位于半导体柱3侧面的第二金属层8和栅极金属层9的上表面低于半导体柱3的上表面。
作为另一种可替换的实现方式，在前述步骤03和步骤04之间，该铁电存储器的制作方法还可以包括：如图27所示，对平坦化后的基板1中的栅极金属层9、第二金属层8、铁电层7进行刻蚀减薄，以使得位于半导体柱3侧面的栅极金属层9、第二金属层8、铁电层7的上表面低于半导体柱3的上表面。
当然，上述关于栅极金属层9和第二金属层8，或者栅极金属层9、第二金属层8、铁电层7的刻蚀减薄过程可以是单次刻蚀工艺，也可以是多次刻蚀工艺，本申请对此不做限制，实际中可以根据需要选择合适工艺即可。
此处还需要说明的是，对于位于半导体柱3侧面的铁电层7而言，只有夹在第一金属层6、第二金属层8之间的部分作为有效铁电层，在第一金属层6、第二金属层8形成的电场作用下被正常极化。通过减小有效铁电层7的面积，能够在铁电层F上获得更高的电压降，使得铁电材料充分极化；具体可以参考前述铁电场效应管01实施例中对应的描述。
另外，在一些可能实现的方式中，上述铁电存储器的制作方法在前述步骤04之后还可以包括：
步骤05、参考图28所示，在基板1的表面形成绝缘层13，并在绝缘层13对应半导体柱3以及栅极金属层9的位置开孔，露出半导体柱3以及栅极金属层9的上表面；并在露出的半导体柱3的上表面依次形成第二电极31和电极连接部32，在露出的栅极金属层9的表面形成栅极连接部91。
可以理解的是，上述步骤05中形成的第二电极31和前述步骤01中形成的第一电极2，一个为源极，另一个为漏极；例如，第一电极2可以为源极，第二电极31为漏极。
示意的，参考图28所示，上述步骤05可以包括，在步骤04中形成的基板1的表面形成绝缘层13，并通过化学机械平坦化工艺，对绝缘层13的表面进行平坦化处理；然后，对绝缘层13进行刻蚀(例如光刻工艺)，并在绝缘层13对应半导体柱3以及栅极金属层9的位置开孔，以露出半导体柱3以及栅极金属层9的上表面；接下来，采用镍(Ni)、钛(Ti)等金属，通过图案化工艺在露出的半导体柱3的表面形成第二电极31；然后，采用铜(Cu)、钨(W)等金属，通过图案化工艺在第二电极31的表面形成电极连接部32，在露出栅极金属层9的表面形成栅极连接部91。
关于上述铁电存储器01的制作方法实施例中其他相关的内容，可以对应参考前述芯片结构实施例中对应的部分，此处不再赘述；关于前述铁电存储器01实施例中相关的结构，可以对应参考上述铁电存储器01的制作方法实施例对应制作，也可以结合相关技术进行适当的调整进行制作，本申请对此不做限制。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种铁电存储器，由至少一个存储单元构成，其特征在于，所述存储单元包括：
    柱状的半导体沟道部；
    源部和漏部，分别设置于所述半导体沟道部的两端；
    在所述半导体沟道部的侧面上依次环绕设置的第一介电层、第一金属层；层叠设置在所述第一金属层表面的铁电层和第二金属层，所述铁电层位于所述第一金属层和所述第二金属层之间。
  2. 根据权利要求1所述的铁电存储器，其特征在于，所述第一介电层覆盖所述半导体沟道部的全部侧面。
  3. 根据权利要求1或2所述的铁电存储器，其特征在于，所述第一金属层在所述半导体沟道部上的投影覆盖所述半导体沟道部的全部侧面。
  4. 根据权利要求1-3任一项所述的铁电存储器，其特征在于，所述铁电层仅覆盖所述第一金属层的部分表面。
  5. 根据权利要求1-4任一项所述的铁电存储器，其特征在于，所述第二金属层在所述半导体沟道部侧面上的投影位于所述铁电层在所述半导体沟道部侧面上的投影的区域内。
  6. 根据权利要求1-5任一项所述的铁电存储器，其特征在于，所述铁电层包括铁电材料、反铁电材料中的至少一种。
  7. 根据权利要求1-6任一项所述的铁电存储器，其特征在于，所述第一介电层、所述第一金属层、所述铁电层和所述第二金属层依次环绕设置在所述半导体沟道部的表面上。
  8. 根据权利要求1-7任一项所述的铁电存储器，其特征在于，
    所述源部和所述漏部采用重掺杂的P型半导体结构，所述半导体沟道部采用轻掺杂的P型半导体结构；
    或者，所述源部和所述漏部采用重掺杂的N型半导体结构，所述半导体沟道部采用轻掺杂的N型半导体结构。
  9. 一种存储设备，其特征在于，包括：字线、源线、位线以及铁电存储器；
    所述铁电存储器包括：柱状的半导体沟道部、源部和漏部，所述源部和漏部分别设于所述半导体沟道部的两端；所述铁电存储器还包括：在所述半导体沟道部的侧面上依次环绕设置的第一介电层、第一金属层，以及层叠设置在所述第一金属层表面的铁电层和第二金属层；所述铁电层位于所述第一金属层和所述第二金属层之间；
    所述铁电存储器的第二金属层与所述字线连接，所述铁电存储器的源部与所述源线连接，所述铁电存储器的漏部与所述位线连接。
  10. 根据权利要求9所述的存储设备，其特征在于，
    所述存储设备包括多条所述源线、字线、位线，以及呈阵列排布的多个所述铁电存储器；
    所述多个所述铁电存储器中的每一个与一条源线、一条字线和一条位线相连。
  11. 根据权利要求9或10所述的存储设备，其特征在于，所述铁电层仅覆盖所述第 一金属层的部分表面。
  12. 跟据权利要求9-11任一项所述的存储设备，其特征在于，所述第二金属层在所述半导体沟道部侧面上的投影位于所述铁电层在所述半导体沟道部侧面上的投影的区域内。
  13. 一种铁电存储器的制作方法，其特征在于，包括：
    在基板上依次形成第一电极、半导体柱、第一绝缘层；在形成有所述第一电极、所述半导体柱、所述第一绝缘层的基板上，依次形成第一介电层、第一金属层、铁电层、第二金属层和栅极金属层；
    对形成有所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层的基板的表面进行平坦化处理，露出所述半导体柱的上表面；
    对平坦化后的基板中的所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层进行刻蚀，保留所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层位于所述半导体柱侧面的部分。
  14. 根据权利要求13所述铁电存储器的制作方法，其特征在于，
    在所述对形成有所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层的基板的表面进行平坦化处理，露出所述半导体柱的上表面之后；
    在所述对平坦化后的基板中的所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层进行刻蚀，保留所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层位于所述半导体柱侧面的部分之前；
    所述制作方法还包括：
    对平坦化后的基板中的所述第二金属层、所述栅极金属层进行刻蚀减薄，以使得位于所述半导体柱侧面的所述第二金属层和所述栅极金属层的上表面低于所述半导体柱的上表面；
    或者，对平坦化后的基板中的所述第二金属层、所述栅极金属层、所述铁电层进行刻蚀减薄，以使得位于所述半导体柱侧面的所述第二金属层、所述栅极金属层、所述铁电层的上表面低于所述半导体柱的上表面。
  15. 根据权利要求13或14所述的所述铁电存储器的制作方法，其特征在于，在所述对平坦化后的基板中的所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层进行刻蚀，保留所述第一介电层、所述第一金属层、所述铁电层、所述第二金属层和所述栅极金属层位于所述半导体柱侧面的部分之后，
    所述制作方法还包括：
    在基板的表面形成第二绝缘层，并在所述第二绝缘层对应所述半导体柱以及所述栅极金属层的位置开孔，露出所述半导体柱以及所述栅极金属层的上表面；
    在露出的所述半导体柱的上表面依次形成第二电极和电极连接部，在露出的所述栅极金属层的表面形成栅极连接部；其中，所述第二电极和所述第一电极一个为源极，另一个为漏极。
PCT/CN2020/119530 2020-09-30 2020-09-30 铁电存储器及其制作方法、存储设备 WO2022067720A1 (zh)

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