Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/3457—Solder materials or compositions; Methods of application thereof
  • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
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  • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
  • H01L24/742—Apparatus for manufacturing bump connectors
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  • H01L2224/11—Manufacturing methods
  • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
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  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • H01L2224/8119—Arrangement of the bump connectors prior to mounting
  • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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  • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
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  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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Definitions

• the present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board that can be suitably used for a package substrate for mounting an IC chip.
• solder bumps are used for electrical connection between a knock substrate and an IC chip.
• the solder bump is formed by the following process.
• the IC chip is placed on the solder bumps, and the solder bumps and the IC chip nodes (terminals) are connected by reflow. Implement it.
• a printing technique using a ball alignment mask and a squeegee as described in Patent Document 1 is used.
• Patent Document 1 JP 2001-267773 A
• solder balls with a small diameter are smaller than the sand grains, and in the method of using the ball alignment mask and the squeegee together in Patent Document 1, the solder balls are deformed by the squeegee and the solder bump height varies. Appears and the quality deteriorates. That is, when the solder ball has a small diameter, the weight ratio to the surface area becomes small, and the solder ball adsorption phenomenon due to intermolecular force occurs. In the prior art, solder balls that tend to agglomerate are sent in contact with a squeegee, so that the solder balls are damaged and some of them are chipped.
• the connection pads on which the solder bumps are mounted are required to have a small diameter.
• the solder bump connected to the connection pad must be high. In other words, since the thermal expansion coefficient differs between the IC chip and the printed wiring board made of resin, if the solder bump height is high, the thermal expansion coefficient between the IC chip and the printed wiring board at the solder bump is high. This is because the stress generated due to the difference is easily absorbed.
• the opening 71 is provided in the solder resist layer 70 so that the connection pad 158P has a small diameter, and a solder bump having a height is formed.
• a relatively large solder ball 77 was mounted on a small-diameter connection pad 158P, and reflow was performed to form solder bumps as shown in FIG. 15 (C).
• the take of the connection between the connection pads 158P! / Ru of solder bump 78U other, to take from the connection pads 158P of floating! Te ⁇ connection! /, Stomach solder bump 78 F is known to occur .
• One of the objects of the present invention is to reliably form a bump with a high height on a small-diameter connection pad (a conductive circuit exposed from the solder resist layer) provided in the opening of the solder resist.
• a printed wiring board manufacturing method is provided.
• the method for producing a printed wiring board having bumps according to claim 1 has at least the following steps (a) to (c) as technical features:
• solder resist layer having an opening with a depth of 3 to 18 m to the surface of the connection pad exposing the upper end force
• a relatively large low-melting-point metal sphere is mounted in the small-diameter opening of the solder resist layer. Reflow is performed to form a bump with a high height from the low melting point metal sphere at the small-diameter opening in the solder resist layer. At this time, by adjusting the thickness of the solder resist layer, the opening upper edge force is 3-18 ⁇ m deep to the connection pad surface, and the distance between the low melting point metal sphere mounted in the opening and the connection pad is increased. Because of the close proximity, solder bumps and connection pads can be securely connected when the low melting point metal sphere is reflowed.
• the thickness of the solder resist layer is adjusted so that the low melting point metal sphere is brought into contact with the connection pad in a state where it is mounted in the opening. During reflow, the low melting point metal ball mounted in the opening and the connection pad are in contact with each other, so that the solder bump and the connection pad can be reliably connected.
• a low melting point is obtained by using a mask having an opening corresponding to the opening of the solder resist layer, positioning a cylindrical member above the mask, and sucking air from the opening of the cylindrical member.
• the metal balls are assembled and the cylindrical member or the printed wiring board and the mask are moved relative to each other in the horizontal direction, thereby moving the low melting point metal balls assembled just below the cylindrical member and the solder resist layer of the solder resist layer through the opening of the mask. Drop into the opening. For this reason, fine low-melting-point metal spheres can be reliably mounted in all openings of the solder resist layer.
• the low melting point metal sphere is moved in a non-contact manner, unlike the case of using a squeegee, the low melting point metal sphere can be mounted in the opening without scratching, and the bump height can be made uniform. Furthermore, like a build-up multilayer wiring board, the surface has many undulations, and even a printed wiring board can appropriately place a low melting point metal sphere in the opening.
• solder ball mounting apparatus in which a small solder ball 77 (with a diameter of less than 200 ⁇ m) is mounted on a connection pad of a multilayer printed wiring board will be described with reference to FIG.
• FIG. 12A is a configuration diagram showing the configuration of the solder ball mounting device according to one embodiment of the present invention.
• FIG. 12B is an arrow view of the solder ball mounting device of FIG.
• the solder ball mounting apparatus 100 positions and holds the multilayer printed wiring board 10.
• FIG. 10 shows a cross-sectional view of the multilayer printed wiring board 10
• FIG. 11 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG.
• a conductor circuit 34 is formed on the surface of the core substrate 30.
• the front surface and the back surface of the core substrate 30 are connected through a through hole 36.
• an interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed, and an interlayer resin insulation layer 150 in which via holes 160 and conductor circuits 158 are formed are disposed.
• a solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158.
• the height HI (height protruding from the solder resist layer surface) of the solder bump 78U is set to about 30 ⁇ m.
• Solder bumps 78D are formed on the lower surface side of the multilayer printed wiring board through the openings 71 of the solder resist layer 70.
• the opening of the solder resist has a force via hole 160 formed so as to expose a part of the conductor circuit 158.
• the opening may be formed so as to include a part of the via hole 160 and the conductor circuit 158.
• solder bumps 78 U on the upper surface side of the multilayer printed wiring board 10 are connected to the electrode pads 92 of the IC chip 90.
• solder bump 78D on the lower surface side is connected to the land 96 of the daughter board 94!
• filler 37 containing copper particles with an average particle size of 10 ⁇ m is screen-printed on through-hole 36 Fill, dry, and cure (Fig. 2 (A)). This is applied to the substrate on which a mask having an opening in the through hole portion is placed by a printing method so that the through hole is filled, and after filling, dried and cured.
• the filler 37 protruding from the through hole 36 is removed by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku), and further, scratches due to this belt sander polishing are removed. Puff polishing is performed to flatten the surface of the substrate 30 (see FIG. 2 (B)). In this way, the substrate 30 is obtained in which the side wall conductor layer 36b of the through hole 36 and the resin filler 37 are firmly adhered to each other through the rough layer 36 ⁇ .
• a palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate 30 flattened in (3), By applying electroless copper plating, a 0.6 m thick electroless copper plating film 23 is formed (see FIG. 2C).
• electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 24 having a thickness of 15 m, thickening of the portion that becomes the conductor circuit 34, and filling of the through hole 36 A portion to be a lidded layer (through-hole land) covering the filled filler 37 is formed (Fig. 2 (D)).
• electrolytic plating solution [Electrolytic plating solution]
• the portions of the plating films 23, 24 and the copper foil 32 where the etching resist 25 is not formed are dissolved and removed with an etching solution mainly composed of salty cupric copper, and further, The etching resist 25 is stripped and removed with 5% KOH to form an independent conductor circuit 34 and a lid plating layer 36a covering the filler 37 (see FIG. 3A).
• the resin film for the interlayer resin insulation layer is subjected to main pressure bonding on the substrate under the conditions of a vacuum of 67 Pa, a pressure of 0.4 Mpa, a temperature of 85 ° C., a pressure bonding time of 60 seconds, and then at 170 ° C. for 40 minutes. Heat cured.
• the substrate on which the via hole opening 51 is formed is immersed in an 80 ° C. solution containing 60 gZl of permanganic acid for 10 minutes to remove particles existing on the surface of the interlayer resin insulation layer 50.
• a rough surface 50 ⁇ was formed on the surface of the interlayer resin insulation layer 50 including the inner wall of the via hole opening 51 (FIG. 4A).
• catalyst nuclei are attached to the surface of the interlayer resin insulation layer and the inner wall surface of the via hole opening.
• the above substrate is made of palladium chloride (PbCl) and salt stannic acid (SnCl
• the catalyst was applied by dipping in a catalyst solution containing 2) and depositing palladium metal.
• the substrate provided with the catalyst is immersed in an electroless copper plating aqueous solution (Sulcup PEA) manufactured by Uemura Kogyo Co., Ltd., so that the thickness of the entire rough surface is 0.3 to 3.0.
• An electroless copper plating film of m was formed, and a substrate having an electroless copper plating film 52 formed on the surface of the interlayer resin insulation layer 50 including the inner wall of the via hole opening 51 was obtained (Fig. 4 (B)). ).
• a commercially available photosensitive dry film was attached to the substrate on which the electroless copper plating film 52 was formed, a mask was placed, and exposure was performed with lOmjZcm 2 , and 0.8% sodium carbonate.
• a developing resist 54 having a thickness of 25 ⁇ m was provided by developing with an aqueous solution. Next, place the board at 50 ° C. After washing with water at 25 ° C and further with sulfuric acid, electroplating is performed under the following conditions, and the plating resist 54 non-formed part is 15 m thick.
• An electrolytic copper plating film 56 was formed (FIG. 4 (C)).
• the thickness of the lower conductor circuit 58 was 15 m (Fig. 5 (A)). However, the thickness of the lower conductor circuit may be between 5 and 25 / ⁇ ⁇ .
• the upper end force of the opening 71 is also deep enough to reach the surface of the connection pad 158P (the surface of the gold plating layer 74).
• D2 was set to 10 m.
• the alignment mark 34M of the multilayer printed wiring board 10 is recognized by the alignment force memer 146, and the position of the multilayer printed wiring board 10 with respect to the ball alignment mask 16 is determined by the ⁇ suction table 114. to correct. That is, the positions are adjusted so that the openings 16a of the ball alignment mask 16 correspond to the upper surface openings 71 of the multilayer printed wiring board 10, respectively.
• a solder ball 77 (diameter 75 m, Sn 63Pb37 (manufactured by Hitachi Metals)) is quantitatively supplied from the solder ball supply device 122 to the mounting cylinder 124 side. It may be supplied in advance in the mounting cylinder.
• the force Sn using SnZPb solder for the solder balls Pb-free solder that can be selected from group forces such as Ag, Cu, In, Bi, and Zn may also be used.
• the mounting cylinder 124 is positioned above the ball alignment mask 16 while maintaining a predetermined clearance with the ball alignment mask (for example, 0.5 to 4 times the ball diameter).
• a predetermined clearance with the ball alignment mask for example, 0.5 to 4 times the ball diameter.
• the solder balls 77 assembled on the ball alignment mask 16 are moved along with the movement of the mounting cylinder 124, and the upper surface opening 71 of the multilayer printed wiring board 10 is passed through the opening 16a of the ball alignment mask 16. Drop to and mount. Thereby, the solder balls 77 are sequentially aligned on all the connection pads on the multilayer printed wiring board 10 side.
• the mounting cylinder 124 is moved, but instead, with the mounting cylinder 124 fixed, the multilayer printed wiring board 10 and the ball alignment mask 16 are moved to gather directly below the mounting cylinder 124. It is also possible to mount the solder balls 77 thus formed on the openings 71 of the multilayer printed wiring board 10 through the openings 16 a of the ball alignment mask 16.
• the surplus solder balls 77 are guided to the position without the opening 16 a on the ball alignment mask 16 by the mounting cylinder 124, and then sucked and removed by the ball removing cylinder 161.
• solder ball 77 on the upper surface is melted by reflowing at 230 ° C., and a solder bump 78U having a height of about 30 m (Hl) is formed from the solder ball 77 mounted in the opening 71 on the upper surface. Formed ( Figure 9).
• the thickness of the solder resist layer 70 the distance between the solder ball 77 mounted in the opening 71 and the connection pad 158P is made closer, so when the solder ball 77 is reflowed, the solder bump 78U And connection pad 158P can be easily connected.
• solder bump 78U and the connection pad 15 The connection with 8P can be taken reliably.
• a solder bump 78D was formed on the lower surface.
• connection pad of the printed wiring board and the electrode 92 of the IC chip 90 are connected via the solder bump 78U. It is done. Thereafter, it is attached to the daughter board 94 via the solder bump 78D (FIG. 11).
• the mounting cylinder 124 is positioned above the ball alignment mask 16, and the solder balls 77 are combined by sucking air from the mounting cylinder 124, thereby mounting the mounting cylinder 124. Or, by moving the printed wiring board and the ball alignment mask 16 relative to each other in the horizontal direction, the solder balls 77 assembled just below the mounting cylinder 124 are moved onto the ball alignment mask 16 and the ball alignment mask. It is dropped into the opening 71 of the multilayer printed wiring board 10 through the 16 openings 16a. At this time, since the upper end force of the opening 71 is also made shallower to the connection pad 158P, it is difficult for the solder ball 77 to be caught on the upper end surface of the opening 71.
• solder ball 77 can be mounted in all small diameter openings 71 of the plate 10. Also, since the solder ball 77 is moved in a non-contact manner, unlike the case of using a squeegee, the solder ball can be mounted on the small diameter opening 71 without scratching, and the height of the solder bump 78 can be made uniform. . Furthermore, since the solder balls are guided by a suction force, the solder balls can be prevented from agglomerating and adhering.
• the thickness D4 of the solder resist layer 70 so that the depth D2 to the connection pad surface is equal to or less than the distance X in the opening upper end force! /.
• the distance X is preferably small. This is because in order to make the solder ball 77 into a solder bump by reflow, the air in the gap V must be pushed out of the solder bump. If the air present in the gap V cannot be pushed out of the solder bump, the connection pad and the solder bump This is because the adhesiveness is inferior between the solder bumps and voids are generated in the solder bumps. In some cases, solder bumps cannot be formed on the connection pad. Such a defect is more likely to occur as the gap V is larger.
• the depth D2 to the surface of the connection pad that exposes the opening upper end force is 18 m or less. This is thought to be due to the fact that if the depth X is large, the solder ball tends to be caught at the upper end surface of the solder resist opening, making it impossible to mount it in the opening. On the other hand, if D2 is less than 3 m, solder ball mounting will not be a problem, but the ability as a dam will decrease, and solder will flow out when the solder ball is reflowed, and will contact the solder on the adjacent connection pads. And may cause a short circuit.
• the depth D2 is preferably in the range of 3-18 m.
• 20 / ⁇ ⁇ voids were observed in the bumps.
• solder ball mounting in which solder ball mounting was performed with the apparatus shown in FIG. 12 was disclosed in Japanese Patent Laid-Open Nos. 3-265150, 2000-77837, and 8-20682. Pick up the solder bumps and mount them on the connection pads.
• FIG. 1 is a process diagram showing a method for producing a multilayer printed wiring board according to a first embodiment of the present invention.
• FIG. 2 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 3 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 4 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 5 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 6 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 7 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 8 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 9 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
• FIG. 10 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment.
• FIG. 11 is a cross-sectional view showing a state where an IC chip is mounted on the multilayer printed wiring board shown in FIG.
• FIG. 12 (A) is a configuration diagram showing the configuration of the solder ball mounting device according to the embodiment of the present invention
• FIG. 12 (B) is an arrow indicating the solder ball mounting device of FIG. 12 (A). It is an arrow view also seeing B side force.
• FIG. 13 is an explanatory view showing a state where a solder ball is placed in the opening.
• FIG. 14 is a chart showing test results of solder ball mounting yield.
• FIG. 15 shows solder resist layer formation in the prior art, and Fig. 15 (B) shows solder ball mounting
• FIG. 15C is an explanatory view showing the solder bump after reflow.

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• Engineering & Computer Science (AREA)
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• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)

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• 2007
  • 2007-01-23 TW TW096102452A patent/TW200746964A/zh not_active IP Right Cessation
  • 2007-01-26 EP EP07707506A patent/EP1978795A4/en not_active Withdrawn
  • 2007-01-26 JP JP2007556016A patent/JP4666399B2/ja active Active
  • 2007-01-26 WO PCT/JP2007/051274 patent/WO2007086509A1/ja not_active Ceased
  • 2007-01-26 CN CN2007800007403A patent/CN101331812B/zh not_active Expired - Fee Related
  • 2007-01-26 CN CN2010106229552A patent/CN102098881A/zh active Pending
  • 2007-01-26 KR KR1020087002447A patent/KR100973950B1/ko active Active
• 2008
  • 2008-05-12 US US12/093,436 patent/US8083123B2/en active Active

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