WO2006108359A1 - METHOD OF FABRICATING InGaAlN FILM AND LIGHT-EMITTING DEVICE ON A SILICON SUBSTRATE - Google Patents

METHOD OF FABRICATING InGaAlN FILM AND LIGHT-EMITTING DEVICE ON A SILICON SUBSTRATE Download PDF

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Publication number
WO2006108359A1
WO2006108359A1 PCT/CN2006/000681 CN2006000681W WO2006108359A1 WO 2006108359 A1 WO2006108359 A1 WO 2006108359A1 CN 2006000681 W CN2006000681 W CN 2006000681W WO 2006108359 A1 WO2006108359 A1 WO 2006108359A1
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Prior art keywords
aluminum nitride
indium gallium
gallium aluminum
silicon substrate
preparing
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PCT/CN2006/000681
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English (en)
French (fr)
Inventor
Fengyi Jiang
Wenqing Fang
Li Wang
Chunlan Mo
Hechu Liu
Maoxing Zhou
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Lattice Power (Jiangxi) Corporation
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Priority to US11/910,735 priority Critical patent/US7888779B2/en
Priority to EP06722330.5A priority patent/EP1870945A4/en
Priority to JP2008505717A priority patent/JP5105621B2/ja
Publication of WO2006108359A1 publication Critical patent/WO2006108359A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Definitions

  • the present invention relates to a semiconductor material, and more particularly to a method of preparing an indium gallium aluminum nitride film and a light emitting device on a silicon substrate.
  • Indium gallium aluminum nitride It is one of the preferred material systems for preparing short-wavelength light-emitting devices.
  • many novel light-emitting devices such as blue, green, white light-emitting diodes, and violet semiconductor lasers, have been fabricated using indium gallium aluminum nitride materials.
  • indium gallium aluminum nitride materials are also good materials for the preparation of many high performance electronic devices.
  • indium gallium aluminum nitride materials on sapphire substrates and silicon carbide substrates are known.
  • a method of preparing a gallium nitride material on a sapphire substrate is disclosed in Japanese Patent No. JP2737053.
  • a method of preparing a gallium nitride material on a silicon carbide substrate is disclosed in US Pat. No. 5,686,738. According to these disclosed techniques, high quality indium gallium aluminum nitride materials have been prepared.
  • silicon carbide substrates are very expensive, the use of indium gallium aluminum nitride materials for growth will be costly.
  • the sapphire substrate is also expensive, and it is an insulator, which is difficult to process and cannot be fabricated into a chip structure having upper and lower electrodes, which results in a complicated manufacturing process and an increased cost.
  • Silicon is one of the most mature semiconductor materials. It is not only cheap, but also easy to control its conductivity type and resistivity. Its processing technology is also very mature. If it is used to grow indium gallium and aluminum, it will save a lot of cost. However, the lattice mismatch and thermal mismatch of silicon and indium gallium aluminum nitride materials are very large, and indium gallium aluminum nitride grown on silicon is prone to cracking, so that high-performance light-emitting or electronic devices cannot be prepared.
  • the literature (Phys. stat. sol.
  • the area of the light-emitting chip is typically required to be greater than 100 X 100 microns 2 because b has not been able to produce efficient light-emitting devices in accordance with the methods disclosed in these documents.
  • One of the objects of the present invention is to provide a method for preparing a crack-free indium gallium aluminum nitride film on a silicon substrate. Law.
  • Another object of the present invention is to provide a method of preparing an indium gallium aluminum nitride light-emitting device.
  • A forming a pattern structure having a groove and a mesa on the surface of the silicon substrate
  • the depth of the trench is greater than or equal to 6 microns, and the indium gallium aluminum nitride films grown on the mesas on both sides of the trench are not connected to each other.
  • the depth of the trench is 6 to 300 ⁇ m, preferably 10 to 30 ⁇ m; and the width of the trench is larger than
  • the width of the film which is grown horizontally on both sides of the mesa preferably the width of the groove is 6 to 50 ⁇ m, and the width of the groove may be selected to be more than twice the film thickness.
  • the grooves on the substrate are in the shape of a line, staggered or connected to each other, or radiate radially, or do not intersect each other.
  • the ratio of the circumference of the independent mesa that is not connected to each other and the area thereof is greater than 1.0 mm / mm 2 , less than 40 mm / mm 2 , preferably greater than 4 mm / mm 2 , less than 20 mm / mm 2 .
  • the graphic structure is a circle, a triangle, a square, a square, a polygon or other irregular figure.
  • the mesa area is greater than 100 X 100 ⁇ m 2 and less than 3000 X 3000 ⁇ m 2 , preferably greater than 200 X 200 ⁇ m 2 and less than 1000 X 1000 ⁇ m 2 . ;
  • the method of the light-emitting device includes the method of preparing an indium gallium aluminum nitride thin film on a silicon substrate as described above. It also includes forming P-type and N-type electrodes on the surface of the indium gallium aluminum nitride film or on the back side of the substrate, and then cutting the substrate along the grooves to form a separate light-emitting element for each mesa.
  • a plurality of light-emitting devices are formed on the same silicon substrate simultaneously but independently of each other.
  • A forming a trench having a depth of 6 ⁇ m or more on the silicon substrate, and dividing the surface of the substrate into a plurality of mesas having an area greater than 100 ⁇ 100 ⁇ m 2 and less than 3000 ⁇ 3000 ⁇ 2 ;
  • B depositing an indium gallium aluminum nitride multilayer film on the surface of the substrate;
  • C forming P-type and N-type electrodes on the surface of the indium gallium aluminum nitride film or the back surface of the substrate;
  • the indium gallium aluminum nitride material is grown on a large-area silicon substrate to a certain thickness, due to the accumulation of stress. This will cause the film to crack.
  • the present invention therefore reduces the stress experienced by the mitigating film by creating a groove of a certain density and sufficient depth and width on the substrate. Since the surface of the substrate is divided into a plurality of regions, the indium gallium aluminum nitride material grown in each region is spatially separated, thereby increasing the free surface and reducing stress.
  • the groove must have a sufficient depth to change the stress distribution between the indium gallium aluminum nitride epitaxial film and the substrate.
  • the silicon mesa can withstand greater stress, thereby reducing the stress on the indium gallium aluminum nitride film grown on the mesa and preventing the film from cracking. Since the thickness of the film required to prepare the indium gallium aluminum nitride photodiode is generally greater than 3 microns, the method of the present invention requires that the depth of the trench be greater than 6 microns.
  • the grooves on the substrate may be combined in a line shape, but it is premised that the stress can be reduced and finally the luminescent material can be applied. They may be staggered or connected to each other, forming a circle, a triangle, a square, a square, a polygon or other irregular pattern, etc., or may be radially divergent, or even any shape that does not intersect each other, and it is generally preferred to have a crisscross grooved lining.
  • the bottom is divided into a number of lattices of a certain shape.
  • the shape of the lattice can be any common regular shape such as a square, a rectangle, or a triangle. For ease of device preparation, the preferred shape is square.
  • the method of forming the grooves may be any mature groove method, such as dry etching, wet etching, mechanical dicing, and the like. Since the film on the edge of the mesa is extended in the horizontal direction and extends outward, in order to prevent the adjacent films on the mesa from abutting each other, the width of the groove must be greater than the thickness of the film grown in the horizontal direction. Preferred conditions It is more than twice the film thickness. 0 ⁇ The thickness of the groove is required to achieve a uniform circumference / area ratio of any independent mesa is greater than 1.0 mm, in accordance with the area of the substrate, the number of grooves or the length of the substrate is different. /mm 2 .
  • the density of the trenches should not be too large, and the mesa area described in the method of the present invention is greater than 100 X 100 ⁇ m 2 .
  • the indium gallium aluminum nitride material grown on the silicon substrate is thin and brittle, if the blade is diced from the front surface of the indium gallium aluminum nitride material, the film may be broken and cracked when the chip is cut; It is opaque in the visible range, it is difficult to take the back scribe like a sapphire substrate and then split it. Law.
  • the grid corresponding to the chip size is pre-etched on the surface of the substrate before the indium gallium aluminum nitride material is grown, and then the long indium gallium aluminum nitride film is regenerated.
  • the dicing blade is cut along the groove before the growth, and the width of the groove is larger than the thickness of the blade, so that the blade does not touch the film material grown on the surface, and the film does not crack.
  • the electrode structure of the chip can be either the same side electrode or the upper and lower electrodes.
  • the grown indium gallium aluminum nitride can also be transferred to a substrate of another silicon substrate or other material to form a light-emitting device.
  • Figure 1 is a partial schematic view of a surface of a substrate engraved with a groove
  • Figure 2 is a cross-sectional view of the A-A direction of Figure 1;
  • FIG. 3 is a schematic cross-sectional view showing an indium gallium aluminum nitride film grown on a silicon substrate
  • FIG. 4 is a schematic view showing the shape of a surface of a substrate according to another embodiment of the present invention.
  • Figure 5 is a schematic view showing the shape of the surface of the substrate according to still another embodiment of the present invention.
  • Fig. 6 is a schematic view showing the appearance of an ohmic electrode prepared by using the epitaxial wafers shown in Fig. 3 and dicing;
  • Fig. 7 is a cross-sectional view taken along line B-B of Fig. 6.
  • 1 is a mesa
  • 2 and 2' are trenches
  • 3 is an indium gallium aluminum nitride film
  • 4 is a p-type electrode
  • 5 is a dicing groove
  • 6 is an n-type electrode.
  • the devices involved in the present invention are currently common devices in the industry and will not be described here.
  • a silicon (111) substrate is patterned on the surface by a conventional photolithographic mask and then plasma etched as shown in FIG.
  • the square area 1 in the figure is a mesa area that is not etched.
  • Area 2 is the grooved area that is engraved.
  • Figure 2 shows this table and groove structure more clearly in cross section.
  • the center distance of two adjacent square lattices is 100 micrometers
  • the width of the trenches is 6 micrometers
  • the depth of the trenches is 6 micrometers.
  • the substrate section has a structure as shown in FIG. Comparing Fig. 2 and Fig. 3, it can be seen that there is deposition of indium gallium aluminum nitride material in the mesa and the trench.
  • the film grown in the groove and the film grown on the mesa are not connected to each other.
  • the film grows outward in the horizontal direction around the table and protrudes from the edge of the table. Since the groove width is sufficiently wide, the film grown on the adjacent mesa does not abut due to the outward extension. Thus, since the films grown on the respective surfaces are independent of each other and free, the stress can be released and cracks do not occur on the mesa.
  • a p-type electrode 4 is formed on each of the mesas, and an n-type electrode 6 is formed on the back side of the substrate corresponding to each of the cells.
  • the substrate is diced along the trench 2 to obtain a chip die as shown in FIG. Fig. 7 further shows the structure of the grain after the slitting in a sectional view.
  • a silicon (111) substrate is patterned on the surface by a conventional photolithographic mask and then plasma etched as shown in Fig. 1.
  • the square area 1 in the figure is a 3 ⁇ 4 face area that is not etched.
  • Area 2 is the grooved area that is engraved.
  • the cross-sectional structure of the substrate after the groove is shown in Fig. 2.
  • the center distance of two adjacent square lattices is 3000 micrometers
  • the width of the trenches is 50 micrometers
  • the depth of the trenches is 200 micrometers.
  • the patterned substrate is cleaned by a well-known silicon wafer cleaning process, placed in a reaction chamber, and indium gallium aluminum nitride required for a light-emitting device including a buffer layer, an n-type layer, a light-emitting layer, and a p-type layer is sequentially deposited on the surface.
  • Multi-layer structure The total thickness of the indium gallium aluminum nitride multilayer film 3 was 4 ⁇ m.
  • the substrate has a structure as shown in Fig. 3. A small area is formed on each of the mesas by photolithography masking and ICP etching, in which the n-type layer in the indium gallium aluminum nitride multilayer film 3 is exposed.
  • An n-type electrode 6 is formed in the exposed n-type region, and a p-type electrode 4 is formed on the etched mesa (p-type layer).
  • the substrate is then slashed along trench 2 to obtain separate chip dies.
  • a silicon (111) substrate is patterned on the surface by a conventional photolithographic mask and then plasma etched to form a triangular lattice pattern as shown in FIG.
  • Area 1 in the figure is a mesa region that is not etched.
  • Area 2 is the grooved area that is engraved.
  • the sides of the triangle are 300 microns, the width of the grooves is 20 microns, and the depth of the grooves is 20 microns.
  • the patterned lining is cleaned by a well-known silicon wafer cleaning process, placed in a reaction chamber, and indium gallium-aluminum-nitrogen required for a light-emitting device including a buffer layer, an n-type layer, a light-emitting layer, and a p-type layer is sequentially deposited on the surface.
  • the total thickness of the indium gallium aluminum nitride multilayer film 3 is 4 Micron.
  • a p-type electrode 4 is formed on each of the mesas, and an n-type electrode 6 is formed on the back side of the substrate corresponding to each of the cells.
  • the substrate is diced along the trench 2 to obtain separate chip dies.
  • a silicon (111) substrate is patterned on the surface by a conventional photolithographic mask and then plasma etched as shown in Fig. 5.
  • Area 1 in the figure is a mesa region that is not etched.
  • Region 2 and Region 2' are the grooved regions that are engraved.
  • the grooves 2 are perpendicular to each other, and the grooves 2' are at an angle of 45 degrees to the grooves 2.
  • the groove 2 divides the surface into square lattices having a side length of 4000 ⁇ m, and the grooves 2 further incompletely divides the grooves.
  • the single groove 2' has a length of 1500 microns.
  • the patterned substrate is cleaned by a well-known silicon wafer cleaning process, placed in a reaction chamber, and indium gallium aluminum nitride required for a light-emitting device including a buffer layer, an n-type layer, a light-emitting layer, and a P-type layer is sequentially deposited on the surface.
  • Multi-layer structure The total thickness of the indium gallium aluminum nitride multilayer film 3 is 3 ⁇ m.
  • a p-type electrode 4 is formed on each of the mesas, and an n-type electrode 6 is formed on the back side of the substrate corresponding to each of the cells.
  • the substrate is diced along the trench 2 to obtain separate chip dies.
  • a silicon (111) substrate is patterned on the surface by a conventional photolithographic mask and then plasma etched as shown in Fig. 1.
  • the square area 1 in the figure is a mesa area which is not etched.
  • Area 2 is the grooved area that is engraved.
  • the cross-sectional structure of the substrate after the groove is shown in Fig. 2.
  • the lattice has a rectangular shape with a size of 500 X 400 ⁇ m, a groove width of 30 ⁇ m, and a groove depth of 300 ⁇ m.
  • the patterned substrate is cleaned by a well-known silicon wafer cleaning process, placed in a reaction chamber, and indium gallium aluminum nitride including a buffer layer, an n-type layer, a light-emitting layer, a p-type layer, and the like is sequentially deposited on the surface.
  • Multi-layer structure The total thickness of the indium gallium aluminum nitride multilayer film 3 was 6 ⁇ m.
  • the substrate section has a structure as shown in FIG. A small area is formed on each of the mesas by photolithography masking and ICP etching, in which the n-type layer in the indium gallium aluminum nitride multilayer film 3 is exposed.
  • An n-type electrode 6 is formed in the exposed n-type region, and a P-type electrode 4 is formed on the unetched mesa (p-type layer).
  • the substrate is then slashed along trench 2 to obtain separate chip dies. '

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Description

在硅衬底上制备铟镓铝氮薄膜及发光器件的方法 技术领域
本发明涉及一种半导体材料，尤其是涉及一种在硅衬底上制备铟镓铝氮薄 膜及发光器件的方法。
背景技术：
铟镓铝氮 （
Figure imgf000003_0001
) 是制备短波长发光器件的 优选材料体系之一。 近年来在世界各地研究人员的努力下， 已经用铟镓铝氮材 料制造出许多新颖的发光器件， 如蓝色、 绿色、 白色发光二极管， 以及紫色半 导体激光器等等。 同时铟镓铝氮材料也是制备许多高性能电子器件的良好材 料。
在现有技术中，在蓝宝石衬底和碳化硅衬底上制备铟镓铝氮材料的方法已 经为公众所知。 例如， 日本专利一 JP2737053 中公开了一种在蓝宝石衬底上制 备氮化镓材料的方法； 美国专利 US— 5686738中公开了一种在碳化硅衬底上制 备氮化镓材料的方法。 根据这些公开的技术， 已经可以制备出高质量的铟镓铝 氮材料。 但是， 由于碳化硅衬底非常昂贵， 因而用于生长铟镓铝氮材料将使成 本很高。 而蓝宝石衬底也比较贵， 并且它是绝缘体， 加工困难， 不能制成具有 上下电极的芯片结构， 这样就导致器件制造工艺复杂， 成本增加。 硅是一种最 成熟的半导体材料， 它不仅价格便宜， 而且容易控制其导电类型和电阻率， 其 加工工艺也很成熟， 如果用于生长铟镓铝氮将可以大大节约成本。 但是硅和铟 镓铝氮材料的晶格失配和热失配都很大， 在硅上生长的铟镓铝氮很容易出现裂 纹， 从而无法制备出高性能的发光或电子器件。 文献 （Phys. stat. sol. (a) 188， 155 (2001) ) 给出了一种在衬底上用氮化硅进行区域掩膜的方法， 可以 减少裂纹的出现，但该方法工艺较复杂，不利于规模化生产。文献（Appl. Phys. Lett. 78， 288 (2001) ) 提出了一种侧向限制外延的方法， 通过形成沟槽来改 善应力释放， 然而该文献的结论指出， 用此方法在硅（111)衬底上生长厚度为 0. 7微米的 GaN， 得到的无裂区域最大不超过 14. 3微米。 由于制作欧姆电极的 需要， 发光芯片的面积一般要求大于 100 X 100微米 2， 因 b按照这些文献公开 的方法还无法制造出有效的发光器件。
发明内容：
本发明的目的之一是提供一种在硅衬底上制备无裂纹铟镓铝氮薄膜的方 法。
本发明的目的之二是提供一种制备铟镓铝氮发光器件的方法。
本发明的这些以及其他目的将通过下列详细说明和描述来进一步阐述。 本发明的在硅衬底上制备铟镓铝氮（InxGayAll- x-yN， 0<=χ<=1 , 0<=y<=l ) 薄膜的方法， 包括以下步骤：
A、 在硅衬底表面形成具有沟槽和台面的图形结构；
B、 在衬底表面沉积铟镓铝氮薄膜；
其中所述的沟槽的深度大于等于 6微米，并且沟槽两侧台面上生长的铟镓 铝氮薄膜互不相连。
进一步的， 在本发明的在硅衬底硅（111)上制备铟镓铝氮薄膜的方法中， 沟槽的深度为 6— 300微米， 较好为 10— 30微米； 沟槽的宽度大于其两侧台面 上向水平方向生长的薄膜的宽度， 较好的是沟槽的宽度为 6— 50微米， 可以选 择的是沟槽的宽度大于两倍的膜厚。 在衬底上的沟槽呈线形状， 彼此交错或相 连接， 或呈放射状发散， 或彼此不相交。
在本发明的在硅衬底上制备铟镓铝氮薄膜的方法中，在图形结构中，任意 互不相连的独立台面的周长与其面积之比大于 1. 0毫米 /毫米 2， 小于 40毫米 / 毫米 2， 较好的是大于 4毫米 /毫米 2， 小于 20毫米 /毫米 2。 所述的图形结构为 圆形、 三角形、 方形、 正方形、 多边形或其它不规则图形。 所述的台面面积大 于 100 X 100微米 2， 小于 3000 X 3000微米 2， 较好的是大于 200 X 200微米 2， 小于 1000 X 1000微米 2。 ;
在本发明的使用硅衬底制备铟镓铝氮（
Figure imgf000004_0001
〈=l， 0<=y<=l ) 发光器件的方法中， 包括如上所述的在硅衬底上制备铟镓铝氮薄膜的方法。 还 包括在所述的铟镓铝氮薄膜表面或衬底背面形成 P型和 N型电极， 然后沿着所 述的沟槽把衬底切开使每个台面形成一个独立的发光元件。
在本发明中， 多个发光器件同时但相互独立地在同一个硅衬底上形成。 本发明的使用硅衬底制备铟镓铝氮 （InxGayAlmN,
Figure imgf000004_0002
) 发光器件的方法， 包括如下步骤：
A、 在硅衬底上形成深度大于等于 6微米的沟槽， 使衬底表面分割成多个 面积大于 100 X 100微米 2、 小于 3000 X 3000微米 2的台面；
B、 在衬底表面沉积铟镓铝氮多层薄膜； C、 在所述的铟镓铝氮薄膜表面或衬底背面形成 P型和 N型电极；
D、 沿着所述的沟槽把衬底切开使每个台面形成一个独立的发光元件。 用本发明的方法可以通过简单的衬底处理而生长出髙质量、无裂紋和面积 较大的铟镓铝氮薄膜， 进而可以制备出髙性能和大量的发光器件。
在本发明中， 由于硅和铟镓铝氮材料之间的晶格失配和热失配很大，在大 面积的硅衬底上生长铟镓铝氮材料达到一定厚度后， 由于应力的累积就会导致 薄膜裂开。 因此本发明通过在衬底上开出一定密度且足够深度和宽度的沟槽来 减小缓解薄膜承受的应力。 由于衬底表面被分割成许多区域， 因此在每个区域 内生长的铟镓铝氮材料在空间上就是分离的，因此增加了自由面，减少了应力。 另一方面， 槽必须具有足够的深度， 以使铟镓铝氮外延薄膜和衬底之间的应力 分布发生改变。 当槽的深度足够深， 则硅台面可以承受更大的应力， 从而减少 台面上生长的铟镓铝氮薄膜所受的应力， 防止薄膜裂开。 由于制备铟镓铝氮发 光二极管所需薄膜的厚度一般大于 3微米， 本发明的方法要求槽的深度大于 6 微米。
在本发明中， 衬底上的沟槽可以组合呈线形状， 但是以能够减少应力， 并 最终使发光材料能够应用为前提。 它们可以是彼此交错或连接的， 构成圆形， 三角形， 方形， 正方形、 多边形或其他不规则图形等， 也可以呈放射状发散， 甚至彼此不相交的任意形状， 一般优选让纵横交错的槽把衬底分割成一定形状 的许多格子。 格子的形状可以是正方型、 长方形、 三角形等任意常见的规则形 状。 为方便器件制备， 优选的形状为正方形。 槽的形成方法可以是任意成熟的 刻槽方法， 如干法刻蚀、 湿法刻蚀、 机械划片等方法。 由于在台面的边缘薄膜 会在水平方向上生长而向外延伸， 为避免相邻的台面上薄膜因为相互延伸而对 接起来， 沟槽的宽度还必须大于水平方向生长的薄膜的厚度， 优选的条件是大 于两倍的膜厚。 为了有效驰豫应力， 根据衬底的面积， 需要的沟槽数目或长度 不同， 本发明方法的优选条件为沟槽的密度需要达到使任意独立的台面的周长 /面积比大于 1. 0毫米 /毫米 2。 为了能够形成欧姆电极以制作有效的发光器件， 沟槽的密度也不能太大，在本发明方法中所述的台面面积大于 100 X 100微米 2。
由于生长在硅衬底上的铟镓铝氮材料很薄而且很脆，在切割芯片时如果刀 片从长有铟镓铝氮材料的正面进行划片会对薄膜造成破坏使之崩裂； 而硅片在 可见光范围内又不透明， 难以像蓝宝石衬底一样釆取背面划片然后裂片的办 法。 本发明根据设计的芯片尺寸， 在进行铟镓铝氮材料生长前预先在衬底表面 刻出与芯片尺寸相对应的格子， 然后再生长铟镓铝氮薄膜。 这样在划片时让划 片刀沿着生长前刻好的沟槽进行切割， 槽的宽度大于刀片厚度， 就可使刀片不 碰到台面上生长的薄膜材料， 也就不会造成薄膜崩裂， 从而得到完整的芯片晶 粒。根据本发明的方案，芯片的电极结构既可以是同侧电极也可以是上下电极。 根据本发明的方法， 也可以把生长好的铟镓铝氮转移到另一个硅衬底或其它材 料的衬底上再制作成发光器件。
附图说明：
图 1是刻有沟槽的衬底表面局部示意图；
图 2是图 1中 A-A方向的横截面示意图；
图 3是在硅衬底上生长铟镓铝氮薄膜后的横截面示意图；
图 4是本发明另一种实施例衬底表面刻槽形状示意图；
图 5是本发明又一种实施例衬底表面刻槽形状示意图；
图 6是用 1和图 3所示的外延片制作好欧姆电极并划片后的外观示意图； 图 7是图 6中 B-B方向的横截面示意图。
所有图中相同的数字其指向物均具有相同的含义。其中 1为台面，2和 2' 为沟槽， 3为铟镓铝氮薄膜， 4为 p型电极， 5为划片槽， 6为 n型电极。
在本发明中所涉及到的设备均为目前本行业中的常用设备，在此不多作介 绍。
下面结合实施例对本发明进行具体的描述。 由技术常识可知， 本发明可以 通过其他的不脱离其精神实质或必要特征的实施方案来实现。 因此， 下列实施 方案， 就各方面而言， 都只是举例说明， 并不是仅有的。 所有在本发明范围内 或等同本发明的范围内的改变均被本发明包含。
具体实施方式
实施例 1 :
参照附图。 把一块硅（111)衬底用常规的光刻掩膜然后等离子刻蚀的办法 在表面刻出如图 1示出的格子图形。 图中正方形区域 1为未被刻蚀的台面区。 区域 2则为被刻出的沟槽区。 图 2用断面图更加清楚地示出了这种台面和沟槽 结构。 在本实施例中， 相邻两个正方形格子的中心距离为 100微米， 沟槽的宽 度为 6微米， 沟槽的深度为 6微米。 把刻好图形的衬底用熟知的硅片清洗工艺 清洗干净， 放入反应室， 在表面沉积包括缓冲层、 n型层、 发光层、 p型层等 发光器件所需的铟镓铝氮多层结构。 铟镓铝氮多层薄膜 3的总厚度为 4微米。 沉积完成后， 衬底断面具有如图 3所示的结构。 对比图 2和图 3， 可以看出， 台面和沟槽内都会有铟镓铝氮材料沉积， 由于槽的深度大于薄膜厚度， 槽内生 长的薄膜和台面上生长的薄膜互相之间没有连接。 在台面四周薄膜沿水平方向 也会向外生长并突出于台面边缘。 由于槽宽足够宽， 因此相邻台面上生长的薄 膜并没有由于向外延伸而对接起来。 这样由于各台面上生长的薄膜都是相互独 立的并且自由的， 因此应力可以得到释放， 台面上不会出现裂纹。 在薄膜生长 完成后， 在每个台面上制作一个 p型电极 4， 在衬底背面相应于每个格子制作 一个 n型电极 6。 沿着沟槽 2将衬底划开， 就得到如图 6所示的芯片晶粒。 图 7用断面图进一步示出了划开后晶粒的结构。
实施例 2:
把一块硅（111)衬底用常规的光刻掩膜然后等离子刻蚀的办法在表面刻出 如图 1示出的格子图形。 图中正方形区域 1为未被刻蚀的 ¾面区。 区域 2则为 被刻出的沟槽区。 刻槽后的衬底断面结构如图 2示。 在本实施例中， 相邻两个 正方形格子的中心距离为 3000微米，沟槽的宽度为 50微米，沟槽的深度为 200 微米。 把刻好图形的衬底用熟知的硅片清洗工艺清洗干净， 放入反应室， 在表 面依次沉积包括缓冲层、 n型层、 发光层、 p型层等发光器件所需的铟镓铝氮 多层结构。 铟镓铝氮多层薄膜 3的总厚度为 4微米。 沉积完成后， 衬底断面具 有如图 3所示的结构。 用光刻掩膜和 ICP刻蚀的办法在每个台面上刻出一个小 区域， 在该区域内暴露出铟镓铝氮多层薄膜 3中的 n型层。 在暴露的 n型区制 作一个 n型电极 6, 在为刻蚀的台面（p型层）上制作一个 p型电极 4。 然后沿 着沟槽 2将衬底划开， 就得到分离的芯片晶粒。
实施例 3:
参照附图。 把一块硅 (111)衬底用常规的光刻掩膜然后等离子刻蚀的办法 在表面刻出如图 4示出的三角格子图形。 图中区域 1为未被刻蚀的台面区。 区 域 2则为被刻出的沟槽区。 在本实施例中， 三角形的边长为 300微米， 沟槽的 宽度为 20微米， 沟槽的深度为 20微米。 把刻好图形的衬 用熟知的硅片清洗 工艺清洗干净， 放入反应室， 在表面依次沉积包括缓冲层、 η型层、 发光层、 ρ 型层等发光器件所需的铟镓铝氮多层结构。 铟镓铝氮多层薄膜 3的总厚度为 4 微米。 薄膜生长完成后， 在每个台面上制作一个 p型电极 4， 在衬底背面相应 于每个格子制作一个 n型电极 6。 沿着沟槽 2将衬底划开， 就得到分离的芯片 晶粒。
实施例 4:
参照附图。 把一块硅 (111)衬底用常规的光刻掩膜然后等离子刻蚀的办法 在表面刻出如图 5示出的图形。 图中区域 1为未被刻蚀的台面区。 区域 2和区 域 2' 则为被刻出的沟槽区。 沟槽 2为互相垂直， 而沟槽 2' 则与沟槽 2成 45 度角。沟槽 2把表面分割成边长为 4000微米的正方形的格子， 沟槽 2， 则进一 步把沟槽作不完全分割。单条沟槽 2' 长度为 1500微米。把刻好图形的衬底用 熟知的硅片清洗工艺清洗干净， 放入反应室， 在表面依次沉积包括缓冲层、 n 型层、 发光层、 P型层等发光器件所需的铟镓铝氮多层结构。 铟镓铝氮多层薄 膜 3的总厚度为 3微米。薄膜生长完成后， 在每个台面上制作一个 p型电极 4， 在衬底背面相应于每个格子制作一个 n型电极 6。 沿着沟槽 2将衬底划开， 就 得到分离的芯片晶粒。
实施例 5:
把一块硅（111)衬底用常规的光刻掩膜然后等离子刻蚀的办法在表面刻出 如图 1示出的格子图形。 图中方形区域 1为未被刻蚀的台面区。 区域 2则为被 刻出的沟槽区。 刻槽后的衬底断面结构如图 2示。 在本实施例中， 格子为长方 形， 尺寸为 500 X 400微米， 沟槽的宽度为 30微米， 沟槽的深度为 300微米。 把刻好图形的衬底用熟知的硅片清洗工艺清洗干净， 放入反应室， 在表面依次 沉积包括缓冲层、 n型层、 发光层、 p 型层等发光器件所薷的铟镓铝氮多层结 构。 铟镓铝氮多层薄膜 3的总厚度为 6微米。 沉积完成后， 衬底断面具有如图 3所示的结构。 用光刻掩膜和 ICP刻蚀的办法在每个台面上刻出一个小区域， 在该区域内暴露出铟镓铝氮多层薄膜 3中的 n型层。 在暴露的 n型区制作一个 n型电极 6， 在未刻蚀的台面 （p型层） 上制作一个 P型电极 4。 然后沿着沟槽 2将衬底划开， 就得到分离的芯片晶粒。 '

Claims

权利要求
1、一种在硅衬底上制备铟镓铝氮薄膜的方法，其特征在于包括以下步骤：
A、 在硅衬底表面形成具有沟槽和台面的图形结构；
B、 在衬底表面沉积铟镓铝氮薄膜；
其中所述的沟槽的深度大于等于 6微米，并且沟槽两侧台面上生长的铟镓 铝氮薄膜在水平方向上互不相连。
2、 根据权利要求 1所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其特征 在于沟槽的深度为 6— 300微米。
3、 根据权利要求 1所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其特征 在于沟槽的深度为 10- 30微米。
4、 根据权利要求 1所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其特征 在于沟槽的宽度大于其两侧台面边缘向外生长的薄膜宽度。
5、 根据权利要求 1或 4所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其 特征在于沟槽的宽度大于两倍的膜厚。
6、 根据权利要求 4或 5所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其特征在于沟槽的宽度为 6— 50微米。
7、 根据权利要求 1一 6之一所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其特征在于在衬底上的沟槽呈线形状， 彼此交错或相连接， 或呈放射状发散， 或彼此不相交。
8、 根据权利要求 1所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其特征 在于在图形结构中， 任意互不相连的独立台面的周长与其面积之比大于 1. 0毫 米 /毫米 2， 小于 40毫米 /毫米 2，
9、 根据权利要求 1所述的在硅衬底上制备铟镓铝氮薄膜的方法， 其特征 在于在图形结构中， 任意互不相连的独立台面的周长与其面积之比为大于 4毫 米 /毫米 2， 小于 20毫米 /毫米 2。
10、根据权利要求 8或 9所述的在硅衬底上制备铟镓铝氮薄膜的方法，其 特征在于所述的图形结构为圆形、 三角形、 方形、 正方形 多边形或其他不规 则图形。
11、根据权利要求 8或 9所述的在硅衬底上制备铟镓铝氮薄膜的方法，其 特征是所述的台面面积大于 100 X 100微米 2， 小于 3000 X 3000微米 2。
12、根据权利要求 8或 9所述的在硅衬底上制备铟镓铝氮薄膜的方法，其 特征在于所述的台面面积大于 200 X 200微米 2， 小于 1000 X 1000微米 2。
13、一种使用硅衬底制备铟镓铝氮发光器件的方法，其特征在于包括权利 要求 1一 12的方法。
14、 根据权利要求 13所述的使用硅衬底制备铟镓铝氮发光器件的方法， 其特征在于还包括在所述的铟镓铝氮薄膜表面或衬底背面形成 P 型和 N型电 极， 然后沿着所述的沟槽把衬底切幵使每个台面形成一个独立的发光元件。
15、根据权利要求 13或 14所述的使用硅衬底制备铟镓铝氮发光器件的方 法， 其特征在于在进行铟镓铝氮材料生长前预先在衬底表面刻出与芯片尺寸相 对应的格子， 然后再生长铟镓铝氮薄膜。
16、根据权利要求 13或 14所述的使用硅衬底制备铟镓铝氮发光器件的方 法， 其特征在于在划片时让划片刀沿着生长前刻好的沟槽进行切割。
17、 根据权利要求 13— 16之一所述的使用硅衬底制备铟镓铝氮发光器件 的方法， 其特征在于芯片的电极结构既可以是同侧电极也可以是上下电极。
18、 根据权利要求 13— 16之一所述的使用硅衬底制备铟镓铝氮发光器件 的方法， 其特征在于多个发光器件同时但相互独立地在同一个硅衬底上形成。
19、一种使用硅衬底制备铟镓铝氮发光器件的方法，其特征在于包括如下 步骤：
A、 在硅衬底上形成深度大于等于 6微米的沟槽， 使衬底表面分割成多个 面积大于 100 X 100微米 2、 小于 3000 X 3000微米 2的台面；
B、 在衬底表面沉积铟镓铝氮薄膜；
C、 在所述的铟镓铝氮薄膜表面或衬底背面形成 P型和 N型电极；
D、 沿着所述的沟槽把衬底切开使每个台面形成一个独立的发光元
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