WO2006103977A1 - ディスプレイ駆動回路 - Google Patents
ディスプレイ駆動回路 Download PDFInfo
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- WO2006103977A1 WO2006103977A1 PCT/JP2006/305576 JP2006305576W WO2006103977A1 WO 2006103977 A1 WO2006103977 A1 WO 2006103977A1 JP 2006305576 W JP2006305576 W JP 2006305576W WO 2006103977 A1 WO2006103977 A1 WO 2006103977A1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0252—Improving the response speed
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
- H03F2203/30099—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor the pull transistor being gated by a switching element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
- H03F2203/30132—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor the push transistor being gated by a switching element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45618—Indexing scheme relating to differential amplifiers the IC comprising only one switch
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45726—Indexing scheme relating to differential amplifiers the LC comprising more than one switch, which are not cross coupled
Definitions
- the present invention relates to a drive circuit for driving a display element such as a liquid crystal element.
- a display driver is used to drive the vertical lines of a display panel such as a liquid crystal panel.
- a number of display drive circuits are mounted according to the number of vertical lines.
- the display drive circuit receives an input voltage having a gradation level (voltage value) corresponding to an image to be displayed, or receives a plurality of bit data inputs corresponding to the gradation level, and responds to the input voltage. Outputs the output voltage to the vertical line corresponding to itself.
- Patent Document 1 Japanese Patent Laid-Open No. 2001-156559
- the display drive circuit includes an P-type MOS differential input unit 1 including transistors M1, M2, and M3, and an N-type MOS including transistors M4, M5, and M6.
- a current mirror circuit 4 composed of a differential input section 2 and transistors M7, M8, M9 and M10, a current mirror circuit 4 composed of transistors Mil, M12, M13 and M14, and transistors Ml 5 and M16
- a phase compensation capacitance CI, C2 where Vdd is a positive power supply voltage and Vss is a negative power supply voltage.
- FIG. 25 shows changes in the voltage Vin applied to the display drive circuit, the voltage Vc at the connection node of the phase compensation capacitances CI and C2, and the output voltage Vout received by the vertical line.
- the output terminal of the display drive circuit is disconnected from the vertical line of the display.
- the voltage value of the input voltage Vin fluctuates.
- the phase compensation capacitors Cl and C2 charge and discharge charges according to the fluctuation of the voltage value of the input voltage Vin.
- the voltage Vc at the connection node of the phase compensation capacitances CI and C2 gradually increases. This The rate of discharge is proportional to the amount of current (tail current) flowing in each of the transistors M1 and M6, and inversely proportional to the capacitance value of the phase compensation capacitances CI and C2.
- the output terminal of the display drive circuit is not connected to the vertical line, the voltage value of the output voltage Vout applied to the vertical line does not change.
- the output terminal of the display drive circuit and the vertical line are connected, and the voltage Vc at the connection node of the phase compensation capacitances CI and C2 is output to the vertical line via the output circuit 5. Be done. As shown in FIG. 25, the voltage value of the output voltage Vout gradually rises as the voltage Vc rises.
- Patent Document 2 Japanese Patent Application Laid-Open Nos. 11-259052 (Patent Document 2), 2000-295044 (Patent Document 3), and 2003-228353 (Patent Document 4). Etc are shown.
- Patent Document 5 As a display driver of a conventional dot inversion drive system, Patent Nos. 2002-14658 (Patent Document 5) are disclosed.
- the display driver 10 of Patent Document 5 FIG. 4
- gradation voltages of positive polarity and negative polarity are alternately supplied to odd-numbered vertical lines and even-numbered vertical lines.
- a switch 16 is connected between each display drive circuit 14. In this display driver, turning on / off the switch 16 distributes the charge accumulated in each horizontal line. In this way, we are aiming for effective ⁇ IJ of charge.
- FIG. 26 shows input voltages Vin (2n-1) and Vin (2n) applied to the respective display drive circuits and voltages Vc (2n_l) and Vc (2n) generated in the phase compensation capacitances of the display drive circuits.
- the figure shows how the output voltage Vout (2n_l) and Vout (2n) received by the vertical line change.
- each of the display drive circuits 14 outputs an output voltage Vout (2n_l), Vout (2n) according to the input voltage Vin (2n_l), Vin (2n).
- Vin (2n_l) charges corresponding to the input voltages Vin (2n-1) and Vin (2n) are accumulated.
- the switch 16 is turned on, and the output terminal of the (2n ⁇ l) th display drive circuit 14 is connected to the output terminal of the (2n) th display drive circuit 14. Ru. Also, since switch 15 is turned off, each output terminal is disconnected from the vertical line.
- the switch 16 is turned off, the switch 15 is turned on, and the output terminal of the display drive circuit 14 is connected to the vertical line, and the voltage V c (2n) of the phase compensation capacitance is obtained.
- -l), Vc (2n) are output via the output circuit.
- the voltage values of the output voltages Vout (2n-l) and Vout (2n) gradually increase toward the target value as the voltages Vc (2n_l) and Vc (2n) rise and fall Z. Ascend / descend.
- Patent Document 6 Patent No. 35869898 (Patent Document 6), Patent No. 3063670 (Patent Document 7), Japanese Patent Application Laid-Open Nos. 2000-39870 (Patent Document 8), Japanese Patent Application Laid-Open No. 2000 ⁇ 22193 (Patent Document 9), JP-A 10-133174 (Patent Document 10), JP-A 10-3 03537 (Patent Document 11, JP-A 2000-39870 (Patent Document 12), Japanese Patent Application Laid-Open No. 2000-221932 (Patent Document 13), U.S. Patent No. 6, 650, 312 (Patent Document 14), U.S. Patent No. 6, 184, 855 (Patent Document 15), etc. There is.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2001-156559
- Patent Document 2 Japanese Patent Application Laid-Open No. 11 259052
- Patent Document 3 Japanese Patent Application Laid-Open No. 2000-295044
- Patent Document 4 Japanese Patent Application Laid-Open No. 2003 228353
- Patent Document 5 Japanese Patent Application Laid-Open No. 2002- 14658
- Patent Document 6 Patent No. 3586998
- Patent Document 7 Patent No. 3063670
- Patent Document 8 Japanese Patent Laid-Open No. 2000-39870
- Patent Document 9 Japanese Patent Laid-Open No. 2000-221932
- Patent Document 10 Japanese Patent Application Laid-Open No. 10-133174
- Patent document 11 Unexamined-Japanese-Patent No. 10-301537
- Patent Document 12 Japanese Patent Application Laid-Open No. 2000-39870
- Patent Document 13 Japanese Patent Application Laid-Open No. 2000-221932
- Patent Document 14 U.S. Patent No. 6,650, 312
- Patent Document 15 U.S. Patent No. 6,184,855.
- an object of the present invention is to change the voltage value of the output voltage at high speed. More specifically, it is an object of the present invention to provide a display driving circuit in which the time required for the voltage value of the output voltage to reach the target value is shortened by charging and discharging the phase compensation capacitance at high speed in the transition mode.
- a display drive circuit has an input terminal to which an input voltage is applied, and an output terminal for outputting an output voltage to a vertical line of a display panel.
- the display drive circuit outputs an output voltage according to the input voltage. And a transition mode in which the voltage value of the input voltage is changed.
- the display drive circuit includes a differential amplification unit, a first capacitive element, an output unit, an output switch, a first supply switch, an input switch, and a supply switching unit.
- the differential amplification unit has a first input node connected to the input terminal, a second input node, and a first output node.
- the differential amplification unit outputs, from the first output node, a first voltage according to a difference between voltages applied to each of the first and second input nodes.
- the first capacitive element is connected between the first supply node and the intermediate node.
- the first supply node is connected to the first output node of the differential amplification unit.
- the intermediate node is connected to the second input node of the differential amplifier.
- the output unit includes an input / output node, a first drive transistor connected between the first reference node and the input / output node, and a second drive transistor connected between the input / output node and the second reference node. Have.
- the output unit also supplies the output current generated by the first and second drive transistors to the intermediate node via the input / output node.
- the output switch is connected between the input / output node of the output section and the output terminal, turned on in the output mode, and turned off in the transition mode.
- the first supply switch is connected between the first supply node and the third reference node, and is turned off in the output mode and turned on in the transition mode.
- the third reference node is provided with a voltage whose impedance is lower than the first voltage from the differential amplification unit.
- the input switch is connected between the intermediate node and the input terminal and is off in the output mode and on in the transition mode.
- the supply switching unit causes the output unit to supply the output current in the output mode and stops the supply of the output current to the output unit in the transition mode.
- the voltage at the intermediate node is supplied to the output terminal via the output section.
- the transition mode one end of the first capacitance element is connected to the third reference node, and the other end is connected to the input terminal.
- the charge / discharge rate of the charge in the first capacitive element is faster than in the output mode. Therefore, during the transition mode, the charge of the charge amount according to the input voltage can be quickly stored in the first capacitive element, and the voltage value of the voltage of the first capacitive element is quickly varied to the voltage value of the input voltage. be able to. Therefore, the time for the output voltage to reach the target value (voltage value of the input voltage) after entering the output mode is shorter than in the past. Thus, the fluctuation of the voltage value of the output voltage is It is possible to change S quickly.
- the differential amplification unit further includes a second output node.
- the differential amplifier unit outputs, from the second output node, a second voltage according to the difference between the voltages applied to the first and second input nodes.
- the display drive circuit further includes a second capacitive element and a second supply switch.
- the second capacitive element is connected between the second supply node and the intermediate node.
- the second supply node is connected to the second output node of the differential amplifier.
- the second supply switch is connected between the second supply node and the fourth reference node, turned off in the output mode, and turned on in the transition mode.
- the fourth reference node is provided with a voltage whose impedance is lower than the second voltage from the differential amplifier.
- the voltage at the intermediate node is supplied to the output terminal via the output unit.
- one end of the first capacitance element is connected to the third reference node, and the other end is connected to the input terminal.
- one end of the second capacitive element is connected to the fourth reference node, and the other end is connected to the input terminal.
- the voltage from the third and fourth reference nodes has a low impedance, the charge / discharge rate of the charge in the first and second capacitive elements is faster than in the output mode.
- the charge of the charge amount according to the input voltage can be quickly stored in the first and second capacitive elements, and the voltage value at the intermediate node is the voltage value of the input voltage. Can be changed quickly. Therefore, the time required for the voltage value of the output voltage to reach the target value after entering the output mode is shorter than in the prior art. Thus, the fluctuation of the voltage value of the output voltage can be fluctuated at high speed.
- the supply switching unit includes a connection switch.
- the connection switch is connected between the intermediate node and the input / output node of the output unit.
- the connection switch connects the intermediate node and the input / output node in the output mode and disconnects the intermediate node and the input / output node in the transition mode.
- an output current flows in the first and second drive transistors of the output unit.
- the output current of the output section is supplied between the intermediate node and the output terminal.
- the transition mode the intermediate node is not connected to the input / output node of the output section, and no output current is supplied between the intermediate node and the output terminal. Les. This makes it possible to prevent the output current from flowing between the output section and the input terminal during the transition mode.
- the display drive circuit further includes a first current limit transistor and a second current limit transistor.
- the first current limit transistor is connected between the first reference node and the first drive transistor, and receives a first predetermined voltage at its gate.
- the second current limit transistor is connected between the second reference node and the second drive transistor, and receives a second predetermined voltage at its gate.
- the display drive circuit further includes a first clamp circuit and a second clamp circuit.
- the first clamp circuit limits the gate voltage of the first drive transistor.
- the second clamp circuit limits the gate voltage of the second drive transistor.
- each of the first supply switch, the second supply switch, and the input switch is turned on from off before the transition mode is changed to the output mode.
- the display drive circuit has an input terminal to which an input voltage indicating positive or negative polarity is applied, and an output terminal to output the first output voltage to the vertical line of the display.
- the display drive circuit also has an output mode and a transition mode. In the output mode, another output terminal for outputting the second output voltage of the opposite polarity to the first output voltage to another vertical line of the display is disconnected from its own output terminal, and the output voltage is adjusted according to the input voltage. Output the first output voltage.
- the transition mode one output terminal is connected to another output terminal, and the polarity of the input voltage is inverted.
- the display drive circuit includes a differential amplification unit, a first capacitive element, an output unit, a first supply switch, and a supply switching unit.
- the differential amplifier has a first input node connected to the input terminal, a second input node, and a first output node. Also, the differential amplification unit outputs, from the first output node, a first voltage according to a difference between voltages applied to each of the first and second input cathodes.
- the first capacitive element is connected between the first supply node and the intermediate node.
- the first supply node is connected to a first output node of the differential amplifier unit.
- the intermediate node is connected to the second input node of the differential amplifier.
- the output unit is connected between the input / output node and the first reference node and the input / output node. And a second drive transistor connected between the input / output node and the second reference node.
- the output unit also supplies the output current generated by the first and second drive transistors to the intermediate node and the output terminal through the input / output node.
- the first supply switch is connected between the first supply node and the third reference node, and is turned off in the output mode and turned on in the transition mode.
- the third reference node is provided with a voltage whose impedance is lower than the first voltage from the differential amplifier.
- the supply switching unit causes the output unit to supply the output current in the output mode and stops the supply of the output current to the output unit in the transition mode.
- the voltage at the intermediate node is supplied to the output terminal via the output unit.
- the output terminal is connected to another output terminal to distribute the charge accumulated at each output terminal.
- the voltage value of the output voltage of the output terminal becomes an intermediate value.
- one end of the first capacitive element is connected to the third reference node.
- the charge / discharge rate of the charge in the first capacitive element is faster than in the output mode.
- the charge of the charge amount corresponding to the voltage value (intermediate value) of the voltage at the output terminal can be quickly stored in the first capacitive element, and the voltage value of the first capacitive element is set to the intermediate value. Can be changed quickly. Further, since the intermediate node and the output terminal are connected, the voltage value of the voltage at the intermediate node and the voltage value of the voltage at the output terminal are equal to each other. Therefore, the time until the voltage value of the output voltage reaches the target value (voltage value of the input voltage) after entering the output mode is shorter than in the conventional case. Thus, the fluctuation of the voltage value of the output voltage can be fluctuated at high speed.
- the distributed charge can be effectively reused. This can reduce power consumption.
- the differential amplifier unit further includes a second output node.
- the differential amplifier unit generates a second voltage corresponding to a difference between voltages applied to the first and second input nodes. Output from force node.
- the display drive circuit further includes a second capacitive element and a second supply switch.
- the second capacitive element is connected between the second supply node and the intermediate node.
- the second supply node is connected to the second output node of the differential amplifier.
- the second supply switch is connected between the second supply node and the fourth reference node, turned off in the output mode, and turned on in the transition mode.
- the fourth reference node is provided with a voltage whose impedance is lower than the second voltage from the differential amplifier.
- the voltage at the intermediate node is supplied to the output terminal via the output unit.
- the output terminal is connected to another output terminal to distribute the charge accumulated at each output terminal.
- the voltage value of the output voltage of the output terminal becomes an intermediate value.
- one end of the first capacitive element is connected to the third reference node, and one end of the second capacitive element is connected to the fourth reference node.
- the charge / discharge rate of the charge in the first and second capacitive elements is faster than in the output mode.
- the supply switching unit includes an output switch, a first connection switch, and a second connection switch.
- An output switch is connected between the input / output node of the output section and the output terminal. The output switch connects the input / output node to the output terminal in the output mode, and disconnects the input / output node from the output terminal in the transition mode.
- the first connection switch is connected between the intermediate node and the input / output node of the output unit. The first connection switch connects the intermediate node to the input / output node in the output mode, and disconnects the intermediate node from the input / output node in the transition mode.
- the second connection switch is connected between the intermediate node and the output terminal. Second connection The switch disconnects the intermediate node and its output terminal in the output mode, and connects the intermediate node and its output terminal in the transition mode.
- an output current flows in the first and second drive transistors of the output unit.
- the output In the output mode, the output is connected to the intermediate node and the output terminal. Thereby, the output current is supplied between the intermediate node and the output terminal.
- the transition mode the output is disconnected from the intermediate node and the output terminal. As a result, no output current is supplied between the intermediate node and the output terminal.
- each of the first and second supply switches is turned on from off before the transition mode is changed to the output mode.
- the display drive circuit described above can suppress voltage fluctuations at the first supply node, the second supply node, and the intermediate node before entering the output mode.
- the supply switching unit includes a first connection switch and a second connection switch.
- the first connection switch is connected between the drain of the first drive transistor and the input / output node.
- the first connection switch connects the drain to the input / output node in the output mode, and disconnects the drain from the input / output node in the transition mode.
- the second connection switch is connected between the input / output node and the drain of the second drive transistor. The second connection switch connects the input / output node and the drain in the output mode, and disconnects the input / output node and the drain in the transition mode.
- the first drive transistor is a PMOS transistor, and receives a voltage corresponding to the voltage of the first output node, the source connected to the first reference node, the drain connected to the input / output node, and the drain. And a gate.
- the second driving transistor is an NMOS transistor, a source connected to the second reference node, a drain connected to the input / output node, and a gate receiving a voltage corresponding to the voltage of the second output node.
- the differential amplification unit includes a first differential input circuit, a first power mirror circuit, a second differential input circuit, and a second current mirror circuit.
- the first differential input circuit includes first and second input side transistors.
- the source of each of the first and second input side transistors is connected to the second reference node.
- the gate of the first input side transistor receives the voltage of the first input node.
- the gate of the second input side transistor receives the voltage of the second input node.
- the first current mirror circuit includes first and second output side transistors receiving outputs of the first and second input side transistors.
- the source of each of the first and second output side transistors is connected to the first reference node.
- the gates of each of the first and second output side transistors are connected to each other.
- the drain of the first output side transistor is connected to the first output node.
- the gate and the drain of the second output side transistor are connected to each other.
- the second current mirror circuit includes third and fourth input side transistors.
- the source of each of the third and fourth input side transistors is connected to the first reference node.
- the gate of the third input transistor receives the voltage of the first input node.
- the gate of the fourth input side transistor receives the voltage of the second input node.
- the second current mirror circuit includes third and fourth output side transistors receiving outputs of the third and fourth input side transistors.
- the source of each of the third and fourth output side transistors is connected to the second reference node.
- the gates of the third and fourth output side transistors are connected to each other.
- the drain of the third output transistor is connected to the second output node.
- the gate and the drain of the fourth output side transistor are connected to each other.
- the supply switching unit includes a connection switch.
- the connection switch is connected between the first output node and the second output node. The connection switch connects the first output node and the second output node in the output mode, and disconnects the first output node and the second output node
- the display drive circuit in the output mode, current flows between the first and second output nodes, and each of the first and second output nodes responds to the difference between the input voltage and the voltage of the intermediate node. The voltage is output.
- the first and The current does not flow between the second output nodes, the positive voltage from the first reference node is applied to the gate of the first drive transistor, and the negative electrode from the second reference node is applied to the gate of the second drive transistor. Sexual voltage is given. Therefore, since the first and second drive transistors are deactivated, no output current flows to the output portion. As described above, since the output current flowing to the output section can be stopped during the transition mode, power consumption can be reduced.
- the differential amplifier unit further includes a first P-type transistor and a first N-type transistor connected in parallel between the first output node and the second output node. And a second P-type transistor and a second N-type transistor connected in parallel between the drains of the second and fourth output side transistors.
- the connection switch is connected between a third P-type transistor connected between the first output node and the first P-type transistor, and between the second output node and the first N-type transistor. And the third N-type transistor.
- Each of the third P-type transistor and the third N-type transistor is on in the output mode and off in the transition mode.
- the voltage between the source and the gate of each of the first P-type transistor and the first N-type transistor is connected to the third P-type transistor and the third N-type transistor. Since it can be made equal to the case without, it is possible to suppress the deviation of the operating point of the differential amplifier.
- the display drive circuit further includes a first blocking switch and a second blocking switch.
- a first blocking switch is connected between the first output node and the first supply node.
- the first cutoff switch connects the first output node and the first supply node in the output mode, and disconnects the first output mode and the first supply node in the transition mode.
- a second blocking switch is connected between the second output node and the second supply node. The second cutoff switch connects the second output node and the second supply node in the output mode, and disconnects the second output node and the second supply node in the transition mode.
- a first stable voltage corresponding to the voltage of the first supply node in the output mode is applied to the third reference node.
- a second stable voltage corresponding to the voltage of the second supply node in the output mode is applied to the fourth reference node.
- the display drive circuit described above can suppress voltage fluctuations at each of the first and second supply nodes that occur when the transition mode is changed to the output mode. As a result, it is possible to suppress the fluctuation of the voltage Vc at the intermediate node that occurs when the output mode is entered, so that the voltage value of the output voltage can be fluctuated at higher speed.
- the display drive circuit further includes a power supply circuit.
- the power supply circuit generates the first and second stable voltages, supplies the generated first stable voltage to the third reference node, and generates the generated second stable voltage as the fourth reference node. Supply to
- the power supply circuit includes a ladder resistor connected between the first reference node and the second reference node.
- the power supply circuit includes a supply differential amplifier, third and fourth capacitive elements, third and fourth drive transistors, a first voltage follower circuit, and a second voltage follower circuit.
- the supply differential amplification unit has a third input node receiving a predetermined voltage, a fourth input node, a third output node, and a fourth output node.
- the supply differential amplification unit outputs, from the third output node, the third voltage according to the difference between the voltages applied to the third and fourth input nodes, and outputs the fourth voltage from the fourth output node. .
- the third and fourth capacitive elements are connected in series between the third supply node connected to the third output node and the fourth supply node connected to the fourth output node, and are connected to connect each other
- the node is connected to the fourth input node.
- Third and fourth drive transistors are connected in series between the first reference node and the second reference node, and connection nodes connecting each are connected to connection nodes of the third and fourth capacitance elements. Connected
- the first voltage follower circuit receives the voltage at the third supply node and outputs the first stable voltage.
- Second voltage receives the voltage at the fourth supply node and outputs the second stable voltage.
- the supply switching unit sets the connection state of the first drive transistor such that the source is connected to the first reference node and the drain is connected to the input / output node.
- the connection state of the second drive transistor is set such that the source is connected to the second reference node and the drain is connected to the input / output node.
- the supply switching unit sets the connection state of the first drive transistor to a state in which at least one of the source and the drain is not connected, and connects the connection state of the second drive transistor to the source and At least one of the drains is disconnected.
- the voltage applied to the first reference node exhibits positive polarity
- the voltage applied to the second reference node exhibits negative polarity
- the first drive transistor is a P-type transistor, and has a source connected to the first reference node, a drain connected to the input / output node, and a gate.
- the second drive transistor is an N-type transistor, and has a source connected to the second reference node, a drain connected to the input / output node, and a gate.
- the supply switching unit applies a positive voltage to the gate of the first drive transistor and applies a negative voltage to the gate of the second drive transistor in the output mode.
- the supply switching unit applies a negative voltage to the gate of the first drive transistor and a positive voltage to the gate of the second drive transistor in the transition mode.
- the first and second drive transistors are activated, and an output current flows.
- the transition mode the first and second drive transistors are inactivated, and the output current does not flow.
- the fluctuation of the voltage value of the output voltage can be fluctuated at high speed. Also, minutes The allocated charge can be effectively reused, and power consumption can be reduced. Furthermore, since the instantaneous large current does not flow at the output terminal, EMI can be reduced.
- FIG. 1 is a circuit diagram showing a configuration of a display drive circuit according to a first embodiment of the present invention.
- FIG. 2 is a timing chart for explaining the operation of the display drive circuit shown in FIG.
- FIG. 3 is a circuit diagram showing a modification of the display drive circuit shown in FIG.
- FIG. 4 is a circuit diagram showing a configuration of a display drive circuit according to a second embodiment of the present invention.
- FIG. 5 is a circuit diagram showing a modification of the display drive circuit shown in FIG.
- FIG. 6 is a circuit diagram showing a configuration of a display drive circuit according to a third embodiment of the present invention.
- FIG. 7 is a circuit diagram showing a configuration of a display drive circuit according to a fourth embodiment of the present invention.
- FIG. 8 is a circuit diagram showing a modification of the display drive circuit shown in FIG.
- FIGS. 9A, 9B, and 9C are circuit diagrams showing configuration examples of the clamp circuit shown in FIG.
- FIG. 10 is a circuit diagram showing a configuration of a display drive circuit according to a fifth embodiment of the present invention.
- FIG. 11A is a circuit diagram showing a configuration example of the power supply circuit shown in FIG.
- FIG. 11B is a circuit diagram showing a configuration example of the power supply circuit shown in FIG.
- FIG. 12 is a timing chart for explaining an example of on / off operation of each switch.
- FIG. 13 is a circuit diagram showing a configuration of a display driver according to a sixth embodiment of the present invention.
- FIG. 14 is a circuit diagram showing a configuration of a display drive circuit shown in FIG.
- FIG. 15 is a timing chart for illustrating the operation of the display drive circuit shown in FIG.
- 16 is a circuit diagram showing a modification of the display drive circuit shown in FIG.
- FIG. 17 is a circuit diagram showing a configuration of a display drive circuit according to a seventh embodiment of the present invention.
- FIG. 18 is a circuit diagram showing a modification of the display drive circuit shown in FIG.
- FIG. 19 is a circuit diagram showing a configuration of a display driving circuit according to an eighth embodiment of the present invention.
- FIG. 20 is a circuit diagram showing a configuration of a display driver according to a ninth embodiment of the present invention.
- FIG. 21 is a circuit diagram showing a configuration of a display drive circuit shown in FIG.
- FIG. 22 is a timing chart for explaining an example of the on / off operation of each switch.
- FIG. 23 is a circuit diagram showing a modification of the display drive circuit shown in FIG.
- FIG. 24 is a circuit diagram showing a modification of the display driving circuit shown in FIG.
- FIG. 25 is a timing chart for explaining the operation of the conventional display drive circuit.
- FIG. 26 is a timing chart for illustrating the operation of the conventional charge distribution display drive circuit.
- SW12 Human power switch
- SW13a, SW13b Supply switch
- FIG. 1 shows the configuration of a display drive circuit according to a first embodiment of the present invention.
- This circuit includes an input terminal 101, a differential amplification unit 102, phase compensation capacitors C103a and C103b, an output terminal 104, drive transistors T105a and T105b, an output switch SW11, an input switch SW12, and a supply switch. It prepares for SW13a and SW13b and connection switch SW14.
- This circuit drives the vertical line of the display panel, and in the output mode, supplies the output voltage Vout to the vertical line via the output terminal 104 in accordance with the input voltage Vin applied to the input terminal 101. In the transition mode, the voltage value of the input voltage Vin fluctuates.
- Input terminal 101 receives an input voltage Vin.
- the differential amplification unit 102 has input nodes ni l and nl 2 and output nodes nl 3 a and nl 3 b.
- the input node nil is connected to the input terminal 101.
- differential amplification section 102 generates two voltages according to the difference between the voltages applied to each of input nodes nil and nl 2, and outputs one of the voltages from output node nl 3a. Output pressure from output node nl 3 b.
- phase compensation capacitance C103a One end of the phase compensation capacitance C103a is connected to the supply node nl4a connected to the output node nl3a, and the other end is connected to the phase compensation capacitance C103b.
- phase compensation capacitance C103b One end of phase compensation capacitance C103b is connected to supply node nl4b connected to output node nl 3b, and the other end is phase compensation capacitance C It is connected to 103a.
- a connection node (intermediate node) nc between the phase compensation capacitors C103a and C103b is connected to the input node nl 2 of the differential amplification unit 102.
- the output terminal 104 is connected to a vertical line (not shown) of the display panel.
- the drive transistors T105a and T105b are connected in series between the power supply node Vcc and the ground node Vss to constitute an output circuit for generating an idling current (output current).
- the output switch SW11 is connected between a connection node (input / output node of output circuit) nt between the drive transistors T105a and T105b and the output terminal 104.
- the input switch SW12 is connected between the intermediate node nc and the input terminal 101.
- Supply switch SW13a is connected between power supply node Vcc and supply node nl4a.
- Supply switch SW 13 b is connected between supply node nl 4 b and ground node Vss.
- the connection switch SW14 is connected between the intermediate node nc and the node nt of the output circuit.
- each of the switches SW11, SW12, SW13a, SW13b, and SW14 may be turned on / off by, for example, control signals si1, sl2, sl3a, sl3b, sl4 from a control circuit (not shown). It is controlled.
- the differential amplification unit 102 includes a high voltage differential input circuit including a pair of input side transistors 11 la and 112a, a high voltage current mirror circuit including a pair of output side transistors 113a and 114a, and a pair of input side transistors 1
- a low voltage differential input circuit including l ib, 112 b, a low voltage current mirror circuit including a pair of output side transistors 113 b, 114 b, and a high voltage current mirror circuit and a low voltage current mirror circuit And a pair of connection circuits.
- each of the input side transistors 111a and 112a is connected to the ground node Vss via the adjustment transistor 201a.
- the gate of input side transistor 11 la receives the voltage of input node nil (input voltage Vin applied to input terminal 101), and the gate of input side transistor 112a has the voltage of input node nl 2 (voltage Vc at intermediate node nc) Receive
- the gates of the output side transistors 113a and 114a are connected to each other, and the source is connected to the power supply node Vcc.
- a pair of cascode transistors 203a and 204a is cascode connected to the drains of the output side transistors 113a and 114a.
- the output node nl 3a connected to the supply node nl 4a is a drain of the output side transistor 113a. Located between the in and the source of the cascode transistor 203a.
- the source of each of the input side transistors 111 b and 112 b is connected to the power supply node Vcc via the adjustment transistor 201 b.
- the gate of input-side transistor 11 lb receives the voltage of input node nil (input voltage Vin applied to input terminal 101), and the gate of input-side transistor 112b receives the voltage of input node nl2 (voltage Vc at intermediate node nc). receive.
- the gates of the output side transistors 113b and 114b are connected to each other, and the source is connected to the ground node Vss.
- a pair of cascode transistors 203b and 204b is cascode connected to the drains of the output side transistors 113b and 114b.
- An output node nl 3 b connected to the supply node nl 4 b is located between the drain of the output side transistor 113 b and the source of the cascode transistor 203 b.
- connection transistors 115n and 115p are connected in parallel in a force S manner.
- a node nl5a connected to the gate of the drive transistor T105a is located between the drain of the cascode transistor 203a and the drain of the connection transistor 115 ⁇ (the source of 115p).
- the node nl 5 b connected to the gate of the drive transistor Tl 05 b is located in a cascode transistor.
- connection transistors 116 n and 116 p are connected in parallel between the cascode transistors 204 a and 204 b. These connection circuits may be load resistances connected in parallel by transistors.
- FIG. 2 shows how the input voltage Vin input to the input terminal 101, the capacitance voltage Vc at the intermediate node nc, and the output voltage Vout supplied from the output terminal 104 change.
- the display drive circuit 10 is in the “output mode”.
- the output switch SW11 and the connection switch SW14 are on, and the input switch SW12 and the supply switch SW 13a and SW13b are off.
- a voltage (capacitance voltage) Vc having a voltage value corresponding to the input voltage Vin is generated at the intermediate node nc, and from the output terminal 104 according to the capacitance voltage Vc.
- An output voltage Vout having a voltage value (that is, a voltage value corresponding to the input voltage Vin) is output.
- the display drive circuit 10 is in the “transition mode”. In this case, the output switch SW11 and the connection switch SW14 are turned off, and the input switch SW12 and the supply switch SW13a and SWl 3b are turned on. Also, the voltage value of the input voltage Vin fluctuates to a new voltage value.
- supply node nl 4 a is connected to power supply node Vcc, and one end of phase compensation capacitance C 103 a receives a voltage from power supply node Vcc.
- supply node nl 4 b is connected to ground node Vs s, and one end of phase compensation capacitance C 103 b receives a voltage from ground node Vss.
- the intermediate node nc is connected to the input terminal 101, and the phase compensation capacitors C103a and C103b receive the input voltage Vin.
- Each of the phase compensation capacitors C103a and C103b charges and discharges electric charge according to the voltage value of the input voltage Vin.
- the voltage value of the capacitance voltage Vc at the intermediate node nc fluctuates according to the charge / discharge of this charge.
- the charge / discharge speed of charge in phase compensation capacitors C103a and 103b is faster than in the output mode It is. Therefore, the phase compensation capacitances C103a and C103b can quickly store the charge of the charge amount according to the input voltage Vin.
- the voltage value of the capacitive voltage Vc can be quickly changed to the voltage value of the input voltage Vin, and the charge and discharge in the phase compensation capacitors C103a and C103b can be completed during the transition mode.
- the display drive circuit 10 changes from the “transition mode” to the “output mode”.
- the output switch SW11 and the connection switch SW14 are turned on, and the input switch SW12 and the supply switch SW13a and SW13b become active.
- the intermediate node nc is connected to the output terminal 104 via the connection switch SW14, the node nt of the output circuit, and the output switch SW11. Therefore, the voltage Vc at the intermediate node is supplied to the output terminal nt through the output circuit.
- the output voltage Vout is set to the target value after the output mode is entered. Force until reaching the force voltage Vin) Force is shorter than before.
- the fluctuation speed of the voltage value of the output voltage Vo ut depends on the time constant of the output impedance of the display drive circuit 10 and the load capacity of the display (not shown).
- the voltage value of the output voltage can be changed at high speed without increasing the tail current or decreasing the capacitance value of the phase compensation capacitance.
- connection switches SW15a and SW15b are connected in series between the drive transistors T105a and T105b.
- the connection node ns between the connection switches SW15a and SW15b is connected to the intermediate node nc and the output terminal 104.
- Each of the switches SW15a and SW15b is controlled to be turned on / off by, for example, control signals sl5a and sl5b from a control circuit (not shown).
- connection switch SW15a and SW15b The on / off timing of each of the connection switches SW15a and SW15b is the same as that of the connection switch SW14, and the operation by the display drive circuit 10 is also the same as that of FIG. According to this structure, the idling current (current path: Vcc ⁇ T105a ⁇ SW15a ⁇ ns ⁇ SW15b ⁇ T105b ⁇ Vss) flowing through the output circuit can be stopped in the transition mode. Thus, power consumption can be reduced.
- connection switch SW15a is connected between power supply node Vcc and drive transistor T105a, and connection switch SWl 5b is driven.
- the same effect can be obtained by connecting between the transistor T105b and the ground node Vss.
- the connection switch SW15a is connected between the node nl 5a and the gate of the drive transistor T105a
- the connection switch SW15b is connected to the node nl 5b and the gate of the drive transistor T105b.
- the same effect can be obtained by connecting between. That is, in the transition mode, at least one of the source, drain, and gate of the drive transistors T105a and T105b is not connected.
- FIG. 4 shows the configuration of a display drive circuit 20 according to a second embodiment of the present invention.
- This circuit includes a connection switch SW21 instead of the connection switch SW14 shown in FIG.
- the connection switch SW21 is connected between the drain of the cascode transistor 203a and the drain of the connection transistor 115n (the source of the connection transistor 115p).
- the on / off of the switch SW21 is controlled by, for example, a control signal s21 from a control circuit (not shown).
- the on / off timing of the connection switch SW21 is the same as that of the connection switch SW14.
- the intermediate node nc is connected to the output terminal 104 via the node nt of the output circuit.
- the other configuration is the same as in FIG.
- the operation of the display drive circuit 20 shown in FIG. 4 is similar to that of the display drive circuit 10 shown in FIG. Here, the operation related to the connection switch SW21 will be described.
- connection switch SW21 is turned on.
- the drain of the cascode transistor 203a is connected to the drain of the connection transistor 115 ⁇ (the source of the connection transistor 115p). That is, it is connected to the node nl 5 b via the node nl 5 a force S, the switch SW 21, and the connection node transistors 115 n and 115 p.
- current force S flows between node nl5a and node nl5b, and each force of output nodes nl 3a, nl 3b and nodes nl 5a, nl 5b is a voltage according to the difference between input voltage Vin and capacitive voltage Vc Is output.
- the drive transistor T105a , T105b are activated, and an idling current flows in the output circuit (between the drive transistors T105a and T105b).
- connection switch SW21 is turned off.
- the voltage from the power supply node Vcc is supplied to the gate of the drive transistor T105a via the supply switch SW13a, the supply node nl4a, the output node nl 3a, the cascode transistor 203a, and the node nl 5a, so that the drive transistor T105a is not Activate.
- the voltage from the ground node Vss is supplied to the gate of the drive transistor T105b through the supply switch SW13b, the supply node nl4b, the output node nl3b, the cascode transistor 203b, and the node nl 5b, so the drive transistor T105b is Deactivate. Therefore, no idling current flows in the output circuit.
- the voltage value of the output voltage can be changed at high speed, and power consumption can be reduced. Further, as compared with the display drive circuit 10 shown in FIG. 3, the number of switches is small, so that the circuit scale can be reduced.
- connection switch SW21 between the source of the connection transistor 115 ⁇ (the drain of the connection transistor 115115) and the drain of the cascode transistor 203b.
- connection transistor SW22n is connected to the drain of the cascode transistor 203a and the connection transistor 115. It is connected between n and the drain.
- the connection transistor SW22p is connected between the drain of the cascode transistor 203a and the source of the connection transistor 115p.
- Each of the switches SW22n and SW22p is controlled to be on / off by, for example, control signals s22n and s22p from a control circuit (not shown).
- the on-Z timing of each of the connection transistors SW22n and SW22p is the same as that of the switch SW21.
- connection transistors 115 ⁇ and 115 ⁇ can be made equal to that in the case where the connection transistors SW22 n and SW2 2 p are not connected (for example, in the case of FIG. 1). . Thereby, the deviation of the operating point of the differential amplification unit 102 can be suppressed.
- FIG. 6 shows the configuration of a display drive circuit 30 according to a third embodiment of the present invention.
- this circuit 30 includes cutoff switches SW31 a and SW31 b.
- the blocking switch SW31a is connected between the output node nl 3a and the supply node nl 4a.
- the blocking switch SW3 lb is connected between the output node nl3 b and the supply node nl 4 b.
- the on / off of each of the shutoff switches SW31a and SW31b is controlled by, for example, control signals s31a and s31b from a control circuit (not shown).
- the on / off timing of each of the shutoff switches SW31a and SW31b is the same as that of the output switch SW11.
- the operation of the display drive circuit 30 shown in FIG. 6 is similar to that of the display drive circuit 10 shown in FIG. Here, the operation related to the shutoff switches SW31a and SW31b will be described.
- the shutoff switches SW31a and SW31b are turned on. Also, the supply switch SW13a and SW13b are turned off.
- Supply node nl 4 a is connected to output node nl 3 a without being connected to power supply node Vcc.
- supply node nl 4 b is connected to output node nl 3 b without being connected to ground node Vss.
- the shutoff switches SW31a and SW31b are turned off. Also, the supply switch SW13a and SW13b are turned on.
- Supply node nl 4 a is connected not to output node nl 3 a but to power supply node Vcc.
- supply node nl 4 b is connected to output node nl 3 b without being connected to ground node Vss. Therefore, a through current (current path: Vcc ⁇ nl4a ⁇ nl 3a ⁇ l lla ⁇ 201a ⁇ Vdd) does not flow between the supply node nl 4a and the output node nl 3a.
- a through current flows between the output node nl 3 b and the supply node nl 4 b.
- no through current (current path: Vcc ⁇ SW 13a ⁇ nl 4a ⁇ nl 3a ⁇ 2 03a ⁇ 15n ⁇ 203b ⁇ nl 3b ⁇ nl 4b ⁇ SWl 3b ⁇ Vss) between node nl 5a and node nl 5b Leh.
- the through current can be cut off in the transition mode.
- the voltage value of the output voltage can be changed at high speed, and power consumption can be reduced.
- the cutoff switches SW31a and SW31b can also be applied to the display drive circuit shown in FIG.
- FIG. 7 shows the configuration of a display drive circuit 40 according to a fourth embodiment of the present invention.
- This circuit 40 includes current limiting transistors T401a and T401b in addition to the display drive circuit 10 shown in FIG.
- the current limiting transistor T401a is connected between the power supply node Vcc and the source of the driving transistor T105a.
- the current limiting transistor T401b is connected between the source of the driving transistor T105b and the ground node Vss.
- the voltage value of the output voltage can be changed at high speed, and the output voltage The amount of current flow can be adjusted. For example, if the maximum value of the output current is "IMAX” and the load capacity of the display panel is "CL", the slew rate is "IMAX / CL". In this way, the rise speed or fall speed of the display drive circuit can be controlled, and the drive capability can be adjusted according to the characteristics of the display panel.
- the same effect can be obtained even if the display drive circuit 40 includes clamp circuits 402a and 402b instead of the current limit transistors T401a and T401b.
- the clamp circuit 402a limits the voltage value of the voltage VGP applied to the gate of the drive transistor T105a.
- the clamp circuit 402b limits the voltage value of the voltage VGN applied to the gate of the drive transistor T105b.
- each of the clamp circuits 402a and 402b shown in FIG. 8 can be configured by a plurality of diodes 411 connected in series.
- each of the clamp circuits 402a and 402b may be composed of a plurality of diode-connected transistors 412a and 412b connected in series.
- each of the clamp circuits 402a and 402b may be formed by the transistors 413a and 413b whose gates are applied with predetermined voltages BN and BP, respectively.
- the current limiting transistors T40 la and T401 b shown in FIG. 7 and the clamp circuits 402 a and 402 b shown in FIG. 8 are also applicable to the display drive circuits shown in FIGS. 3, 4, 5 and 6. Applicable.
- FIG. 10 shows the configuration of a display drive circuit 50 according to a fifth embodiment of the present invention.
- This circuit 50 includes a node na receiving a stable voltage VH and a node nb receiving a stable voltage VL, instead of the power supply node Vcc connected to the supply switch SW13a shown in FIG. 1 and the ground node Vss connected to the supply switch SW13b. .
- the other configuration is the same as in FIG.
- the voltage value of stable voltage VH is equal to the voltage value of the voltage of supply node nl 4 a in the output mode (when supply switch SW 13 a is off).
- the voltage value of the stable voltage VL is equal to the voltage value of the node nl4b in the output mode (when the supply switch SW13b is off).
- Each of the stable voltages VH and VL is generated by the power supply circuit 501.
- the power supply circuit 501 may be a ladder resistor connected between the power supply node Vcc and the ground node Vss.
- the output of tap 501a of the ladder resistor is supplied as a stable voltage V H.
- the output of tap 501b of the ladder resistor is output as a stable voltage VL.
- the power supply circuit 501 includes an input terminal 101, a differential amplification unit 102, phase compensation capacitors C103a and C103b, drive transistors T105a and T105b, and a voltage follower circuit 511a, Good, even in the configuration with 511b.
- the intermediate node nc is connected to the node nt of the output circuit.
- Supply node nl 4 a is connected to voltage follower circuit 51 la.
- Supply node nl 4 b is connected to voltage follower circuit 51 lb.
- a voltage having a voltage value “VCC / 2 (VCC is a voltage value of the voltage at power supply node Vcc)” is applied to input terminal 101.
- the output of the voltage follower circuit 511a is supplied as a stable voltage VH.
- the output of the voltage follower circuit 511b is supplied as a stable voltage VL.
- the operation of the display drive circuit 50 shown in FIG. 10 is similar to that of the display drive circuit 10 shown in FIG. Here, an operation related to the power supply circuit 501 will be described.
- the voltage value at the supply node nl4a in output mode is slightly lower than the voltage value at the power supply node Vcc.
- the voltage at the supply node nl4b is slightly larger than the voltage at the ground node Vss. Therefore, the power supply no
- the supply node nl 4 a is charged and discharged due to the deviation of the voltage value. The same phenomenon occurs at the supply node nl 4 b.
- the supply switch SW13a in the transition mode, the supply switch SW13a is turned on, and one end of the phase compensation capacitance C103a is connected to the node na to which the stable voltage VH is supplied. Thereby, the voltage fluctuation of supply node nl 4a in the output mode is suppressed. Further, the supply switch SW13b is turned on, and one end of the phase compensation capacitance C103b is connected to the node nb to which the stable voltage VL is supplied. Thereby, the voltage fluctuation of the supply node n 14a in the output mode is suppressed.
- phase compensation capacitance C103a and at one end of C103b which occur when transition mode is changed to output mode are suppressed, and therefore the phase caused by voltage fluctuations at nodes nl4a and nl4b. It is possible to suppress charge / discharge of charges in the compensation capacitors C103a and C103b.
- the voltage value of the output voltage can be changed at a higher speed.
- Power supply circuit 501 is also applicable to the display drive circuit shown in FIGS. 3, 4, 5, 6, 7, and 8.
- each switch may be turned on / off as shown in FIG.
- the input switch SW12 and the supply switches SW13a and SW13b are turned off from on before the output switch SW11 is also turned on. That is, one end of the phase compensation capacitance C103a is connected to the power supply node Vcc (or node na) before the intermediate node (connection node between the phase compensation capacitances C103a and C103b) is connected to the output terminal 104 in the output mode.
- phase compensation capacitance C103b is separated from the ground node Vs s (or node nb), and the input terminal 101 is separated from the intermediate node nc.
- voltage fluctuation at one end (supply node nl4a) of phase compensation capacitance C103a and one end (supply node nl4b) of C103b is calculated. It can be suppressed, and the fluctuation of the output voltage can be made faster.
- FIG. 13 shows the configuration of a display driver according to the sixth embodiment of the present invention.
- This driver includes 2n (n is a natural number) display drive circuits 60 and (2n_l) distribution switches SW60.
- the display driver drives the display panel by supplying different output voltages to the odd-numbered vertical lines and the even-numbered vertical lines (for example, a dot inversion driving method or a frame inversion driving method).
- Each of 2n display drive circuits 60 receives an input voltage different in polarity from an input voltage applied to display drive circuit 60 adjacent to display drive circuit 60. That is, when the input voltages Vin (l), Vin (3),..., Vin (2 n-1) applied to the odd-numbered display drive circuits are S “negative”, the even-numbered display The polarity of the input voltages Vin (2), Vin (4),..., Vin (2n) applied to the dynamic circuit 60 is "positive electrode 10 life".
- each of the 2n display drive circuits 60 has an output voltage Vout (l), according to a given input voltage Vin (1), Vin (2),..., Vin (2n).
- Vout (2) ⁇ ⁇ ⁇ ⁇ Outputs Vout (2n).
- the output voltage Vout (2n-1) supplied from the odd-numbered display drive circuit 60 has a polarity S of "negative polarity”
- the output voltage Vout (2n) supplied from the even-numbered display drive circuit 60 Is “positive polarity”.
- Each of the 2n input voltages Vin (1), Vin (2), ⁇ , Vin (2 n) reverses their polarity in accordance with a predetermined timing.
- the polarity of 2n input voltages is inverted every one horizontal line period.
- it is assumed that the polarity of the input voltage is reversed in the transition mode.
- the distribution switch SW60 is connected between the output terminals of two display drive circuits 60 adjacent to each other. Distribution switch SW60 turns off in output mode and transitions Turn it on. That is, the distribution switch SW60 is turned on when the polarity of each of the input voltages Vin (1), Vin (2),..., Vin (2n) is inverted.
- the output terminal of the second display drive circuit 60 and its own output terminal are disconnected, while the output voltage of the first display drive circuit 60 is in accordance with the input voltage Vin (1).
- Output voltage Vout (l) In the first display drive circuit 60, its output terminal and the output terminal of the second display drive circuit are connected in the transition mode, while the polarity of the applied input voltage Vin (1) is inverted.
- FIG. 14 shows the configuration of the display drive circuit 60 shown in FIG.
- the input voltage is referred to as “Vin capacitance voltage” and “Vc output voltage is referred to as“ Vout ”.
- the circuit 60 includes a connection switch SW61 in place of the input switch SW11 shown in FIG.
- the connection switch SW61 is connected between the intermediate node nc and the output terminal 104.
- the on / off of the connection switch SW61 is controlled by, for example, a control signal s61 from a control circuit (not shown).
- the on / off timing of the connection switch SW61 is the same as that of the input switch SW12 shown in FIG.
- FIG. 15 shows changes in the input voltage Vin (2n-1), the capacitance voltage Vc (2n-1), and the output voltage Vout (2n-1) in the (2n-l) th display drive circuit.
- the changes in the input voltage Vin (2 ⁇ ), the capacitive voltage Vc (2n), and the output voltage Vout (2n) in the (2n) th display drive circuit are shown.
- the display drive circuit 60 is in the “output mode”.
- the output switch SW61 and the connection switch SW14 are on, and the connection switch SW61 and the supply switch SW 13a and SW13b are off.
- a voltage (capacitance voltage) Vc having a voltage value according to the input voltage Vin is generated at the intermediate node nc, and the output terminal 104 outputs an output voltage Vout having a voltage value according to the input voltage Vin.
- the input voltage Vin (2n-1) and the output voltage Vout (2n_l) are positive polarity, and the input voltage Vin (2n) and the output voltage Vou t (2n) is negative.
- the display drive circuit 60 is in the “transition mode”.
- the distribution switch SW60 is turned on, and the output terminals of each of the 2n display drive circuits 60 are connected to each other to distribute the charge accumulated at each output terminal.
- the output terminal 104 of the (2n_l) th display drive circuit is discharged, and the voltage value of the output voltage Vout (2n_l) falls to an intermediate value.
- the output terminal 104 of the (2n) th display drive circuit is charged, and the voltage value of the output voltage Vout (2n) rises to an intermediate value.
- the voltage value of each output voltage is an intermediate value.
- the output switch SW11 and the connection switch SW14 are turned off, and the connection switch SW61 and the supply switches SW13a and SW13b are turned on. Further, a new input voltage Vin whose polarity is inverted is applied to the input terminal 101.
- the input voltage Vin (2n-1) is negative, and the input voltage Vin (2n) is positive.
- supply node nl 4 a is connected to power supply node Vcc, and one end of phase compensation capacitance C 103 a receives a voltage from power supply node Vcc.
- the supply node nl 4b is connected to the power S ground node Vs s, and one end of the phase compensation capacitance C 103b receives the voltage from the ground node Vss.
- the intermediate node nc is connected to the output terminal 104, and the phase compensation capacitances C103a and C103b receive the output voltage Vout (intermediate value) of the output terminal 104.
- Each of phase compensation capacitances C103a and C103b charges and discharges charges according to the voltage value of the output voltage Vout.
- the voltage value of the capacitance voltage Vc at the intermediate node nc fluctuates according to the charge / discharge of this charge.
- the charge / discharge speed of charges in the phase compensation capacitances C103a and 103b is faster than that in the output mode. Therefore, the movement of charge between intermediate node nc and output terminal 104 can be made quick. That is, the voltage value of the capacitive voltage Vc can be rapidly changed to the voltage value (intermediate value) of the output voltage Vout. Further, since the intermediate node nc and the output terminal 104 are connected, the voltage value of the capacitive voltage Vc and the voltage value of the output voltage Vout are Become equal.
- the display drive circuit 10 changes from the “transition mode” to the “output mode”.
- the output switch SW11 and the connection switch SW14 are turned on, and the connection switch SW61 and the supply switch SW13a and SW13b become active.
- the intermediate node nc is connected to the output terminal 104 via the connection switch SW14, the node nt of the output circuit, and the output switch SW11.
- the voltage value of the output voltage Vout of the output terminal 104 is equal to the voltage value of the capacitance voltage Vc at the intermediate node nc, charging / discharging of the output terminal 104 occurs due to the voltage difference between the output voltage Vout and the capacitance voltage Vc. Absent. Therefore, the voltage value of the output voltage Vout varies from the voltage value of the intermediate voltage to the target value according to the operation speed of the display drive circuit.
- the voltage value of the output voltage Vout (2n_l) drops from the “middle value” to the “target value (2n_l)", and the voltage value of the output voltage Vout (2n) changes from the “middle value” Increase to the target value (2n).
- the intermediate node nc and the output terminal 104 are connected to change the voltage value of capacitance voltage Vc to an intermediate value at a high speed, whereby the voltage value of output voltage Vout becomes the target value.
- the time to reach can be shortened.
- the voltage value of the output voltage can be changed at high speed without increasing the tail current or decreasing the capacitance value of the phase compensation capacitance.
- connection switch SW15a and SW15b shown in FIG. 3 instead of the connection switch SW61 shown in FIG.
- the connection switch SW15a is connected between the power supply node Vcc and the drive transistor T105a
- the connection switch SW15b is between the drive transistor T105b and the ground node Vss. Similar effects can be obtained by connecting.
- the connection switch SW15a is connected between the node nl 5a and the gate of the drive transistor T105a
- the connection switch SW15b is connected between the node nl5b and the gate of the drive transistor T105b. Even if you get the same effect, you can S. That is, in the transition mode, at least one of the source, the drain, and the gate may be in a non-connection state in the connection state of the drive transistors T105a and T105b.
- FIG. 17 shows a configuration of a display drive circuit 70 according to a seventh embodiment of the present invention.
- the circuit 70 includes the connection switch SW21 shown in FIG. 4 in place of the output switch SW11 and the connection switches SW14 and SW61 shown in FIG.
- the other configuration is the same as in FIG.
- the operation of the display drive circuit 70 shown in FIG. 17 is similar to that of the display drive circuit 60 shown in FIG.
- the operation related to the connection switch SW21 is also the same as in the case of FIG.
- connection switch SW21 is turned on, and each of the drive transistors T105a and T105b is activated, so an idling current flows in the output circuit.
- connection switch SW21 is turned off, and each of the drive transistors T105a and T105b is inactivated, so that no idling current flows in the output circuit.
- the voltage value of the output voltage can be changed at high speed, and power consumption can be reduced.
- 14 and 16 and the display drive circuit 10 shown in FIG. In comparison, since the number of switches is small, the circuit scale can be reduced.
- the same effect can be obtained even when the display drive circuit 70 includes the connection transistors SW22n and SW22p shown in FIG. 5 instead of the connection switch SW21.
- the voltage between the source and the gate of each of the connection transistors 115n and 115p is not connected when the connection transistors SW22n and SW22p are connected (for example, in the case of FIG. 14). And can be equal. Thereby, the shift of the operating point of the differential amplification unit 102 can be suppressed.
- FIG. 19 shows the configuration of a display drive circuit 80 according to an eighth embodiment of the present invention.
- This circuit 80 includes the switches SW31a and SW31b shown in FIG. 6 in addition to the display drive circuit 60 shown in FIG.
- the operation of the display drive circuit 80 shown in FIG. 19 is similar to that of the display drive circuit 60 shown in FIG. Further, the operation related to the switches SW31a and SW31b is also the same as in the case of FIG.
- the switches SW31a and SW31b are turned on. Also, the supply switch SW13a and SW13b are turned on. Thereby, the phase compensation capacitance C103a receives the voltage of the output node nl 3a force, and the phase compensation capacitance C103b receives the voltage from the output node nl 3b.
- the switches SW31a and SW31b are turned off. Also, the supply switch SW13a and SW13b are turned on. As a result, no through current flows between node nl 4 a and output node nl 3 a and between output node nl 3 b and node nl 4 b.
- the switches SW31a and SW31b are the devices shown in FIG. It is applicable also to a play drive circuit.
- FIG. 20 shows a configuration of a display driver according to a ninth embodiment of the present invention.
- This driver includes 2n display drive circuits 90 instead of 2n display drive circuits 60 shown in FIG. 13, and further includes a power supply circuit 501 shown in FIG.
- the other configuration is the same as in FIG.
- Each of display drive circuits 90 receives stable voltages VH and VL from power supply circuit 501.
- FIG. 21 shows the configuration of the display drive circuit 90 shown in FIG.
- This circuit 90 includes nodes na and nb shown in FIG. 10 in place of the power supply node Vcc connected to the supply switch SW13a shown in FIG. 16 and the third ground node Vss connected to the supply switch SW13b.
- the other configuration is the same as in FIG.
- the operation of the display drive circuit 90 shown in FIG. 21 is similar to that of the display drive circuit 60 shown in FIG. Also, the operation related to the power supply circuit 501 is the same as in FIG.
- stable voltage VH from node na is supplied to supply node nl 4 a, whereby the voltage fluctuation at supply node nl 4 a is suppressed when transitioning from the transition mode to the output mode.
- stable voltage VL from the node nb is supplied to the supply node nl 4 b, whereby the voltage fluctuation at the supply node nl 4 b is suppressed when transitioning from the transition mode to the output mode.
- the power supply circuit 501 can also be applied to the display drive circuit shown in FIGS. 14, 17, 18 and 19. (Time of on / off)
- each switch may be turned on / off as shown in FIG.
- the connection switch SW61 and the supply switches SW13a and SW13b are turned off from on before the distribution switch SW60 is turned on. That is, before charge redistribution by distribution switch SW60 ends, one end of phase compensation capacitance C103a is separated by power supply node Vcc (or node na), and one end of phase compensation capacitance C103b is grounded node Vss Disconnect from node nb).
- the differential amplifier unit 102 of the display drive circuit has two inputs and two outputs, but the same effect can be obtained even if it is a two-input one-output differential amplifier. You can get it.
- a display drive circuit 10A power input terminal 101, a 2-input 1-output differential amplification unit 102A, one phase compensation capacitance C103b, an output terminal 104, drive transistors T105a and T105b, Even if it has the output switch SWl l, the input switch SW12, one supply switch SW13b, and the connection switch SW14. Further, as shown in FIG.
- the display drive circuit 60A includes an input terminal 101, a 2-input 1-output differential amplification unit 102A, one phase compensation capacitance C103b, an output terminal 104, and a drive transistor T105 a, Even if it is equipped with T105b, output switch SWl l, one supply switch SW13b, and connection switch SW14, SW61.
- T105b input terminal 101
- PM S S transistor configured of an NMOS transistor.
- each switch may be any of a PMOS transistor, an NMOS transistor, and a CMOS transfer gate.
- a constant current source may be connected to one end of supply switch SW13a instead of power supply node Vcc, and a constant current source may be connected to one end of supply switch SW13b instead of ground node Vss. It is good.
- constant current sources capable of switching between the drive state and the stop state may be connected to the nodes nl4a and nl4b. In this case, these constant current sources are stopped in the output mode and driven in the transition mode.
- the present invention can change the voltage value of the output voltage at high speed, and is thus useful as a display drive circuit or the like for driving a display panel of a liquid crystal panel.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/886,432 US7928953B2 (en) | 2005-03-29 | 2006-03-20 | Display driver circuit |
JP2007510404A JP4927712B2 (ja) | 2005-03-29 | 2006-03-20 | ディスプレイ駆動回路 |
US13/046,173 US8514164B2 (en) | 2005-03-29 | 2011-03-11 | Display driver circuit |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2005-336563 | 2005-03-29 | ||
JP2005-094251 | 2005-03-29 | ||
JP2005094251 | 2005-03-29 | ||
JP2005336563 | 2005-11-22 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US11/886,432 A-371-Of-International US7928953B2 (en) | 2005-03-29 | 2006-03-20 | Display driver circuit |
US13/046,173 Division US8514164B2 (en) | 2005-03-29 | 2011-03-11 | Display driver circuit |
Publications (1)
Publication Number | Publication Date |
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WO2006103977A1 true WO2006103977A1 (ja) | 2006-10-05 |
Family
ID=37053238
Family Applications (1)
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PCT/JP2006/305576 WO2006103977A1 (ja) | 2005-03-29 | 2006-03-20 | ディスプレイ駆動回路 |
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US (2) | US7928953B2 (ja) |
JP (1) | JP4927712B2 (ja) |
WO (1) | WO2006103977A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008244984A (ja) * | 2007-03-28 | 2008-10-09 | Fuji Electric Device Technology Co Ltd | カレントミラー回路 |
JP2010021911A (ja) * | 2008-07-14 | 2010-01-28 | Nec Electronics Corp | 演算増幅器 |
JP2011171975A (ja) * | 2010-02-18 | 2011-09-01 | Renesas Electronics Corp | 出力回路及びデータドライバ及び表示装置 |
JP2015159530A (ja) * | 2014-01-21 | 2015-09-03 | セイコーインスツル株式会社 | 増幅回路 |
CN111081183A (zh) * | 2019-12-19 | 2020-04-28 | 武汉华星光电技术有限公司 | Goa器件及显示面板 |
JP7498554B2 (ja) | 2018-12-04 | 2024-06-12 | シナプティクス インコーポレイテッド | システム、及び、方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP5532301B2 (ja) * | 2009-12-25 | 2014-06-25 | ソニー株式会社 | 駆動回路および表示装置 |
US10263579B2 (en) * | 2016-10-28 | 2019-04-16 | Hewlett Packard Enterprise Development Lp | Differential amplifier |
IT201700021364A1 (it) | 2017-02-24 | 2018-08-24 | St Microelectronics Srl | Amplificatore operazionale, circuito, apparecchiatura e procedimento corrispondenti |
US10730073B2 (en) | 2017-02-24 | 2020-08-04 | Stmicroelectronics S.R.L. | Electronic circuit, corresponding ultrasound apparatus and method |
IT201700021392A1 (it) | 2017-02-24 | 2018-08-24 | St Microelectronics Srl | Circuito di pilotaggio, apparecchiatura ad ultrasuoni e procedimento corrispondenti |
US11011970B2 (en) * | 2017-12-12 | 2021-05-18 | Rohm Co., Ltd. | Gate drive circuit |
WO2019116825A1 (ja) | 2017-12-12 | 2019-06-20 | ローム株式会社 | ゲート駆動回路 |
US10622994B2 (en) * | 2018-06-07 | 2020-04-14 | Vishay-Siliconix, LLC | Devices and methods for driving a semiconductor switching device |
US10608630B1 (en) * | 2018-06-26 | 2020-03-31 | Xilinx, Inc. | Method of increased supply rejection on single-ended complementary metal-oxide-semiconductor (CMOS) switches |
JP7316034B2 (ja) * | 2018-11-14 | 2023-07-27 | ローム株式会社 | ドライバ回路 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000165161A (ja) * | 1998-11-24 | 2000-06-16 | Matsushita Electric Ind Co Ltd | 差動増幅回路 |
JP2001156559A (ja) * | 1999-09-17 | 2001-06-08 | Matsushita Electric Ind Co Ltd | 高スルーレート差動増幅回路 |
JP2006094534A (ja) * | 2004-09-24 | 2006-04-06 | Samsung Electronics Co Ltd | スルーレートの改善のための差動増幅器回路及び方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2977047B2 (ja) | 1995-06-09 | 1999-11-10 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | 液晶表示パネル駆動装置 |
JP3586998B2 (ja) | 1996-10-31 | 2004-11-10 | ソニー株式会社 | 液晶ディスプレイの駆動装置 |
JP3063670B2 (ja) | 1997-04-25 | 2000-07-12 | 日本電気株式会社 | マトリクス表示装置 |
JP3228411B2 (ja) | 1998-03-16 | 2001-11-12 | 日本電気株式会社 | 液晶表示装置の駆動回路 |
KR100292405B1 (ko) * | 1998-04-13 | 2001-06-01 | 윤종용 | 오프셋 제거 기능을 갖는 박막트랜지스터 액정표시장치 소스드라이버 |
JP2000039870A (ja) | 1998-07-23 | 2000-02-08 | Sony Corp | 液晶表示装置 |
JP2000221932A (ja) | 1999-02-02 | 2000-08-11 | Matsushita Electric Ind Co Ltd | 液晶表示装置およびその駆動方法 |
JP3478989B2 (ja) | 1999-04-05 | 2003-12-15 | Necエレクトロニクス株式会社 | 出力回路 |
JP2002014658A (ja) | 2000-06-29 | 2002-01-18 | Nec Kansai Ltd | 液晶駆動用集積回路素子 |
KR100438784B1 (ko) | 2002-01-30 | 2004-07-05 | 삼성전자주식회사 | 박막 트랜지스터형 액정 표시 장치의 소스 드라이버의출력 회로 |
KR100674912B1 (ko) * | 2004-09-24 | 2007-01-26 | 삼성전자주식회사 | 슬루 레이트(slew rate)를 개선시킨 차동 증폭회로 |
JP2006208653A (ja) * | 2005-01-27 | 2006-08-10 | Mitsubishi Electric Corp | 表示装置 |
-
2006
- 2006-03-20 US US11/886,432 patent/US7928953B2/en not_active Expired - Fee Related
- 2006-03-20 WO PCT/JP2006/305576 patent/WO2006103977A1/ja active Application Filing
- 2006-03-20 JP JP2007510404A patent/JP4927712B2/ja not_active Expired - Fee Related
-
2011
- 2011-03-11 US US13/046,173 patent/US8514164B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000165161A (ja) * | 1998-11-24 | 2000-06-16 | Matsushita Electric Ind Co Ltd | 差動増幅回路 |
JP2001156559A (ja) * | 1999-09-17 | 2001-06-08 | Matsushita Electric Ind Co Ltd | 高スルーレート差動増幅回路 |
JP2006094534A (ja) * | 2004-09-24 | 2006-04-06 | Samsung Electronics Co Ltd | スルーレートの改善のための差動増幅器回路及び方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008244984A (ja) * | 2007-03-28 | 2008-10-09 | Fuji Electric Device Technology Co Ltd | カレントミラー回路 |
JP2010021911A (ja) * | 2008-07-14 | 2010-01-28 | Nec Electronics Corp | 演算増幅器 |
JP2011171975A (ja) * | 2010-02-18 | 2011-09-01 | Renesas Electronics Corp | 出力回路及びデータドライバ及び表示装置 |
US8686987B2 (en) | 2010-02-18 | 2014-04-01 | Renesas Electronics Corporation | Output circuit, data driver and display device |
JP2015159530A (ja) * | 2014-01-21 | 2015-09-03 | セイコーインスツル株式会社 | 増幅回路 |
JP7498554B2 (ja) | 2018-12-04 | 2024-06-12 | シナプティクス インコーポレイテッド | システム、及び、方法 |
CN111081183A (zh) * | 2019-12-19 | 2020-04-28 | 武汉华星光电技术有限公司 | Goa器件及显示面板 |
Also Published As
Publication number | Publication date |
---|---|
US8514164B2 (en) | 2013-08-20 |
US20110157146A1 (en) | 2011-06-30 |
US7928953B2 (en) | 2011-04-19 |
JP4927712B2 (ja) | 2012-05-09 |
US20080150858A1 (en) | 2008-06-26 |
JPWO2006103977A1 (ja) | 2008-09-04 |
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