TW526465B - Display apparatus, digital/analog converting circuit and digital/analog converting method - Google Patents

Abstract

The invented signal line driving circuit comprises the followings: a latch-up circuit, which latches digital pixel data; a D/A converter for converting the latching output of the latch-up circuit into an analog image signal; an AMP17 for amplifying analog image signal converted by the D/A converter; and a signal line selection circuit 18 for selecting the signal line to which the analog image signal amplified by AMP17 is supplied. The AMP17 comprises the followings: odd-number longitudinally-connected inverters IV1 to IV3; capacitor devices C4 and C5, which are individually connected in between the sections of the inverters, and between the input terminal of the initial section inverter and the output terminal of the final section inverter; a first power supply line XAVDD1 for supplying power source voltage to the initial section inverter IV1; and a second power supply line XAVDD2 for supplying power source voltage to the inverter except the initial section inverter. By only separating the power supply lines of the initial section inverter, the precision of AMP17 can be increased.

Description

V. Description of the Invention (i): The application is based on Japanese Patent Application No. 2001-148175 filed on May 17th, which was filed on April 27th, Japanese Patent Application No. 2001-148175 The claim of π τ and the Japanese Patent Application No. Hori, filed on December 28, 2001, are based on and claim the benefit, and the entire contents of these applications are incorporated herein by reference. ', The invention of this invention is related to the conversion of digital pixel data into analog image signals = converters, amplifiers and signal line selection circuits that amplify the output of D / A converters, and image queues and bodies formed on insulating substrates. A display device, a digital analog conversion circuit for converting a digital signal into an analog signal, and a digital analog conversion method. 〆 Related Background Art The development and popularization of liquid crystal display devices in which a pixel array unit and a driving circuit are formed on the same glass substrate. By forming the pixel array portion and the driving circuit on the same glass substrate, the entire liquid crystal display device can be made thinner and lighter, and can be widely used in display devices for portable devices such as mobile phones and notebook computers. Λ. This type of liquid crystal display device with integrated drive circuit is formed on the glass substrate with T F T and silicon on the glass substrate, and uses these thin film transistors (T F τ) to simultaneously form a pixel array portion and a drive circuit. However, since the operation speed of the iTFT formed on the glass substrate is not fast, it is necessary to pay attention to various circuit practices when constructing the driving circuit. This 526465 V. Description of the Invention (In addition, it is currently technically difficult to form TFTs with uniform characteristics on a glass substrate. 'Due to the differences in TFT characteristics, display quality such as unstable display may be reduced. Furthermore, the pixel array When the portion and the driving circuit are formed on the same glass substrate, the problem that the area ratio of the pixel array portion to the area of the broken glass substrate is relatively small and the margin is large. Figure 47 shows the use of polycrystalline silicon TFTs on the glass substrate. The circuit diagram of the previously formed digital analog converter (DAC) is disclosed in Japanese Patent Application Laid-Open No. 10-340072. The DAC in Figure 7 responds to the value of each bit of the digital signal, and connects the -square of switches SW21 and SW22 Through this, the node a forms a reference voltage u or a ground voltage. Since the switch SW23 is turned off at first, the charge stored in the capacitor = element C21 is redistributed to the capacitor element C22. The above process is repeatedly performed by several bits. At the end of this process, switches SW24, SW25 are turned off, switch sw%, and SW27 are turned on. As a result, the voltage at node B is transmitted to the output of the amplifier and stored in the capacitor in the negative feedback loop The bias voltage in the device element C23 is reduced at the same time. By the above processing, the voltage after the D / A conversion is output from the amplifier. After the D / A conversion processing is completed, the switch SW28 is turned on and the signal line writing is performed. Because the DAC in Figure 47 performs the redistribution of stored blood in the digital signals, the D / A conversion takes time, and the nesting time of the signal line is shortened. / As a result, the 仏 line may not be able to increase or decrease the required voltage In addition, the display quality is deteriorated due to instability of photo. ^ In addition, because of the need for Figure 47iDAc and its subsequent paragraphs on each signal line, the paper size is suitable for financial @ S 家 标准 (CNS) A4 specifications (X 297 公 526465 Description of the invention (Small forehead ruler: this consumption "plus" and the circuit occupied area becomes larger "cannot be reduced. The purpose of the present invention is to provide a display device that can improve the display quality. In addition, other purposes of the present invention, ^ f τ, display device In addition to providing a display capable of reducing the margin, the other purpose of the present invention is to convert the digital time required for conversion. 供 Supply-a type that can shorten the digital analog M ^ digital conversion conversion circuit, display device and digital class. Ratio conversion method. 'Another object of the present invention is to provide a digital period for performing digital analog conversion processing <period and outputting digital analog conversion results for a period: repeating' digits that lengthen the period during which digital analog conversion results are output. Analog conversion circuit, display device and digital analog conversion method. In order to achieve the above-mentioned object, the display device of the present invention includes: a signal line and a scan line, which are arranged vertically and horizontally on an insulating substrate; and a display element, which is formed on the foregoing Near each intersection of the signal line and the scanning line; * a scanning line driving circuit that drives the aforementioned scanning line; and a signal line driving circuit that drives the aforementioned signal line formed on the aforementioned insulating substrate; and the aforementioned signal line driving circuit Including: an amplifier for amplifying an analog video signal; and a signal line selection circuit for selecting an analog amplified by the aforementioned amplifier

526465

The signal line of the object to which the f signal is supplied; the amplifier includes:, an odd number of inverters are connected to;, and a private container element, which are respectively connected between the segments of the inverter, and Between the input terminal of the commutator and the output terminal of the aforementioned inverter in the last stage; the first power supply line which supplies the power voltage to the aforementioned inverter in the first stage; and the first power supply line which supplies the power voltage to The aforementioned inverters other than the initial stage. In addition, the display device includes: a bluff line and a scan line, which are arranged vertically and horizontally on an insulating substrate; a display element, which is formed near each intersection of the aforementioned signal line and the scan line; '' a scan line driving circuit, which is Driving the scanning line; and a signal line driving circuit that drives the signal line formed on the insulating substrate; and the signal line driving circuit includes: an amplifier that amplifies an analog video signal; and a signal line selection circuit that is Select the signal line of the analog video signal supply object amplified by the amplifier; the signal line selection circuit has a plurality of analog switches connected in parallel on each signal line; the foregoing analog switches corresponding to the same signal line are controlled at the same- 8-

526465

Turn on and off in the direction. In addition, the display device includes: 4 Lu lines and scan lines, which are arranged vertically and horizontally on an insulating substrate; display elements, which are opened ^ + I, ,, and nearby # ^; as described in the 仏 line and scan lines Each cross-point analog switch has a Bristol, λ, and %% on the aforementioned insulating substrate; and an analog switch for penetration compensation, which is connected in series to at least a part of the analog switches, and is recognized. Exciting — ,,, &lt; magic k each two w, corresponding analog switches are turned on and off in the opposite direction, the aforementioned penetration compensation analogue switch ^ ㉙ ratio switch includes a parallel pMOS transistor a nMOS transistor, Rain two p minus, t t 日 日 〆 〆 两, two% of the crystal foot source, short-circuit between the drain. In addition, the display device includes: a signal line and a scanning line 'which are arranged on an insulating substrate in a vertical and horizontal arrangement; a display element' which is formed near each intersection of the aforementioned signal line and the scanning line; a scanning line driving circuit which drives the foregoing Scanning lines; and ㈣ line driving circuits, which drive the aforementioned signal lines formed on the aforementioned insulating substrate; and the aforementioned signal line driving circuits include: an amplifier, which amplifies analog video signals; and a signal line selection circuit, written by IL You're late, and you choose the signal line of the analog video signal supply target amplified by the amplifier described above; the amplifier includes: power line and ground line; -9-

526465 A7 B7 V. Description of the invention (6) Three inverters connected vertically; a resistance element provided between the foregoing inverter and the aforementioned power line; a resistance element provided between the foregoing inverter and the foregoing Between ground wires; the first capacitor element is connected between the input terminal of the aforementioned inverter in the previous section and the output terminal of the aforementioned inverter in the last section; the switching circuit is arranged in the inverter of the aforementioned first section It can be switched whether a short circuit is formed between the input and output terminals of the inverter in the first stage; and the phase compensation impedance element is inserted between the input and output terminals of the aforementioned inverter in the second stage. In addition, the display device includes: an insulating substrate including a signal line and a scanning line, which are arranged vertically and horizontally; a display element, which is formed near each intersection of the signal line and the scanning line; a scanning line driving circuit, which drives The aforementioned scanning line; and a signal line driving circuit for driving the aforementioned signal line formed on the insulating substrate; and an opposite electrode disposed opposite to the aforementioned insulating substrate and forming a common electrode; and the aforementioned signal line driving circuit The amplifier includes: an amplifier for amplifying an analog video signal; and a signal line selection circuit for selecting a signal line to be supplied by the analog video signal amplified by the amplifier; the amplifier has an odd number of inverters connected in a vertical direction on a display element; The voltage-illuminance characteristic curve is near the voltage with the largest slope, which maximizes the gain of each inverter. • 10- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 7 526465 V. Description of the invention (In addition, the display device includes: signal lines and scanning lines, which are arranged vertically and horizontally on an insulating substrate. · Obvious parts, which are formed near the intersections of the aforementioned signal lines and scanning lines; scanning line driving circuits, which drive the aforementioned scanning lines; and signal line driving circuits, which drive the driving lines formed on the aforementioned insulating substrates The aforementioned signal line; and the aforementioned signal line driving circuit includes an amplifier which amplifies an analog video signal; and a signal line selection circuit which selects a signal line to be supplied with an analog video signal amplified by the aforementioned amplifier; the aforementioned amplifier includes : Inverters connected vertically in the (2η + 丨) segment (where integers greater than ngi); and each component element is connected to the inverter in the aforementioned (2 η + 1) segment &lt; between segments, and Between the input terminal of the aforementioned inverter and the output terminal of the aforementioned inverter in the final stage; and each transistor ruler constituting the aforementioned inverter of the first slave to the second stage If the size is larger than j, the size of the transistor of the aforementioned inverter is included, and the size of each transistor of the inverter is smaller than the size of the transistor of the aforementioned inverter. The display device includes: signal lines and scanning lines, which are arranged vertically and horizontally on an insulating substrate; 70 pieces of display, which are formed at the intersections of the aforementioned signal lines and scanning lines.-This paper is a Chinese National Standard (CNS) Α4 specification (210 χ 29 ^ — 526465 A7 _B7 ——- 5. In the vicinity of the invention (8); Scan line drive circuit, which drives the front scan line; and the signal line drive is more electric, its drive shape A is in the aforementioned insulation The aforementioned signal line on the substrate; and the aforementioned signal line driving circuit includes an amplifier which amplifies an analog image signal; and a signal line selection circuit which selects a signal line to which an analog image signal amplified by a front amplifier is supplied The aforementioned amplifier includes: a power line and a ground line; the reverse direction of the (2n + 1) segment (where 11 is an integer greater than or equal to) of the vertical connection is that, the capacitor element is connected to the front 逑 ( 2 n + 1) between the segments of the inverter, the input terminals of the aforementioned inverter in the initial stage, and the output terminals of the aforementioned inverter in the final stage; and several impedance components, which are respectively connected to the power supply Line and the aforementioned odd number of inverters; the impedance values of the aforementioned impedance elements respectively connected to the aforementioned inverters in the second to 2n stages are smaller than the impedance values of the aforementioned impedance elements connected to the aforementioned inverters in the last stage, and The impedance value of the aforementioned impedance element connected to the aforementioned inverter in the first stage is greater than the impedance value of the aforementioned impedance element connected to the aforementioned inverter in the second stage. In addition, the display device includes: a signal line and a scanning line, which are arranged vertically and horizontally. On an insulating substrate; -12-

Applicable to China National Standard (CNS: Tl4 specification (―JiT 526465

Near the display element; and on the insulating substrate before it was formed at the intersections of the aforementioned signal lines and scanning lines, the scanning line driving circuit was used to drive the aforementioned scanning line ^ number line driving circuit, which was driven to form the aforementioned signals And the aforementioned signal line driving circuit includes: a latch circuit, which latches digital pixel data; a D / A converter, which converts the aforementioned pinout Lei Jiu, Π lock private circuit (the latch output is converted into an analog image signal An amplifier that amplifies the analog video signal converted by the aforementioned D / A converter; and a signal line selection circuit that selects a signal line to which the analog video signal supplied by the amplifier is amplified; the amplifier includes: vertical connection (211 + 1) paragraph (where 11 is an integer of 1 or more); and capacitor components, which are connected to the inverter (<1 n + 丨) and <1; Between the input terminal of the aforementioned inverter and the output terminal of the aforementioned inverter of the last stage; the inverter of the aforementioned (2n + 1) stage has first and second power terminals, respectively, the aforementioned first and second At least one of the two power terminals is supplied with a different reference voltage for each inverter in the aforementioned (2n + 1) stage, and is supplied to each of the aforementioned first and second power terminals in the inverter from the second stage to the 2n stage. The reference voltage of at least one of the parties is greater than that of the aforementioned inverter supplied to the last paragraph. -13- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Binding 526465-_____ ____B7 V. Description of the invention (1 〇) The reference voltage of at least one of the aforementioned first and second power terminals, and the reference voltage of at least one of the aforementioned first and second power terminals supplied to the inverter of the first stage is smaller than the aforementioned reference voltage supplied to the second stage. The reference voltage of at least one of the aforementioned first and second power terminals of the commutator. In addition, the display device includes: a signal line and a scanning line, which are arranged vertically and horizontally on an insulating substrate; a display element, which is formed on the aforementioned signal line And near the intersections of the scanning lines; · Scanning line driving circuits that drive the aforementioned scanning lines; and 仏 ,,, and spring drive the fast road 'which is formed on the aforementioned insulating substrate The aforementioned signal line; and the aforementioned signal line driving circuit includes: an amplifier 'which amplifies an analog video signal; and a signal line selection circuit which selects a signal line to which an analog video signal supply object amplified by the amplifier is applied, and performs signal line writing The aforesaid amplifier includes: ^ several first amplifying sections, and the common rule is composed of more than one inverter, and are connected in parallel with each other; a second amplifier, which includes a plurality of inverters connected vertically; The selection section is to sequentially select any one of the plurality of first amplification sections, supply the output of the selected first amplification section to the inverter of the first stage of the second amplification section, and cause the output of the second amplification section to be output. Return the input side of the inverter of the first stage of the first selected amplifier to form a closed circuit; and -14-

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DESCRIPTION OF THE INVENTION (Several capacitor elements ^, 'are connected between the above-mentioned sealed and inverter sections, respectively; before each amplifier in the closed loop, before the meter, the upper ~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 20 ~ 30 A 前述 The Amplifiers in the Closed Circuit When performing the following order writing: When writing the shouting line, you will be able to see the signal line inside you. In addition, the display device contains a video signal. The signal line and scanning line * — ', are vertical and horizontal. Arranged on the insulating substrate · The display and components are re-used on the P poles, and are formed near the aforementioned signal lines and scans; ^ ^ lines and scanning lines drive circuits at each intersection, Drive the aforementioned scanning winding and signal line drive circuit, which can be driven to form the aforementioned signal line; and 4, and the power supply voltage before the edge board generates a lightning &amp; ^ voltage to produce 4:;:! Is based on the first-second power supply voltage supplied from the outside;% source voltage is approximately an integral multiple of the voltage level and the aforementioned signal line drive circuit includes an amplifier, which amplifies analog video signals ; And "number line selection circuit, The face of the wheat silly commented on the analogy of the amplifier, the analogy of the amplifier, the analog; the 5V image, the supply and the signal of the object, and the implementation of the signal line nesting; the amplification benefit is based on the second Power voltage drive. In addition, according to the first two M t ^ μ-μ: ^, Bao Po, person voltage level is lower than the first reference 々 &gt;# m should be 11 (n is an integer above 2) The digital analog conversion circuit of bits, digits, and volts contains ... The first electric valley is the element 'its system can be divided into six ^ ^ V ^ ^', storage ® should be the highest 1% of the digital signal above each bit value other than 7C The charge of this paper is in accordance with Chinese National Standard (CNS) A4 specification -15 526465 A7 B7. V. Description of the invention (12) The second capacitor element is for re-distribution and storage of electricity between the aforementioned first capacitor element. The third capacitor element can store the electric charge corresponding to the highest order bit value of the aforementioned digital signal; and the charge control circuit sequentially stores in the first capacitor element other than the highest order bit of the aforementioned digital signal. The charge of each element value is Each bit other than the highest order bit of the bit signal repeatedly performs the storage charge redistribution process with the second capacitor element, and stores the charge corresponding to the highest order bit value of the aforementioned digital signal in the aforementioned third capacitor. Within the element, redistribution of stored charge is performed between the second capacitor element and the third capacitor element. In addition, the display device includes: a plurality of switching elements, which are disposed near the intersection of the signal line and the scanning line The signal line driving circuit is a driving signal line; the scanning line driving circuit is a driving scanning line; the aforementioned signal line driving circuit has a digital analog conversion circuit with the number 22 of the scope of patent application, which is a digital display of pixel information The signal is converted into an analog signal, and the output of the aforementioned digital analog conversion circuit is supplied to a corresponding signal line. Brief Description of the Drawings Fig. 1 is a block diagram showing a rough structure of a first embodiment of a liquid crystal display device. FIG. 2 is a block diagram showing an internal structure of a signal line driving circuit. -16- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 526465 A7 B7 V. Description of the invention (Figure 3 shows the daC, AMP 17 and signal line selection circuit 1 in the signal line drive circuit 1 The circuit diagram of the detailed structure of Figure 8. Figure 4 is the working timing diagram of the DAC. Figure 5 is a diagram that separates the type of power supply voltage supplied from the outside by the inverter in the first stage and the inverter after the second stage. 6A, 6B are circuit diagrams showing the specific structure of the signal line selection circuit 丨 8. Figure 7 is a circuit diagram showing a similar example of the signal line selection circuit 18. Figure 8 is a circuit diagram showing the structure of the precharge control circuit. Figures 9A, 9B It is a circuit diagram showing an analog switch for penetrating compensation in series on an analog switch. Fig. 10 is a circuit diagram showing a capacitor element for phase compensation in A MP. Fig. 11 is a circuit diagram showing a similar example of Fig. 10 Fig. 12 is a circuit diagram showing another similar example of Fig. 10.

Fig. 13 is a circuit diagram showing a similar example of Fig. 12 Q. Fig. 14 is a diagram showing a power wiring pattern of the AMP 17 arranged to overlap the common electrode. Fig. 15 is a diagram showing a configuration in which a capacitor element in the AMP 17 is superposed on a common electrode. &amp; FIG. 16 is a diagram showing a composite resistance from a common potential supply terminal on the glass substrate 2. As shown in FIG. Figure 17 shows the combined resistance diagram from the supply terminal of the auxiliary capacitor potential. Figure 18 A shows the increase characteristics of A MP, Figure 18 b shows the use of -17-

526465 A7 B7

V. Description of the invention (14) A gain characteristic diagram of A MP of the complementary inverter. Fig. 19 is a diagram showing an analog switch on the return control near the input capacitance of the inverter in the initial stage. &Amp; Fig. 20 is a circuit diagram of a tenth embodiment of the signal line driving circuit. FIG. 2 is a diagram showing the voltage level of each part of the liquid crystal display device of this embodiment. Figure 2 shows the edge diagrams of the power supply voltage side and the ground voltage side. FIG. 23 is a circuit diagram of an eleventh embodiment of the signal line driving circuit. Fig. 24 is a circuit diagram of a signal line driving circuit of a twelfth embodiment. Fig. 25 is a circuit diagram of a signal line selection circuit in a signal line driving circuit of a thirteenth embodiment. Figure 2 6 shows the state diagram of the phase margin change. FIG. 7 is a circuit diagram of AMp in a signal line driving circuit of a fourteenth embodiment. FIG. 28 is a circuit diagram of AMp in a signal line driving circuit of a fifteenth embodiment. Fig. 29A is a circuit diagram of an AMP in a signal line driving circuit of a sixteenth embodiment, and Fig. 29B is a circuit diagram of the previous amp. FIG. 3A is a working timing diagram of AMP n in this embodiment, and FIG. 3B is a working timing diagram of AMP 17 of FIG. 25 for comparison. Figure 3 Peripheral circuit diagram of 1 series AMP 17. FIG. 32 is a working timing diagram of the circuit of FIG. 31. Figure 3 3 shows a circuit of a booster circuit included in the power supply IC of Figure 2. -18-This paper is suitable for financial standards @ a 家 标准 (CNS) Μ Specifications (⑽ x 297 公 董)-526465

Illustration. Fig. 3 is an explanatory diagram of the functions of the 4 series power supply IC. Figure 3 shows the relationship between the voltage levels of the external power supply voltage vdd, the power supply voltage XAVDD, the maximum reference voltage REFH generated by the divided resistor ladder, and the minimum reference voltage REVL. Figure 36 is an explanatory diagram of the resistance of the power and ground wires connected to the inverter in the MP. Fig. 37 is an explanatory diagram of the shrinkage time of the 7 series A MP output. Figure 38 shows that the width of the inverter width w 丨 in the first stage is equal to the width of the inverter W2 in the second stage, and the width W2 of the inverter in the second stage and the width of the inverter in the third stage are changed. A graph of the shrinkage time of the output of AMP 17 when the ratio of W 3 is W2 / W3. ^ FIG. 9 is a partial layout diagram of A MP in FIG. 3. FIG. 4 is a layout diagram of a low-temperature polycrystalline silicon τ ρ d substrate of the twentieth embodiment. FIG. 4 is a schematic structural diagram of a 1-series signal line driving circuit. FIG. 42 is a circuit diagram showing a detailed structure of the DAC 16 and the AMP 17. Figure 4 timing chart of the operation of the 3 series DAC 16. FIG. 4 is a working timing diagram of the signal line driving circuit 5 of this embodiment. Fig. 45 is a circuit diagram showing a signal line driving circuit of a common inversion driving. Figure 46 is a circuit diagram of a DAC connected to an AMP without a differential amplifier. Figure 47 is a circuit diagram of a previous Dac using a polycrystalline silicon TFT on a glass substrate. -19- This paper size is in accordance with China National Standard (CNS) A4 (210X297mm). I &quot; ------ _ 16 V. Description of the invention

In the following, reference is made to the I display device and the digital class:; ::: Digital analog conversion circuit of the invention. FIG. 1 is a block diagram showing the structure of the display device of the present invention. = Device structure of the device. Figure 1; Configuration, with the liquid crystal layer sandwiched between them, not shown ... On the base, except for the glass substrate 2 of Figure 1, maybe a ..., and the control signal to the drive circuit &quot;: transport digital image The substrates of the signal source, these substrates mc3 are connected to zero 闰 t, * of the supply voltage, and the printed circuit boards are connected between the boards. Edge: Two: The pixel array section 1 is provided on the substrate 2 and its signal arrays are arranged; = :, spring: and near the intersections of the signal line and the scanning line are formed: prime τ; the signal line drive circuit $, It is a driving signal line; and a scanning, driving circuit 6 which drives a scanning line. The signal line driving circuit 5 includes: a shift register η, which generates shift pulses which are sequentially = dynamic pulse shift; a data bus 12, which supplies bit pixel data; and a sampling interlock 13, which is connected with Shift pulse synchronization, sequential digital pixel data; manned device 14, which integrates the flash lock output of the sample flash lock 13, and simultaneously asks the lock at the same time, the electric willingness to select the circuit ^ 5 ' The upper-order side bit of the pixel data is selected, and the reference voltage is selected; the D / A converter (hereinafter referred to as DAC) 16 is to D / A the lower-order side-bit rows of the digital pixel data according to the selected reference voltage. Conversion; amplifier (hereinafter referred to as AMP) 17, which is amplified by D / A conversion or the like-20- This paper size is suitable for towel @ @ 家 标准 (CNS) A4 specification (2i〇i 297 mm) 17 526465 V. Invention Explanation (contrast t signal; signal line selection circuit 18, which switches and controls AMp 17 "knows which signal line to supply; and timing control circuit". Figure 2 shows the internal structure of the signal line drive circuit 5. Block diagram. Figure 2 = Beyer distribution circuit 21 corresponds to the shift register &quot; and data of Figure i Flow:? In addition, Figure 2 shows the integration of DAC 16 and AMP 17 into a block. The voltage-dividing resistor ladder 20 generates 9 kinds of references based on the three reference voltages supplied from the power supply IC4, E = Vm, REF2. The voltages V1 to V9 are supplied to generate 2 quasi-voltages VI to V9 to the voltage selection circuit 15. The voltage selection circuit ^ selects two kinds of reference voltages Vrl and Vr2 from the reference voltages vi to V9 based on the upper-order 3 bits of digital pixel data. DAC16 uses the reference voltage γη, Vd output from the voltage selection circuit 5 to generate a 3-bit voltage corresponding to the lower order of digital pixel data. ^ The generated voltage is amplified by AMP 17 and supplied to the signal line selection circuit ^ # The selection circuit 18 performs pre-charging of the signal line before supplying the voltage from AMp 17 to the corresponding u line. The pre-charging voltage uses the reference voltage Vm supplied by the power source! Γ1. More specifically, it uses the voltage shown in FIG. 8 The constructed circuit performs pre-charging. "Figure 3 shows the DAC 16, AMP 17, and signal line selection circuits in the signal line drive circuit 5! The detailed structure circuit diagram of 8. As shown in the figure, M. μ is selected according to the private pressure. References provided by circuit 15 Pressure% ~ Performance / α conversion. DAC 16 contains: capacitor elements C 1 ~ C3; analog switches s ~ s ^, 21 scales applicable to Chinese National Standards (CNs) A4 specifications (⑽X tear public love) binding 18 526465 V. Invention Description (S2 S3a, S3b 'S4' which is the charge of the capacitor elements ci ~ c 3 again: distribution; and analog switches S5 '/ S5, S6, / S6, s7, / S7, M_ 4 pixel shell material (below 3 Bit logic executes on / off control. In addition, a capacitor element shared by the DAC 16 and the AMP 17 is provided. The capacitor element C6 can also be used in the D / A conversion process, and it can also be used for the control of the first-stage inverter of AMP 17. Figure 4 is a timing diagram of the operation of the DAC 16. First, at the time of time, the analog switches S5 ~ S7 are opened in response to the lower-order 3 bits of the digital pixel data, and the analog switches Sla ~ S are pulled to 4t, c ,. In response to this, the charge corresponding to the digital pixel data bit is stored in the capacitor element and is connected to 0 :, when the switch Γ is switched on, the charge corresponding to the voltage ^ is stored in the capacitor 2 CM 'analog switch / S6 is turned on In this case, the response voltage is within the capacitor element C1. In addition, when the analog switch S7 is turned on: ^ The voltage ^ is stored in the capacitor element ^ is stored in the Baoguzhai element C2, and at time T2, the analog switch dog and bayby switch s3a, s3b is turned on, and the capacitor Yuan ^ "Redistribution of Charges" Capacitor Element 3 "Implementation Charge. After that, the analogy "" in the capacitor element C2 and the capacitor element C6 is stored in the D / A conversion according to the next 3-bit = reallocation. This is stored at the left end of the capacitor element. In addition, at time =

After ⑺ 丄 3, AMP -22- 526465

The analog switches 18 between 17 and the signal lines are all turned off, and the analog switches ⑺, si0, sn are turned on, forming a short circuit of the input and output of IV1 to IV3. The working threshold voltages of IV1 to IV3 are stored at the right ends of the capacitors C4 to C6. 2. At time T5, the analog switches S9 ~ S1 1 are turned off. The switch s 8 and one of the switches 丨 8 are turned on to perform a nesting operation to make the signal line voltage equal to the analog voltage. The AMP 17 performs the writing operation of the voltage of the left end of the capacitor C6 on the signal line by the switch s 8 that feeds back the signal line voltage to the aforementioned analog voltage. After that, after time T5, the same operations at time Ding to Ding Do are repeated. As shown in FIG. 3, AMP 17 includes: three inverters 1 ¥ 1, IV2 ′ IV3 connected vertically; capacitor elements C4, C5 inserted between the segments of inverters ϊv 丨 ~ v3; connected in series at the end The analog switch S8 and capacitor element C6 between the inverter IV3 of the stage and the inverter ^ ινι of the initial stage; and the analog switch s 9 ~ s J i inserted between the input and output terminals of the inverters IV 1 to IV 3 . The three-stage inverters IV1 to IV3 in the AMP 17 are respectively supplied with a power voltage XAVDD and a ground voltage XAVSS, and this embodiment is shown in FIG. 3, which separates the power supply line L 丨 and After the second stage, the power supply line L 2 of the inverters IV2 ′ IV3 is provided. Specifically, it is in the inverter IV1 in the first stage, and the power supply voltage XAVDD and the ground voltage XAVSS are respectively supplied through the resistance element ruler and R2, and in the inverters IV2 and IV3 after the second stage, through the resistor R3 , R4, respectively, supply the power supply voltage XAVDD and the ground voltage XAVSS. In this way, the reason why only the inverter IV 1 in the first stage separates the power supply line is -23-

This paper size is in accordance with China National Standard (CNS) A4 specification (21〇X 297 male D 526465 A7 B7 V. Description of the invention (2) Because the inverter IV 1 of the initial stage has a great influence on the accuracy of AMP 17. In addition, only The specific circuit structure of the inverter IV 1 in the initial stage to separate the power supply line is not limited to the one shown in FIG. 3. Inverters IV2 and IV3 after the second stage. In the inverter IV1 in the first stage of FIG. 5, a power supply voltage XAVDD2 is supplied via a resistor R1, and a ground voltage XAVSS1 is supplied via a resistor R2. In addition, the second stage The subsequent inverters IV2 and IV3 are supplied with a power supply voltage XAVDD1 through a resistor R3 and a ground voltage XAVSS1 through a resistor R4. The capacitor element C 7 connected to the input and output terminals of the second-stage inverter IV2 of the AMP 17 is an invention After trial and error, a form of an important impedance element that stabilizes the operation of A MP is found. The capacitor element C 7 is an impedance element used for phase compensation. Details will be described later. Capacitor element C 7 sometimes It can be not explicitly set, or it can be formed non-explicitly as parasitic capacitance according to the circuit layout. No explicit phase compensation capacitor is set. When the value of C7 is set to 0, the inverters in the odd-numbered segments are connected vertically. In a loop shape, it is easy to cause a circuit that causes oscillation, and it cannot be used in an amplifier circuit of a display device in any case. Figure 5 is also the same as Figure 3, because the power supply line of the primary inverter IV 1 in the AMP 17 and The power supply lines of other inverters IV2 and IV3 are separated, so the accuracy of AMP 17 can be improved. In addition, for simplicity, Figure 5 omits the analog switches between the input and output terminals of each inverter IV1 to IV3 in AMP 17. In addition, the resistance element Rm and capacitor element Cm shown in Figure 3 are set in the mold-24- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 526465 A7 B7 V. Description of the invention (group (installation Substrate), R1-R4 are provided on the insulating substrate. The capacitor element Cm stabilizes the power supply voltages xavDD and XAVSS, and the resistor elements Rm and R1 to R4 prevent large currents from flowing into the inverters IV1, IV2 'IV3 constituting AMP 17. In order to suppress the increase in power consumption, and to prevent the amp 17 from oscillating, to suppress the occurrence of display failure. (Second Embodiment) 4 The signal line selection circuit 18 in the Lv line driving circuit 5 is constituted by an analog switch including τ FT However, the on-resistance of the analog switch may vary due to the deviation of the characteristics of the TFT, and the display may be unstable due to the deviation of the driving speed of the signal line caused by the AMP. In addition, when local Vth deviation occurs, it may also be caused by the connection of the specific analog switch. The on-resistance is too small, and the circuit of the longitudinally connected inverters in the odd-numbered sections is close to the no-load state, which causes A MP to oscillate, resulting in line defects. Therefore, as shown in FIG. 6A, two analog switches S21 'and S22 may be connected in parallel to each signal line to form the signal line selection circuit 18. At this time, the circuit diagram structure of the signal line selection circuit 丨 8 connected to a certain signal line is shown in FIG. 6 b ′ is a series of switches S21 and S22 including a pMOS transistor and an nMOS transistor in parallel. 'In this way', the analog switches S21 and S22 are connected in parallel to form the signal line selection circuit 18, even if the local Vth deviation of one of the two analog switches S21 and S22 in parallel cannot be turned on reliably, as long as the other- The signal line writing can be performed when the square is turned on, so that the aforementioned display discomfort can be reduced. Therefore, 'is not easily affected by the characteristic deviation of the analog switch. In addition, even if one of the analog switches is defective and cannot function normally, it can be adjusted to -25- This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm)

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On the other hand, the dog can perform signal line writing than the switch, which can improve the manufacturing yield. In addition, if there are no layout restrictions, it is more effective when three or more are connected in parallel. (Third Embodiment) Technically, it is technically difficult to make the on-resistance of the analog switch constituting the signal line selection circuit 18 uniform. Therefore, as shown in FIG. 7, it is considered to insert a resistance element inverse 5 between the signal spring selection private circuit 18 and the ^ line to reduce the on-resistance of the analog switch in the signal spring selection envelope 18 Methods. At this time, the resistance value of the resistor 7G R5 should be set to be greater than the on-resistance of the analog switch within the signal line selection circuit =. By this, since L is observed from AMp 17, the line side resistance is in line with the resistance value of the resistance element R5, and has nothing to do with the on-resistance of the analog switch in the signal line selection circuit 18, so it is possible to reduce the writing of line k Into the timing deviation. In addition, as shown in FIG. 8 π, one end of the resistance element R 5 may be connected to a pre-charged% k circuit 22. The analog switch in the pre-charge control circuit 22 of FIG. 8 is connected to the signal line according to the output of the AMP 17 before the signal line is turned on to perform the pre-charging (pre-write) of the letter j line. In this way, the signal line writing time can be shortened by performing the precharging of the signal line by performing the signal line nesting. In addition, by making the size of the analog switch in the precharge control circuit 22 smaller than the size of the analog switch in the signal line selection circuit 丨 8, the leakage current from the precharge power source can be reduced. Conversely, by making the analog switch size in the precharge control circuit 22 larger than the analog switch size in the line selection circuit 18, the time required for writing the signal line can be further reduced. __ -26- This paper size is applicable to the national standard (CNS) M standard of the towel country (21G> &lt; 297 public envy); · binding line 526465 A7 B7 V. Description of the invention (23) (fourth embodiment) Signal line The analog switches used in the various parts of the driving circuit 5 are generally shown in FIG. 9A, which adopts a structure in which nMOS transistors and pMOS transistors are connected in parallel. However, with this structure, when the analog switch is switched from on to off, the charge stored in the capacitance between the gate and source of the analog switch flows into the load capacitor, and the output voltage of the analog switch fluctuates. Here 'the capacitance between the gate and source of the pMOS transistor and the iiMOS transistor when the analog switch is turned on is set to C gsp (OlM)' CgSn (〇N) 'pMOS voltage when the analog switch is turned off The capacitance between each gate and source of the crystal and the nMOS transistor is set to Cgsp (〇FF) 'When Cgsn (〇FF)', the amount of change in the output voltage of the analog switch △ V is expressed by the following formula (1): △ Factory—i ^ gspjON) ~ ^ gsn (OFF) Wa ~ gsnjON) ~ ^ gsp (OFF)} Q ^ a ~ ^ dd) — c + qleft ^ gsp (OFF) _ {Cgsp (-va)-Cgsn ( ~ K)} Fa-{Cgsn (Vdd -K)-Cgsp (Vdd-Va)} (Vq-vdd) — C + CgsS-Va) + Cgsp (Vdd-Va) • ·-(1) If the signal line is selected When the output voltage of the analog switch in the circuit 18 changes, the writing voltage of the signal line also changes, which adversely affects the display quality. This is also effective for capacitor-related switches such as the capacitor elements C1 to C3 of the DAC 16 shown in FIG. 3. Therefore, in this embodiment, as shown in FIG. 9B, at least a part of the analog switch in the signal line driving circuit 5 is connected to the original analog switch S 2 3 in series with the penetrating compensation analog switch S 24. The analog switch S 2 4 for penetration compensation uses a pMOS transistor and an nMOS transistor in parallel to form a structure in which the source and drain terminals of the two transistors are short-circuited. Analog switches for penetration compensation S 24 and -27- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 526465 A7 B7

I -28- ¥ Paper size applies to Chinese National Standards (CNS) A4 specifications 526465 A7 ---------- B7 V. Description of the invention () 25, 2 = 10 not because of the contradiction in the second paragraph The phase compensation η of the resistive element Ra and the capacitor element C7 in series between the input and output of the commutator IV2 is not easy to cause vibration even when the absolute value of Vth becomes small. The layout can be considered to determine the resistance value of Ra and the capacitance of C7, so that the product of Ra and C 7 <reaches a specific value. The so-called specific value may be about 5 times to 3 times the value of the product of the product p u <the resistance Rsig output to the signal line and the capacitance c々 of the signal line. The circuit of FIG. 10 cuts off the signal line by the impedance element Ra and the capacitor element C7, and prevents the frequency component of the load from easily vibrating i. In addition, when the capacitor element C / is too large, i has the disadvantages of an increase in circuit area and an increase in the driving load of the inverter at the initial stage, the shrinkage is deteriorated, and ringing is easily caused. In addition, the capacitor element 0: 7 of FIG. 10 can also be inserted between the input and output terminals of the third stage inverter IV3 constituting the AMP 17. FIG. 11 is a similar example to FIG. 10, which is characterized in that one end of a capacitor element ^ 々 inserted between the inverter ινι in the first stage and the inverter IV2 in the second stage is connected to the inverter IV2 in the second stage. Between the output terminals, a phase-compensating element including a resistive element Ra and a capacitor element (: 7) is inserted. By inserting such a capacitor element C 7, the effect of preventing oscillation can be obtained in the same manner as in FIG. It can suppress the reduction of the gain more than that shown in Figure 10. Furthermore, because the shrinkage speed is improved, even if the absolute value of Vth becomes larger, it still has the effect of preventing ringing. At this time, the capacitance of the capacitor element c 7 is The capacitor element C4 should be less than 1/2. If it is too large, it will cause the disadvantages of increasing the circuit area and the driving load of the initial stage inverter. The shrinkage will deteriorate and it will easily cause vibration. (CNS) A4 size (210X297 mm) 526465 A7

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Line 526465 A7 B7 V. Description of the invention (27) (Seventh embodiment) When the combined resistance Rcom from the common potential supply terminal on the glass substrate is high, the electric ink level of the common electrode 2 3 formed on the opposite substrate may be The required value cannot be reached within a certain period. This combined resistance Rcom is the resistance of the thick line portion in FIG. 16. Therefore, the seventh embodiment reduces the resistance value of the combined resistor R 7 from the common potential power supply terminal by thickening and shortening the voltage supply line to the common electrode 23. Specifically, the resistance value Rcom of the combined resistor R7 from the common potential power supply terminal should be set to satisfy the relationship of the following formula (2).

Rcom &lt; Specific coefficient X Turn-on period of the aforementioned signal line selection circuit / (Total amount of auxiliary capacitor / Capacitance between the aforementioned common electrode and the aforementioned insulating substrate) / Number of simultaneous writing signal lines- (2) When the combined resistance R cs on the auxiliary capacitor supply terminal is high, the voltage level of the auxiliary capacitor may not reach the required value within a certain period. The combined resistance R c s is the resistance of the thick line portion in FIG. 17. Therefore, a similar example of the seventh embodiment is to reduce the resistance value of the composite resistor R 7 from the potential supply terminal of the auxiliary capacitor by thickening and shortening the voltage supply line to the auxiliary capacitor wiring. Specifically, the resistance value R c s of the combined resistance R 7 from the potential supply end of the auxiliary capacitor should be set to satisfy the relationship of the following formula (3).

Res &lt; Specific coefficient X Turn-on period of the aforementioned signal line selection circuit / (Total amount of auxiliary capacitor / Capacitance between the aforementioned common electrode and the aforementioned insulating substrate) / Number of simultaneous writing signal lines ... (3) -31-This paper Standards apply to China National Standard (CNS) A4 specifications (210X297 mm)

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(Eighth Embodiment) The figure shows an illuminance curve of the liquid crystal portion of the liquid crystal display device of this embodiment. The illuminance is proud of the change of the voltage, and it is attached to the middle voltage. The other voltages are relatively close to the middle lightning pressure, ^ t ^ full /, and the inter-child pressure. That is, the error voltage of the output of AMP 17 near the middle is directly related to the display deviation. Other voltages cannot be identified when the error voltage is not too large. Therefore, the output error voltage of AMp should be minimized near the intermediate voltage. According to the present invention, the output error voltage of the AMP 17 is inversely proportional to the gain product of the name of the inverting amplifier circuit (inverter). The so-called gain here refers to the slope (steep output) of the polarity of the input and output characteristics of the buck amplifier circuit, and the gain changes due to the input voltage. The present inventors have found that driving a liquid crystal display and displaying an inverting amplifier circuit used on line 4 of AMPn, a complementary inverter in which a p-channel TFT and an n-channel TFT are connected in series between power supply voltages is the most appropriate. In this way, when the intermediate voltage is embedded, each inverter works near the threshold of each inverter. As shown in Figure 18B, the gain of the complementary inverter is greatest near its threshold. In addition, a source amplifier can also constitute an inverting amplifying circuit. However, when outputting a voltage near the middle gray scale, it is difficult to configure the error voltage to the minimum. Therefore, in this embodiment, a complementary inverter in which a P-channel TFT and an n-channel TFT are connected in series between the power sources is used as the inverter of the AMP 17. In addition, when a display element other than a liquid crystal display device is used, it is as follows. That is, you can review the voltage range with the steepest slope from the voltage-illuminance characteristic diagram of the display element in Figure 18A, and select the power supply voltage of the amplified section and the type of the amplified section. ) A4 size (210X297 mm)

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Class to maximize the gain of each amplified section of the AMP. (Ninth Embodiment) As shown in FIG. 19, the AMP 17 is formed by vertically connecting the odd-numbered inverters, between the input terminal of the inverter IV1 in the initial stage and the output terminal of the inverter IV3 in the final stage. Insert the analog switch S 8 and the electric switch 衮 Γ to the gain accuracy of · 17, which has the greatest effect; the commutator IV 1. When the analog switch 88 on the return path of the inverter i ν 3 in the last stage and the input capacitance 〇6 of the inverter IV1 in the initial stage are isolated from each other, the on and off switch of the far analog switch S 8 The input capacitance of the inverter I v 1 in the early stage has a greater influence. Therefore, the ninth embodiment is characterized in that the analog switch s 8 on the return path and the input capacitance C 6 of the inverter I V 1 in the initial stage are arranged near each other. With this, by turning on and off the analog switch S 8, the input capacitance of the inverter IV1 in the initial stage is not affected, and high-precision gain adjustment can be performed. (Tenth implementation mode) The ten other types of application only form an imbalance between the resistance value of the resistance connected to the power supply line of the AMP 17 and the resistance value of the resistance connected to the ground line. FIG. 20 is a circuit diagram of a tenth embodiment of the ^ -line driving circuit. The signal line driving circuit of FIG. 20 is the same as the signal line driving circuit of FIG. 3 in terms of circuit structure, but is connected to the power supply line L11 (including the power supply lines li, L2) of the inverter connected to the AMP 17. The sum of the resistance values of the resistors Ri, R3, and Rd is greater than the sum of the resistance values of the resistors R2, R4, and RS connected to the ground line [1 2 (including the ground line L3 'L4). This -33- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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526465 A7 B7 5. The resistance Rd at the description of the invention (30), Rs is the resistance added to the glass substrate, and the resistances R 1 to R 4 are the resistances formed in the glass substrate. The voltage selection circuit 15, DAC 16, AMP 17, and signal line selection circuit 18 of Fig. 20 constitute a group of circuits. Several of these circuits are integrally formed on the same glass substrate. Fig. 21 is a diagram showing voltage levels of respective parts in the liquid crystal display device of this embodiment. The power supply voltage XVDD (= 5 V) is supplied to the shift register 1 in Figure 1. 1. the data bus 1. 2. the sampling latch 1. 3. the load latch 1. 4. the voltage selection circuit 1. 5. the DAC. 16 and the power supply voltage of the signal line selection circuit 18. The power supply voltage XAVDD (= 5.5 V) is a power supply voltage supplied to the inverters IV1, IV2, [V3 of AMP 17 of FIG. 1]. The voltage Gate is the gate voltage of the TFT for pixel driving. The common voltage Vcom is a voltage from 0 V to 5.3 V, and takes an interactive value at a specific period. The signal voltages VsigH and VsigL are the signal voltages output from AMP 17. The maximum voltage VsigH is (= 4.5 V) and the minimum voltage VsigL is (= 0 · 5 V). The voltages REF1 and REF2 are the reference voltages supplied to the voltage-dividing resistor ladder 20 of FIG. 2 and are linked with the driving cycle of VCOM. The values of REF1 and REF2 are 0V and 5V, or interchanged with each other to 5V and 0V. It can be seen from Fig. 21 that the potential difference between the maximum value of the power supply voltage XAVDD and the signal voltage VsigH is 1.0 V, and the potential difference between the ground voltage 0 V and the minimum value VsigL of the signal voltage is 0.5 V. That is, as shown in Fig. 22, the power supply voltage side has an edge of 1.0 V, and the ground voltage side has only an edge of 0.5 V. In Fig. 22, Δ indicates the voltage fluctuations of the signal voltages VsigH and VsigL. At this time, the edge Δνΐ on the power supply voltage side is ZWl ^ XAVOD (VsigH + Δ), and the edge Δν2 on the ground voltage side is Δν2 = (VsigL-A) -XAVSS. -34- This paper size applies Chinese National Standard (CNS) A4 (210X 297mm) 526465 A7 B7 V. Description of the invention (31) When the power supply line L 1 1 and the ground line L 1 2 are connected to the resistors respectively, Both ends of these resistors cause a voltage drop. Therefore, only the voltage of the power terminal of the AMP 17 decreases and the voltage of the ground terminal increases. Even so, when the voltage drops within the above-mentioned range, the AMP 17 can still operate normally. For example, consider the case where the resistance values of the resistors connected to the power supply line L 1 1 and the ground line L 1 2 are made equal to each other, and the resistance values of these resistors are gradually increased. As the resistance value is increased, the voltage drop across the resistor is large. As described above, since the edge on the ground voltage side is small, the ground voltage side protrudes from the edge first. To avoid the ground voltage side protruding from the edge first, make the resistance value of the resistor on the ground voltage side smaller than the resistance of the resistor on the power supply voltage side. Therefore, in this embodiment, the total resistance value of the resistors connected to the power supply line L 1 1 is larger than the total resistance value of the resistors connected to the ground line L 1 2. Thereby, both the power supply line side and the ground line side can ensure the same edge, and the resistance value on the power supply line L 1 1 side is increased, and the current flowing into the power supply line L 1 1 is reduced, which contributes to reducing power consumption. In addition, the effect of reducing power consumption is particularly effective when the absolute value of Vth of each TFT element constituting the inverter of the AMP 17 is small. Since the applied voltage of the gates of the inverters of the AMP 17 is always 0.5 to 4.5 V, a through current flows in each inverter. When the absolute value of the aforementioned V t h is small, the through current thereof increases. Since a resistor is provided on the power supply line in this embodiment, only the product of the current X resistance reduces the effective voltage applied to the inverter, thereby suppressing the through current. In addition, when the absolute value of Vth is large, the penetrating current is small, and the product of the current X resistance is also small ^ The effective voltage applied to the inverter -35- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Centi) 526465 A7 B7 V. Most of the power supply voltage of the invention description (32) is directly applied to ensure the maximum current driving capability. For the above reasons, the technique of this embodiment is particularly suitable when a polycrystalline silicon TFT having a large Vth deviation is formed on a glass substrate, and a pixel portion and a driving circuit of a display device are integrally formed. The above figure 20 shows a kind of resistors R1 and R2 provided on the power supply lines L1 and L2 inside the glass substrate, resistors R3 and R4 provided on the ground lines L3 and L4, and resistors Rd and Rs provided outside the glass substrate, but The number of resistors provided on each line is not particularly limited. In addition, all the resistors may be formed in a glass substrate, and conversely, all resistors may be disposed outside the glass substrate. (Eleventh Embodiment) The eleventh embodiment is to supply a power supply voltage to each inverter in the AMP 17 through an individual resistor. Fig. 2 is a circuit diagram of an eleventh embodiment of a 3-line signal line driving circuit. The signal line drive circuit of FIG. 23 is shared with the circuit structure of the signal line drive circuit of the figure except that the configuration of the power supply lines of the inverters connected to the AMP 17 is different. Resistors R11, R12, and R13 are connected between the power terminals of the three inverters IV1, IV2, and IV3 in the AMP 17 and the reference power terminal T1 supplied with the power voltage XAVDD from the outside. These resistors R11 to R13 may be formed inside the glass substrate or may be externally added to the glass substrate. The resistance value Rdl of the resistance R1 1 connected to the inverter IV 1 in the first stage, the resistance value Rd2 of the resistance R12 connected to the inverter IV2 in the second stage, and -36-This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 526465 A7 B7 V. Description of the invention (33) The resistance value Rd3 of the resistance R 1 3 of the inverter IV 3 connected to the last stage, if set to 1 ^ (12 &lt; 1 ^ 3 &lt; 1 ^ (11. More specifically, 'if set to 1 ^ 1 == 2] &lt;: 0' Rd2 = 200 Ω, 1 ^ 3 = 700 Ω. The resistance value of the first-stage resistance R 1 1 The biggest reason for R di is that the inverter IV 1 in the early stage can only work with a threshold voltage. For the purpose of reducing power consumption, increase the resistance value to reduce the power voltage supplied to the inverter IV 1. The resistance value Rd 3 of the resistance of the last stage is set to a voltage having a desired voltage amplitude output from the inverter IV 3. In addition, when the resistance value Rd 2 of the resistance of the second stage is increased, the amp 17 may oscillate, so the resistance value Rd2 is set to a small value. Thus, in this embodiment, the inverters IV1 to IV3 for supplying the power supply voltage to the AMP 17 are individually provided on each inverter. The resistance of the power supply line is based on the functions of the inverters IV1 to IV3, and the resistance values of the resistors R11 to R13 are set to the most appropriate value, so that the performance of the AMP 17 can be improved and the power consumption can be reduced. Twelfth embodiment) The twelfth embodiment is the one that adjusts the size of the inverter in the AMP 17. Figure 24 is the circuit diagram of the AMP 17 in the signal line drive circuit of the twelfth embodiment. As shown in the figure As shown, AMP 17 includes three inverters IV1 to IV3 connected vertically; capacitor elements C4 and C5 connected between the segments of inverters IV 1 to IV 3; analog switch S 8 and capacitor element C 6, which is connected in series between the output terminal of the inverter IV 3 in the final stage and the input terminal of the inverter IV 1 in the initial stage; and the capacitor element C 7 for phase compensation, which is connected to this paper. China National Standard (CNS) A4 specification (210 X 297 mm) 526465 A7 B7 V. Description of the invention (34) Connected between the input and output terminals of inverter IV 2. This embodiment is the second stage inverter The size of IV 2 is larger than the size of the inverter IV3 in the last stage, and the initial stage The size of the inverter IV1 is smaller than the size of the inverter IV2 in the second stage. Figure 24 shows that the number of stages of the inverter in AMP 17 is divided into three stages, but the number of stages is not particularly limited, as long as it is three or more stages. The odd segments are sufficient. For example, when the inverter of (2n + 1) segments (η is an integer of 1 or more) is connected vertically in AMP 17, the gate width of the transistors constituting the inverters of each segment + i and Gate length L 丨 ~ L 2 n + i, satisfy the following relationship: W2n / L2n ^ W2n + 1 / L2n + 1 W2n_1 / L2n-1 ^ W2n + 1 / L2n + 1 • · W2 / L2-W2n + &quot; L2n + 1 w! / L! ^ W 2 / L 2 The reason for satisfying the relationship of the above formula is as follows: Because the inverter IV 1 in the initial stage is also an input signal stage, when the size of the inverter is increased, the parasitic capacitance becomes Large, and affect the accuracy of AMP 17, so it must not be arbitrarily increased. In addition, the size of the inverter IV3 in the last stage was originally determined by the signal line load in the latter stage. When the size of the inverter is increased, the driving capacity for the load on the signal line is too large, and as a result, the stability of the AMP 17 is impaired. In addition, when the size of the inverter IV in the second stage is larger than that of the inverter IV3 in the last stage, the reaction speed of the inverter IV2 in the second stage is increased, and the working speed of the AMP 17 is increased. -38- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm); binding

Line 526465 A7 ____B7 I. Description of the invention (_ &quot; ~~ 〇〇 In addition, the number of segments of the inverter in AMP 17 can also be an odd number of 3 or more. In this way, by inverting the inverter in AMP 17 The size of the element is set to satisfy the relationship of the formula (1), the accuracy of the AMP 17 is improved, and the working speed is also accelerated. (Thirteenth embodiment) The thirteenth embodiment is the final inverter in the AMP 17. Those whose dimensions are smaller than those of the signal line selection circuit. Fig. 25 is a circuit diagram of the amp 17 and the signal line selection circuit 18 in the signal line driving circuit of the thirteenth embodiment. The structure of the AMP 17 is the same as that of FIG. 24 and has Vertically connected three inverters IV1 to IV3. In this embodiment, the size of the last stage inverter γ3 is smaller than the size of the signal line selection circuit 18. More specifically, it will constitute the last stage inverter IV3. When the gate width of the transistor is set to W3, the gate length is set to L3, and the gate width of the transistor in the k-line selection circuit 18 is set to ^ 4, and the gate length is set to L 4, the following relationship is satisfied: W4 / The reason why L4 ^ W3 / L3 satisfies the relationship of the above formula is because of the signal line selection circuit 丨 8 When the on-resistance is increased, the feedback of AMP 17 is too fast, which may cause AMP 17 to oscillate. At this time, since the longitudinally connected IV1 ~ IV3 act like the ring oscillator circuit (vibration circuit), they vibrate violently. Figure 2 6 shows the change of the phase margin that causes the difficulty of vibration when changing the sizes of the inverters IV1 to IV3 in different AMP 17 and the size of the ## line selection circuit 18. Figure 2 6 When the display size ratio of block g1 is 2: 1: 2: 5 ', the display ratio of display size g2 is 1: 2 ... 2: 5, and the display of block g3 is -39- This paper size is applicable to the Chinese National Standard (CNS ) A4 size (210 X 297 mm) 526465 A7 B7 V. Description of the invention (36) When the size ratio is 2: 2: 1: 5. It can be seen from Figure 26 that when it is block g 3, that is, the last The phase inverter IV 3 has a smaller phase margin than the other inverters IV1, IV2 and the signal line selection circuit 18, and it is also known that when the condition (2) is satisfied, it is not easy to cause vibration. In this way, since the size of the inverter IV 3 in the last stage in the AMP 17 is smaller than the size of the signal line selection circuit 18 in this embodiment, it is possible to It is possible to prevent the oscillation of the AMP 17. In addition, as shown in FIG. 24, the number of stages of the inverter in the AMP 17 is divided into three stages. However, the present invention is applicable even for odd stages of three or more stages. (Fourteenth Embodiment) The fourteenth embodiment adjusts the resistance value of the resistance elements of the power supply terminals of the inverters connected to each stage in the AMP 17. FIG. 27 is a circuit diagram of the AMP 17 in the signal line driving circuit of the fourteenth embodiment. Similarly to the AMP 17 of FIG. 24, the AMP 17 of FIG. 27 has three inverters IV1 to IV3 connected in a vertical direction. Each of the inverters IV1 to IV3 has a power terminal Vdd and a ground terminal Vss. Between the power terminal Vdd and the reference voltage terminal XAVDD of each inverter, resistance elements Rv (l), Rv (2), and Rv are individually connected. (3). Similarly, resistance elements Rs (l), Rs (2), and Rs (3) are individually connected between the ground terminal V s s of each inverter IV1 to IV3 and the ground voltage terminal XAVSS. The resistance value of the resistance element Rv (2) in the second stage is set to be smaller than the resistance value of the resistance element Rv (3) in the third stage, and the resistance of the resistance element Rv (1) in the first stage is -40. National Standard (CNS) A4 specification (210 X 297 mm) 526465 A7 B7 5. Description of the invention (37) The value is set to be greater than the resistance value of the resistance element Rv (2) in the second stage. Similarly, the resistance value of the resistance element RS (2) in the second stage is set to be smaller than that of the resistance element R s (3) in the third stage, and the resistance value of the resistance element R s (1) in the first stage is set to be greater than The resistance value of a segment of the resistance element rs (2). Fig. 2 shows that the number of inverter segments in AMP 17 is divided into three segments, but the number of segments is not particularly limited, and may be an odd segment with more than three segments. For example, when (2n + l) segments of inverters are connected vertically in AMP 17 (η is an integer of 1 or more), the resistance elements Rv (l) connected to the power terminals of the inverters of each segment are separately Rv (2n + 1) satisfies the following relationships:

Rv (2n) ^ Rv (2n + 1)

Rv (2n- 1) ^ Rv (2n + 1)

Rv (2) ^ Rv (2n + 1)

Rv (1) ^ Rv (2) Or, the resistance elements R s (1) to R s (2 η + 1) connected to the ground terminals of the inverters of each segment respectively satisfy the following relationship: Rs (2n ) ^ Rs (2n + l)

Rs (2n-l) ^ Rs (2n + 1)

Rs (2) ^ Rs (2n + 1)

Rs (1) ^ Rs (2) So, because of this embodiment, the resistance value of the resistance element of the power terminal or ground terminal of the inverter connected to each section in AMP 17 meets the above -41-This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 male I) 526465 A7 B7 __ V. Description of the invention (38) The relationship of the formula, so the same effect as the twelfth embodiment can be obtained. That is, by adjusting the resistance value of each resistance element, the drive capability of the inverters in each stage can be optimally adjusted, and the accuracy and working speed of the AMP 17 are improved. (Fifteenth embodiment) A fifteenth embodiment is one in which each of the inverters in the AMP 17 is supplied with a separate power supply voltage. FIG. 8 is a circuit diagram of the AMP 17 in the signal line driving circuit of the fifteenth embodiment. Similarly to the AMP 17 of FIG. 24, the AMP 17 of FIG. 2 has three inverters IV1 to IV3 connected vertically. Each of the inverters IV1 to IV3 has first and second power terminals Vdd and Vss, respectively. Different types of power supply voltages XAVDD (l), XAVDD (2), and XAVDD (3) are supplied to the first power supply terminals Vdd of the inverters IV1 to IV3 of each stage. Similarly, different types of power supply voltages XAVSS (1), XAVSS (2), and XAVSS (3) are supplied to the second power supply terminals V s s of the inverters IV1 to IV3 of each stage. The power supply voltage XAVDD (2) supplied to the inverter IV 2 in the second stage is set to be larger than the power supply voltage XAVDD (3) supplied to the inverter IV3 in the last stage, and is supplied to the power voltage of the inverter IV1 in the first stage. XAVDD (l) is set to be smaller than the power supply voltage XAVDD (2) supplied to the inverter I V2 of the second stage. Alternatively, the power supply voltage XAVSS (2) supplied to the inverter IV2 in the second stage is set to be smaller than the power supply voltage XAVSS (3) supplied to the inverter IV3 in the last stage, and supplied to the inverter IV1 in the first stage. The power supply voltage XAVSS (l) is set to be greater than the power supply voltage supplied to the inverter IV2 of the second stage -42- This paper size is applicable to China National Standard (CNS) A4 specifications (210X 297 mm) 526465 A7 B7 V. Invention Explanation (39) XAVSS (2). Fig. 28 shows that the number of inverter stages in the AMP 17 is divided into three stages, but the number of stages is not particularly limited, and may be an odd stage with three or more stages. For example, when an inverter of (2n + 1) stages (η is an integer of 1 or more) is connected vertically in AMP 17, the power supply voltage XAVDD supplied to the first power terminal V dd of the inverter of each stage is respectively (l) ~ XAVDD (2N + 1) is set to satisfy the following relationship: XAVDD (2n) ^ XAVDD (2n + l) XAVDD (2n-l) ^ XAVDD (2n + l) • _ · XAVDD (2) ^ XAVDD (2n + l) XAVDD (1) ^ XAVDD (2) Or, set the power supply voltages XAVSS (l) to XAVSS (2N + 1) on the second power supply terminal V ss of each inverter The following relationships are satisfied: XAVSS (2n) ^ XAVSS (2n + l) XAVSS (2n-l) ^ XAVSS (2n + l) • · XAVSS (2) ^ XAVSS (2n + l) XAVSS (l) ^ XAVSS (2) In this way, since the power supply voltage to the inverters of each stage in the AMP 17 is individually adjusted in this embodiment, the driving capability of the inverters of each stage can be optimally adjusted to promote the accuracy and work of the AMP 17. Speed up. In addition, even if (Twelfth Embodiment Mode), (Thirteenth Embodiment Mode), (Fourteenth Embodiment Mode), or (Fifteenth Embodiment Mode) are used in combination, this paper standard applies to China National Standard (CNS) A4 specification (210X297 mm) 526465 A7 _____B7 V. Description of the invention (^) 40 7 The same effect can be obtained. Therefore, the drive capability of the inverters in each section can be optimally adjusted to promote AMP The accuracy and working speed of 17 are improved. (Sixteenth embodiment) The sixteenth embodiment is a parallel implementation of sampling of analog video signals and nesting of signal lines. FIG. 2 A is a circuit diagram of amp 17 in a signal line driving circuit of a sixteenth embodiment. The AMP 17 shown in FIG. 29A is an inverter in the initial stage with two first amplifying sections 31 connected in parallel. The first amplifying sections 3 丨 include: a series-connected switch S21, a capacitor element C6a, an inverter IVla, and a switch S22; and a switch s23 connected in parallel between the input and output terminals of the inverter IVla. These first amplification sections 31 are connected to the second amplification section 32. The second amplifier section 32 includes a capacitor element C4, an inverter IV2, a capacitor element c5, and an inverter IV3 connected in series. In addition, the phase compensation components shown in the second section of the inverter setup diagram i] are not shown on the diagram. As shown in FIG. 29B, the AMP 17 shown in FIG. 25 is arranged one by six signal lines, and the AMP 17 of this embodiment is arranged one by 12 signal lines. So each AMP 17 can reduce 2 inverters. FIG. 3A is a working timing diagram of the AMP 17 of this embodiment, and FIG. 30b is a working timing diagram of the AMP 17 of FIG. 25 for comparison. The AMP 17 in FIG. 5 performs the sampling and signal line writing of the analog video signal alternately, while the AMP 17 in this embodiment performs the sampling ^ broadcasting line writing in parallel. Therefore, without shortening the sampling period and the signal line writing period, the signal line can be driven several times as many as in FIG. Figure 3 1 is the peripheral circuit diagram of AMP 17, and shows dac K λ 'l 10, AMP 17 -44- This paper size applies to China National Standard (CNS) A4 specification (210X297 public love) &quot;' ------- -526465 A7

And signal line selection circuit DAC16 includes: analog switch a 32b, which is a unit corresponding to digital pixel data. … The value performs switching control ... The device element cu stores the charge corresponding to bit b 〇 · Tai Jiao cry_ μ 广-你 存 + # 儿 仃, Xungu state file c12, which stores the corresponding bits b0 ~ bk Charge; and switches S33a, S33b, s33c, S33ds34a, =, s34c, which perform the charge storage control of the capacitor elements C11, C12. FIG. 32 is an operation timing diagram of the circuit of FIG. 31. First, at time T1, the switches S33a, s33b, and s33e are turned on. As a result, the charges corresponding to the bits bG, b1 are stored in the capacitor elements C11'C12, respectively. After that, the charge at the corresponding position 丄 b 2 is stored in the capacitor element ㈣ at T2 ', S9a'. After that, at time T3, after the switches S33a, S33b, and 33 断开 are turned off, the switches are turned on between time T4 and T5. Thereby, redistribution of charges is performed among the capacitor elements C11, C12, and C6a. .

Thereafter, at time T6, the switches 810, sn are turned on, and so far, sampling of AMP 17 is performed. After that, the writing of the signal line is performed between times τ 9 to τ 丨 2. T In addition, at times T7 to T15, sampling of data to be written to the next signal line is performed in the same manner as times T1 to T8. Therefore, in this embodiment, the inverters in the first stage are connected in parallel, and the inverters IVla and IVlb are driven by the parent switching to perform data extraction and signal line writing in parallel. ’At this time, the power consumption of AMP 17 is based on the power supply voltage of AMP 17 χ &amp; Αι ^ -45-

526465 A7 B7 V. Description of the invention (42) 17 The current X AMP 17 quantity is expressed. Therefore, as shown in this embodiment, if the number of inverters constituting the AMP 17 is reduced, power consumption can be reduced. (Seventeenth Embodiment) The seventeenth embodiment is one in which the power supply voltage XAVDD for driving the AMP 17 is set to an integer multiple (for example, two times) of the power supply voltage V D D supplied by the power supply unit. The power supply voltage of LSIs such as power supply ICs is usually less than 3 V, but the driver circuit of the liquid crystal display TF device is used to '1) drive liquid crystal materials, or 2) boost the voltage to an appropriate level in order to drive polysilicon with V th greater than LSI. The value is supplied to the signal line driver circuit. For example, the most popular twisted nematic liquid crystals need to be driven in a voltage range of about 4 V. The required voltage for driving polycrystalline silicon requires the maximum sum of the Vth (absolute value) of the P-channel TFT and the N-channel. FIG. 3 shows a circuit diagram of a booster circuit included in the power supply IC of FIG. 2. This booster circuit generates a power supply voltage XAVDD that boosts the power supply voltage V D D supplied from the outside by two times. The generated power voltage XAVDD is used to drive the AMP 17. The boost circuit in FIG. 3 includes: switches SWla, SW2a, which are connected in series between the IN (+) terminal and OUT (+) terminal; a capacitor element C 1 3 and a switch SWlb, which are connected in series between the switches SWla, SW2a Between the connection path and the IN (-) terminal; the capacitor element C14 is connected between the IN (+) terminal and the IN㈠ terminal; the switches SWlb, SW2b are connected in series between the two terminals of the capacitor C1 4; and Capacitor C15 is connected between the OUT (+) terminal and the OUT (-) terminal. First, turn on the switches SWla and SWlb to respond to the input voltage. 46- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 526465 A7 B7 V. Charge of the invention (43) V i η It is stored in the capacitor element C 1 3. Next, the switches la, lb are turned off, and the switches SW2a, SW2b are turned on. As a result, the capacitor element C13 is connected in series to the input voltage Vin. The capacitor element C13 stores a charge corresponding to twice the input voltage Vin, and the output voltage V0 is 2XVin. Although a booster voltage can be generated at any rate by connecting a resistor in the booster circuit of Fig. 33, when considering the power supply efficiency, it is advisable to generate a voltage that is an integer multiple of the input voltage as shown in Fig. 33. Therefore, in this embodiment, the power supply IC 4 generates a voltage XAVDD which is an integral multiple of the power supply voltage VDD. The power supply IC 4 is mounted on a display device formed on the glass substrate 2. The glass substrate 2 is formed using polycrystalline silicon TFT or the like in the same manner as the display device, or is mounted or formed on a substrate different from the glass substrate 2. In any case, since the booster circuit of FIG. 33 does not require an inductive element, it is easy to integrate in an LSI and on a glass substrate. As shown in Figure 34, in addition to the power supply voltage XAVDD for driving the AMP 17, the power supply IC 4 also generates a power supply voltage X VDD for driving digital circuit components in the display device and a reference voltage for D / A conversion. REFH, REFL. Due to the low power consumption of the digital circuit components, the requirements for the power electronic ink XVDD are also small. Therefore, in the present embodiment, in order to improve the efficiency of circuit design and the convenience of manufacture, the power supply voltage XVDD has the same voltage level as the power supply voltage XAVDD. In this way, since the seventeenth embodiment sets the power supply voltage XAVDI for driving the AMP 17 to an integer multiple of the power supply voltage VDD supplied from the outside, the driving ability and power efficiency of the AMP 17 can be improved. In addition, as the electricity that will be used to drive the digital circuit components in the display device -47- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm);

Line 526465 A7 B7 V. Description of the Invention (44) The source voltage XVDD is set to the same voltage level as the power supply voltage XAVDD, so the internal structure of the power supply IC 4 can be simplified. (Eighteenth embodiment) The eighteenth embodiment is a modification of the seventeenth embodiment, which can maintain a sufficient working range even if the Vth and other characteristics of the TFT constituting the AMP are deviated due to manufacturing variations, etc. Those who set each power supply voltage in such a manner as to minimize power consumption. Using polycrystalline silicon TFTs, the power consumption of liquid crystal display devices with DAC 16 and AMP 17 integrally formed on a glass substrate. The power consumption of AMP 17 and the voltage division resistor ladder 20 account for a large proportion. Since the AMP 17 operates at the same time as a continuous current flows into the inverter, it consumes a lot of power. In the structure of the power source I C 4, the boosting efficiency of the power source of the AMP 17 must be maximized. Therefore, XAVDD is formed to 5.5 V, which is twice VDD (2.75 V). In addition, since the power consumption of the voltage-dividing resistor ladder 20 can be expressed as the power / resistance value of the applied voltage, the voltage applied to the voltage-dividing resistor ladder 20 need not be too large. And the voltage deviation must be below 5%. When the voltage deviation is too large, the range of the applied voltage required for the liquid crystal drive cannot be ensured, resulting in insufficient contrast. The voltage applied to the liquid crystal exceeds a certain value, which affects the display of the intermediate gray scale. Therefore, one of the voltages applied to both ends of the voltage-dividing resistor ladder 20 is set to 0V (GND), and the other is set to 5v. The relationship between the external power supply voltage V D D, the power supply voltage XAVDD, the reference voltage maximum value REPH, and the reference voltage minimum value REFL supplied to the partial resistor ladder 20 has the relationship shown in Figs. The maximum value of the reference voltage REFH and the minimum value of the reference voltage REFL are reversed as the voltage level when the polarity is reversed -48- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 526465 A7 B7 V. DESCRIPTION OF THE INVENTION The reference voltages REF1, REF2 of (β) 45 are supplied to the voltage-dividing resistor ladder 20. When the voltage is set from the viewpoint of reducing power consumption, as shown in Fig. 3, the driving voltage of the signal line is in the range of 0.5 V to 4.5 V, which is inevitably biased to the 0 V side instead of the power supply voltage XAVDD. In order to ensure the output voltage of the AMP] 7 with respect to the deviation range of the power supply voltage of the AMP 17, it is advisable to make the resistance values of the power and ground wires of the inverter inserted into the AMP 17 asymmetric on the power line side and the ground line side. . The reason is as described in the tenth embodiment. By connecting the resistors Ra and Rb in FIG. 36, the same effect as that of the tenth embodiment can be achieved. In Figure 3, the resistance R a between the power terminal of each inverter connected to the AMP 17 and the power voltage line XAVDI), and the resistance R b between the ground terminal of each inverter and the ground line GND The resistance ratio is set to be asymmetric (eg R a: Rb = 2: 1). With this, even if the Vth deviation of the TFT is caused by the process of the polysilicon T F T substrate, the power consumption can be suppressed to a minimum and the operation can be stable. (Nineteenth embodiment) The nineteenth embodiment is such that the gate width W of the second stage inverter of the three inverters constituting AMP 17 is greater than the gate width W of the third stage inverter. . Generally speaking, the AMP 17 of the TAB-IC used to drive the signal line of the display device is designed to reduce the gate width of the components constituting the comparison circuit portion of the differential circuit as much as possible and to increase the gate width of the components of the output section, The AMP 17 of this embodiment is significantly different from general thinkers. The inventor tried the wrong result and found that it is particularly suitable for smaller display devices such as liquid crystal display devices for mobile phones and liquid crystal display devices for PDAs. -49- This paper size applies to China National Standard (CNS) A4 (210 X 297) Li); · Staple

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The relative relationship between the idle width of each segment of the inverter without knowing it. The so-called smaller type here refers to the drive load capacitance (capacitance per i signal line) as viewed from AMP Π, which is approximately less than 20 p F. When using polycrystalline stone TFT elements such as Vth and other components with large deviations in characteristics, when forming the AMP 17 for signal line driving, increasing the output section may not help to ensure the stability of the operation, but problems that easily lead to oscillation and ringing . The inventor found out this fact from the result of trial and error, and therefore found that it is appropriate to reduce the gate width of the TFT constituting the inverter of the last stage and increase the gate width of the second stage. As shown in FIG. 24 and the like, the AMP 17 is configured by sandwiching a capacitor element and connecting three inverters in the vertical direction. Therefore, the output of AMp 17 easily causes oscillation and ringing. As shown in FIG. 37, it takes time to reach a stable output (hereinafter, this time is referred to as the contraction time). Figure 38 shows that the gate width w 1 of the inverter in the first stage is equal to the gate width W 2 of the inverter in the second stage, and the gate width w 2 of the inverter in the second stage is changed to that in the third stage. When the ratio of the gate width W 3 of the inverter is W2 / W3, the change of the contraction time of the AMP U output is shown. As shown in the figure, it can be seen that within the range of W2 / W3 from 0 · 5 ~ 1 · 5, the larger the gate width W2 of the inverter in the second stage is greater than the gate width W3 of the inverter in the third stage, the more the shrinkage time short. Therefore, making the gate width w 2 of the inverter in the second stage larger than the gate width W 3 of the inverter in the third stage can further promote the stabilization of the operation of the AMP 17. (Twentyth Embodiment) A specific layout form of an AMP circuit suitable for a liquid crystal display device with a diagonal of 2 inches and 176 X 180 dots will be described below. -50- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm); binding

Line 526465 A7 B7 V. Description of Invention (47) FIG. 39 is a partial layout diagram of AMP 17 of FIG. 3. The reference symbols of the switches and components correspond to FIG. 3. In order to prevent oscillation and chattering, the figure is used as the phase compensation element before and after the inverter in the second stage. The resistive element uses N + doped polycrystalline seconds. The capacitive element is formed by the poly-crystal doped with N + and the father cross of the gate line layer. The signal line capacitance of the display device is 12 pF. The signal line resistance is 0.4 kD. The time constant of the driving load is 12 pF X 〇 8 kQ = 9.6 nsec. The phase compensation element has a resistance of 100 kQ and an electrostatic capacitance of 0.1 pF. The driving time of each signal line is 4 uS. In order to suppress the output voltage error caused by the penetration voltage of the analog switch, a penetration compensation switch is provided everywhere as in FIG. 9. Analog switches and inverters are complementary using p-channel T f T and N-channel TFT. In order to parasitic unwanted parasitic capacitances equally to the p-channel τρτ and N-channel TFT, it is necessary to minimize the influence and implement a symmetrical circuit configuration. The capacitive elements C1, C2, C3, and C6 used in the D / A conversion are formed at the intersection of the N + -doped polycrystalline silicon layer and the gate line layer. These capacitors should have the same electrostatic capacitance. The deviation of electrostatic capacitance is directly related to the error voltage of D / a conversion. For example, C 3 is also used at the intersection of a part of the signal line layer and the electrode line layer, and the same electrostatic capacitance as C 2 is maintained as much as possible. The resistances between the inverters and the power supply constituting AMP 17 use the symbols in Fig. 3, Rm = 360 Q (XAVDD side) / 220 Ω (XAVSS side), Rl == 70 Ω, R3 = 50 Ω, R2 = 35 Ω, R4 = 25 Ω. The brake width ratio of each inverter of AMP 17 is 1 ¥ 1: 1 乂 2: 1 ¥ 3 = 6: 6: 5. -51-This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) 48 526465 V. Description of the invention (One side of the car and two broken substrates, a cup of extremely color filter ^ m is formed Common polarity reversal drive. The other uncles, the four-to-four-four intercropping cycle of the element array section j,, 17 times, 777, are integrated to form a tweezer, 'spring drive circuit 5, scan mode 卩, 6, Let ’s take a couple of nights to drive the electric board. The low-temperature polycrystalline dream TFT array base-line drive circuit 5 is composed of 44 groups of 17 and Μ. Perform 4 D / A conversions and drive the signal line of the AMP 17 during the 7th week, and select the U signal line in order to execute the work number and the general structure of the spring drive private road 5. It is shown in Fig. 4. In addition, the liquid crystal display device of this embodiment includes the power supply IC4 and the LCD &amp; controller shown in Fig. 34, and operates with the power settings shown in Fig. 35 and Fig. 2 丨. With this structure, the low power consumption and the stability of AMp 17 are excellent, and there is no problem in the accuracy of d / a conversion, and a good display can be performed. For the deviation of Vth due to the manufacturing process, sufficient yield can also be ensured. In addition, the absolute Vth value of the N-channel TFT and the P-channel TFT can be changed from the minimum 0.5 V to 2.5 V. (Twenty-first embodiment) The twenty-first embodiment is to extend the writing time of the signal line. The overall structure of the twenty-first embodiment is the same as that of FIG. 1, The block structure of the signal line driving circuit is also the same as that in Fig. 2. The voltage dividing resistor ladder 2 in the signal line driving circuit 5 is composed of several resistance elements not shown in the series diagram. As shown in Fig. 2, the Piezoresistance ladder 20 for -52- This paper size applies to China National Standard (CNS) A4 (210 X297 mm) binding 526465

There are 3 kinds of reference voltages REn, Vm, REF2, and 9 kinds of reference voltages v 丨 ~ v 9 are obtained from the sections of the resistor elements. And Vm should be close to (REF1 + REF2) / 2. The power consumption of the resistance ladder can be expressed by (1 ^? 1々111) multiplication / (resistance between REF1 and Vm) + (Vm_REF2) multiplication / (resistance between v_ref2). For this reason, you can set the value Be minimized. The DAC 16 uses a reference voltage γη output from the voltage selection circuit 15.

'Generates a voltage corresponding to the order of 3 bits below the digital pixel data. Amplified by dac 16 &lt; AMP 17 and supplied to the signal line selection circuit η. The k-line selection circuit 8 pre-charges the signal line before supplying a voltage corresponding to A Mp 17 to the signal line. The precharge voltage uses the reference voltages vr i, vr 2 output from the voltage selection circuit 15. Order

FIG. 42 is a circuit diagram showing a detailed structure of the DAC 16 and the AMp 17. As shown in the figure, the DAC 16 includes: a switch swu, which divides the digital pixel data = the uppermost bit of the lower 3 bits, corresponding to 2 bits m, 〇〇 selects any one of the reference = voltage Vrl ^ Vr2; switch SW12, which selects any one of the reference voltage Vn according to the highest-order bit value of the digital pixel data; and capacitor element (the first capacitor element) CP1, which can store every bit other than the highest-order bit of the digital pixel data Elementary charge, capacitor element (second capacitor element) CP2, which can be redistributed and stored with capacitor element cpi ^; capacitor element (third capacitor element) = 3 'It can store data corresponding to digital pixels The charge of the highest order bit value; the switch SWO, which is turned on when the charge corresponding to the lowest order bit D0 value of the digital pixel data is stored in the capacitor element cpi; the switch (first switching circuit) swi, which Whether to switch between capacitor elements?

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:: The redistribution of stored Tinghe '· switch SW2' is turned on when the charge corresponding to bit = is stored in capacitor element ⑶; switch (second cut = road) SW3, which is expected to respond to bit 〇2 The value of the charge is turned on when the capacitive state component CP3 is stored; and the switch (third switching circuit) sW4, which is used to switch whether to perform storage state redistribution between the capacitor elements CP2 and cp3. 17 packs of differential amplifiers 17a, switch ISP, which is connected between the reverse input terminal and output terminal of the differential amplifier 17a; and switch AFB, which is connected to the switch ISP and the signal line load 3 The connection point &amp; between the capacitor element CP3 and the switches SW3 and SW4. A capacitor element CP3 is connected to the reverse input terminal of the differential amplifier 17a, and a reference voltage Vw is supplied to the forward input terminal. The above-mentioned switches SWO ~ SW3, SW11, SW12, ISP, AFB, XSW are switched and controlled by the charge control circuit 31. Figure 43 is a timing diagram of the operation of the DAC 16. Hereinafter, the operation of the DAC 16 will be described with reference to the operation timing chart of FIG. At time U, when a loading signal is input, digital pixel data D 2 to D 0 are input into the DAC 16. Between time Q ~ t3, the switch SW0 is turned on, and the electric charge is stored in the capacitor element c p i in accordance with the bit value D 0 of the digital pixel data. Specifically, when the bit DO is 1, the charge corresponding to the reference voltage Vri is stored in the capacitor element CP1, and when the bit DO is 0, the charge corresponding to the reference voltage is stored in the capacitor &amp; element CP1. The capacitor_cp2 stores a charge corresponding to the reference voltage Vr2. Between time t3 ~ t4, the switch SW1 is turned on, and the capacitor element cpi, -54-This paper size applies to China National Standard (CNS) A4 specifications (210X 297 public directors) _ 526465 A7 B7

Description of the invention (The redistribution of charge is performed between ⑺. After that, at time &quot; seven, the switch SW2 is turned on, and the charge corresponding to the bit value of the digital pixel data is stored in the capacitor element CP1. "后 '于Between time t5 and t6, the switch SW1 is turned on to perform charge redistribution between the capacitor devices CP1 and CP2. As a result, the capacitors CP1 and CP2 store electric charges corresponding to the values of the bits D1 and D0. Previously, the switches AFB and XSW were in the ON state, corresponding to the voltage stored in the charge in the CP3 CP3, that is, the voltage vold corresponding to the previous digital pixel data was supplied to the signal line load 30. In addition, the 17 spokes The switch jsp between the input and output terminals is turned off, and ^ 7 is continuously supplied to the signal line before time t6. After that, between time t6 and t7, switch SW3 is turned on, corresponding to bit D: wide charge It is stored in the capacitor element cp3. In addition, the switch ISP is turned on instead of the switch AFB, and the XSW is turned off, and the threshold voltage of the AMp 17 is charged at the capacitor element CP3 and the right end is performed. In between, switch SW4 is turned on, whereby Redistribution of the stored charge is performed between the electric elements CP2 and CP3. As a result, the voltage VneW is formed in the capacitor elements CP2 and CP3. The electric charge corresponding to the bit iVp of the digital pixel data is formed. The ON state and the XSW are in the OFF state. Therefore, the voltage corresponding to the stored charge of the capacitor element CP3 is not output from AMP η. As described above, the corresponding pixel 'beit material bit D0 ~ Called a straight charge, the voltage Vn_charges the rain. At the right end of the capacitor element CP3, the working threshold voltage of trace 17 is -55-

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Charging, sampling of AMP 17 is completed. After time t 8, the switch IS P is turned off, the switch xsw, and AFB are turned on, and the voltage corresponding to the stored charge of the capacitor element C P 3 is supplied to the signal line and the load operation of 30 is performed. That is, through the analog switch a f b, before the feedback and the voltage at the left end of the private device CP3 equals Vnew, AMp 17 continues to sink a specific direction of current into the signal line load. 4 and 4 are timing charts of the operation of the signal line driving circuit 5 of this embodiment. At time tu, when the start pulse XST is supplied, the sampling flasher 13 sequentially latches the red odd pixels, and at the end of the latching of the red odd pixels in a horizontal column portion t 1 2, the loading latch 丨 4 integration level The odd red pixels in the column part, and the lock is asked at the same time. The input to the flash latch 14 is input to da (: 16, and the D / A conversion is performed. The sampling latch 13 and the red / odd pixel DAC 16 0 / eight conversion are performed side by side-the red even pixels in the horizontal column part After that, the sampling flasher 13 sequentially executes the latching of the horizontal row of knives, the odd-colored odd pixels, the green even-numbered pixels, the blue odd-numbered pixels, and the even-numbered pixels., || The signal line driving circuit 5 of this embodiment performs a flip-and-reverse drive that inverts the voltage of the common electrode in each horizontal period (1H)., Figure 4 and 5 show a roadmap. There is a circuit 5b as shown in the figure. ΗThe signal line driving circuit of the reverse driving is shared. The signal line driving circuit 5 is repeatedly set on the circuit 5b at a specific interval, and the sampling latch 13 latches the digital pixel data synchronously with the shifted temporary clock. 益 1 1 shift -56-

丨 · Binding

Line 526465 A7

Following the performance, the sampling latch 13 latches the latched data again after the level shift. In DAC 16, there is a higher-order 3 bit D / A. The reference voltage is selected based on the upper-order 3 bits of the latch data of the sampling latch 13. The lower-order 3 bit d / A uses the selected reference voltage to sample The lower 3 bits of latch data of latch 1 3 are D / A converted. The analog video signal after D / A conversion is sampled by the AMP 17, and then supplied to the corresponding signal line through the signal line selection circuit 18. · In this way, in this embodiment, the timing of the DAC 16/8 conversion operation / and the sampling operation of the AMP 17 are partially repeated to ensure a sufficient signal line nesting time. Therefore, several signal lines can also share DAC 16 and AMP 17, which can reduce the circuit scale. The above description only uses the signal line driving circuit 5 of the liquid crystal display device (DAC 16 as an example to describe the sun and the moon, but the digital analog conversion circuit of the present invention can also be applied to various materials. In addition, the signal line The driving timing of the driving circuit 52 is not limited to that shown in Fig. 44. In addition, the signal line driving Honglu 5 &lt; the polarity inversion driving can also use other methods than the H shared inversion driving '. In addition, the AMP 17 can also use other than a differential amplifier. For example, it can be an inverter composed of a p-channel transistor and an n-channel transistor connected in series between the power sources. In this case, there is no Vref terminal. The circuit of the DAC 16 is formed as shown in Fig. 46. The capacitor element cp3 of Fig. 46 has a voltage sampled from the capacitor element cp3 between time t, 7 and t8 from Fig. 43. After the time t8, the analogy is obtained by analogy. Switch AFB input to the capacitor [μ (contrary to the signal line potential comparison function of the comparator. In addition, in order to improve ^ -57- 526465 A7 __ B7 ____ V. Description of the invention () 54 17 voltage output accuracy, Qinlian Using several comparators In addition, as shown in Fig. 46, the phase compensation components shown in Figs. 10 to 3 are arranged in the inverter in the middle of the three inverters in series to ensure the stability of the AM p circuit. As described above. Explanation of element symbols 1: Pixel array section 2: Glass substrate

3: Controller I C

4: Power IC 5: Signal line drive circuit 6: Scan line drive circuit 7: Sequential circuit 1 1: Shift register 1 2: Data bus 1 3 Sampling interrogator 1 4: Load latch 1 5: Voltage selection circuit 16 ·· D / A converter (DAC) 1 7: Amplifier (AMP) 1 8: Signal line selection circuit 1 9: Sequence control circuit 2 〇: Voltage-dividing resistor ladder 2 1: Data distribution Circuit 2 2: Pre-charge control circuit -58-

526465 A7 B7 V. Description of the invention (55) 23 Common electrode 3 1 First enlargement section 3 2 Second enlargement section -59- This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

Claims (1)

526465 Patent application scope ABCD ι · A display device comprising: a signal line and a scanning line 'which are arranged vertically and horizontally on an insulating substrate. A fork which is formed on each of the above-mentioned signal line and scanning line's respective scanning line driving circuits' which Driving the aforementioned scanning lines; and a signal line driving circuit for driving the signal line formed on the insulating substrate; and the aforementioned signal line driving circuit includes: an amplifier 'which magnifies an analog image Signal; and a signal line selection circuit, which selects signal lines to be amplified by the aforementioned amplifier &lt; analog video signal supply target; the aforementioned amplifier includes: · an odd number of inverters connected vertically; a first capacitor element, which is respectively Connected between the aforementioned inverter, the input terminal of the aforementioned inverter in the initial stage and the output terminal of the aforementioned inverter in the final stage; the first power supply line, which supplies the power voltage to the aforementioned inverter in the initial stage ; And (1) a power supply line, which is the aforementioned inverter that supplies the power supply voltage to the initial stage. 2. The display device according to item 1 of the patent application scope, which includes an impedance element individually inserted into the aforementioned first and second power supply wires. 3 · —A display device including: -60- This paper size is applicable to China National Standard (CNS) Α4 specification (210 X 297 mm) 526465 Apply for patent Fanyuan A BCD signal line and scanning line, which is a vertical plate-; from the μ μ, is listed on the insulating substrate · Obvious parts, which are formed on the front plate, near the fork; 0 Know the cross-scanning line driving circuit of the drawing line, which is a scanning line; and k, and spring driving circuits, which are the aforementioned signal lines; Forced on the insulating substrate and described above The signal line driving circuit includes: a device that amplifies an analog video signal; and a U-selection circuit that selects a signal line that is subject to an analog (analog video signal supply); Analog switches,), and eight parallel-connected several corresponding to the same k-line of the above-mentioned age Galeb to switch on and off in the same direction. Each one-to-one ratio switch is controlled in the display device according to item 3 of the scope of the patent application, wherein each of the aforementioned signal lines' includes an impedance element inserted between the aforementioned analog switches corresponding to the aforementioned signal lines. A display device includes: a signal line and a scanning line, which are arranged vertically and horizontally on an insulating substrate; a display unit, which is formed near each intersection of the signal line and the scanning line; an analog switch, which is formed on On the aforementioned insulating substrate; and an analog switch for penetration compensation, which is connected to at least a part of each of the aforementioned analog switches, and is controlled to be bound in the opposite direction to the corresponding analog switch 5. m -61-々, the scope of patent application is on And open. The aforementioned analog switch for penetration compensation includes a pMOS transistor and an nMOS transistor in parallel, and the source and the drain of the two transistors are short-circuited. 6. A display device comprising: a signal line and a scanning line that are arranged vertically and horizontally on an insulating substrate; a display element that is formed near each intersection of the signal line and the scanning line; a scanning line driving circuit that Driving the aforementioned scanning lines; and a signal line driving circuit which drives the aforementioned signal lines formed on the insulating substrate; and the aforementioned signal line driving circuit comprises: an amplifier which amplifies an analog video signal; and a signal line selection circuit which It is a signal line selected by the analog video signal supply object amplified by the aforementioned amplifier; the aforementioned amplifier includes: a power line and a ground line; three inverters connected in a vertical direction; a resistance element which is provided in the aforementioned inverter and the aforementioned power source Between the wires; the resistance element is provided between the inverter and the ground line; the first capacitor element is connected between the input terminal of the inverter in the previous section and the output of the inverter in the last section Between terminals; Switching circuit, which is set in the inverter in the previous paragraph, can be used in this paper size National Standard (CNS) A4 specification (210 X 297 mm) 526465 VI. Whether the patent application scope is changed to a short circuit between the input and output terminals of the inverter in the initial stage; and the π phase compensation impedance element, which is inserted into the second Between the input and output terminals of the aforementioned inverter. 7. The display device according to item 6 of the patent application park, wherein the aforementioned amplifier includes: a capacitor element 'which is connected between the three inverters connected in the longitudinal direction; and a knife-for-private circuit, which is provided respectively In the aforementioned three inverters, it can be changed whether or not a short is formed between the input and output terminals of the corresponding inverter. If the display device of the patent application No. 6 is used, the resistance of the phase compensation impedance element is described. The sum of the value and the capacitance value is approximately the value of the product of the signal line load capacitance and the signal line resistance. 9. The display device according to item 6 of the scope of patent application, wherein the value of the inverter (gate width / length) in the second stage is larger than that in the third stage. 10 · A display device comprising: an insulating substrate, which includes: a signal line and a scanning line, which are arranged in a vertical and horizontal manner, and which are formed near the intersection of the signal line and the scanning line; The tracing driving circuit drives the scanning and signal line driving circuit, which drives the aforementioned signal line formed on the aforementioned insulating base; and the opposite substrate, which is disposed oppositely on the aforementioned insulating substrate, and -63- paper standard Applicable to China National Standard (CNS) A4 specification (210X297 male I) 526465 AB c D 々, the patent application scope has a common electrode; and the aforementioned signal line drive circuit includes: an amplifier, which amplifies analog video signals; and a signal line selection circuit It is a signal line that selects the analog image signal supply object amplified by the amplifier; the amplifier has an odd number of inverters connected vertically, near the voltage at which the slope of the voltage-illuminance characteristic curve of the display element is the largest, so that each reverse direction The gain of the device is the largest. 11. For example, the display device of the scope of application for patent No. 10, wherein the aforementioned amplifier is constituted by connecting an odd number of inverters, and the aforementioned inverters are pMOS transistors each connected between the first and second power supply voltages. And nMOS transistor phase complementary inverter. 12. A display device comprising: a signal line and a scanning line arranged horizontally on an insulating substrate; a display element formed near each intersection of the signal line and the scanning line; a scanning line driving circuit, It is for driving the aforementioned scanning lines; and a signal line driving circuit for driving the aforementioned signal lines formed on the aforementioned insulating substrate; and the aforementioned signal line driving circuit includes: an amplifier which amplifies analog video signals; and a signal line selection circuit, It is a signal line that selects the target of analog image signal amplified by the amplifier; the amplifier includes: -64- This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) 526465 A8 B8 The longitudinal sentence connects &lt; (2n + 1) paragraphs (and n A jw 'only (with n being an integer greater than 1) is the reverse of; and f container elements, which are respectively connected to the aforementioned (2n + 1) paragraphs Between the &amp; between the inverse state and the input terminal of the aforementioned inverter and the output terminal of the aforementioned inverter in the last paragraph; each of the aforementioned inverters constituting paragraphs:-to 2 n The size of the transistor is larger than the size of the transistor of the aforementioned inverter in the final stage, and the size of the transistors of the aforementioned inverter in the initial stage is smaller than the size of the transistor of the aforementioned inverter in the second stage. The display device according to item 2 of the patent application scope, wherein the size of the aforementioned transistor is the ratio of the gate length to the gate width of the transistor. 14. A display device comprising: a signal line and a scanning line, which are vertical and horizontal Arranged on an insulating substrate; a display element formed near each intersection of the aforementioned signal lines and scanning lines; a scanning line driving circuit that drives the foregoing scanning lines; and a #number line driving circuit which is formed by driving the aforementioned The aforementioned signal lines on the insulating substrate; and The aforementioned signal line driving circuit includes: an amplifier, which amplifies analog video signals; and a signal line selection circuit, which selects a signal line to be supplied by the analog video signal amplified by the aforementioned amplifiers; the aforementioned amplifiers include: 65- Applicable to this paper standard China National Standard (CNS) A4 (210 X 297 mm) Pretend 526465 A8 B8 C8 D8 Patent application scope Power line and ground line; Vertically connected (2n + 1) segments (where n is an integer greater than i); Capacitor elements, which are respectively connected to the aforementioned (2n + 1) ) Between the segments of the inverter, the input terminals of the aforementioned inverter in the initial stage, and the output terminals of the aforementioned inverter in the final stage; and several impedance components, which are respectively connected to the power line and the aforementioned odd number Inverters; the impedance values of the aforementioned impedance elements connected to the aforementioned inverters in the second to 2 n stages are smaller than the impedance values of the aforementioned impedance elements connected to the aforementioned inverters in the last stage, and are connected to the initial stage The impedance value of the aforementioned blocking element of the aforementioned inverter is greater than the impedance value of the aforementioned impedance element connected to the aforementioned inverter of the second stage. 15 · A display device comprising: a signal line and a scanning line arranged vertically and horizontally on an insulating substrate, and a display element formed near each intersection of the signal line and the scanning line; a scanning line driving circuit, It is for driving the aforementioned scanning lines; and a signal line driving circuit for driving the aforementioned signal lines formed on the front substrate; and the aforementioned signal line driving circuit includes a latch circuit which latches digital pixel data; D / A converter, which replaces the interlocking input of the aforementioned interlocking circuit with an analog image signal; -66- AB c D 526465 6. A patent-pending amplifier that amplifies the analog video signal converted by the aforementioned D / A converter; and / a signal line selection circuit that selects the target of the analog video signal amplified by the aforementioned amplifier. Signal line; the amplifier includes: a vertically connected (2n + 1) segment (where η is an integer of 1 or more); and a capacitor element connected to the inverter (2η + 1) segment Between the segments, between the input terminal of the aforementioned inverter in the initial stage and the output terminal of the aforementioned inverter in the final stage; the inverter of the aforementioned (2n + 1) stage has first and second power terminals, respectively; At least one of the first and second power terminals is supplied with a different reference voltage for each inverter in the aforementioned (2η + 1) stage, and is supplied to each of the aforementioned first and second inverters from the second stage to the 2η stage. The reference voltage of at least one of the second power terminals is greater than the reference voltage of at least one of the aforementioned first and second power terminals supplied to the inverter of the last stage, and is supplied to the aforementioned inverter of the first stage. Is of the first and second power supply terminal of the reference voltage is less than at least one of the second section is supplied to the inverse filter to one of said first and second power terminals of at least the reference voltage. 16. A display device comprising: a signal line and a scanning line, which are arranged vertically and horizontally on an insulating substrate; a display element, which is formed at the intersection of the aforementioned signal line and the scanning line. Standard (CNS) A4 (210 X 297 mm) 526465 A8 B8 This paper size applies the Chinese National Standard (cns) A4 specification (210X297 Public Director_y 526465 AB c D. Patent application scope. The aforementioned first amplifying sections include the first and second inverters connected in parallel. The aforementioned selecting section includes: A first switching section for switching whether to clamp the capacitor element and connecting the output terminal of the first inverter to the input terminal of the second amplifying section; a second switching section for switching whether to clamp the capacitor element, The input terminal of the first inverter is connected to the output terminal of the second amplifier; the third switching unit is used to switch whether to clamp the capacitor element, and to connect the output terminal of the second inverter to the second An input terminal of the amplifying section; and a fourth switching section that switches whether to clamp the capacitor element and connects the input terminal of the second inverter and the output terminal of the second amplifying section; the amplifier is in the signal line selection circuit When the signal line writing is performed, a closed loop including the foregoing first inverter is formed alternately with a sealing including the foregoing second inverter 18. The display device according to item 16 of the scope of patent application, wherein after the second or fourth switching section is turned on, one of the first and second inverters is supplied to the second amplification section. , To switch on the first or third switching unit, and then supply the analog video signal to be written to the other of the first and second inverters. 19 A display device including: China National Standard (CNS) A4 specification (210X 297 mm) 526465 Patent application signal lines and scanning lines, which are arranged vertically and horizontally on an insulating substrate; display elements' which are formed at the intersection of the aforementioned signal lines and scanning lines Near the point; a scanning line driving circuit that drives the aforementioned scanning lines; a signal line driving circuit that drives the aforementioned signal lines formed on the aforementioned insulating substrate; and a packet source private pressure generating circuit based on the first A power source is pressed to generate a second power source voltage having a voltage level that is approximately an integer multiple of the first power source voltage; and the aforementioned signal line drive circuit includes an amplifier. A device for amplifying an analog image signal; and a signal line selection circuit for selecting a signal line to be supplied by the analog image signal amplified by the aforementioned amplifier and performing signal line nesting; as described above, the amplifier is powered by the aforementioned second power source Voltage driving. 20. If the display device of item 19 of the scope of patent application is applied, the digital circuit components in the aforementioned signal line drive circuit of the front and the first are driven by electric power and ink of the first power supply. 21. If the scope of application of patent is 19 The display device of the above item, wherein the aforementioned amplifier includes: a capacitor element, which is respectively connected between the three segments connected in the longitudinal direction; an inverse short-cut switching circuit, which is respectively provided in the aforementioned three inverters. Correspondence between the input and output terminals of the corresponding inverter -70- This paper is compliant with M1® Home Standard (CNS) A4 specifications (2i0x297, "AB c D 526465 々, patent application range; first impedance Component, which is connected between the aforementioned second power line and each of the first power terminals of the aforementioned odd number of inverters; and a second impedance element, which is connected to the connection Between the respective second power supply terminal potential line and the number of odd inverter, and the impedance is less than the first impedance element. 22. —A digital analog conversion circuit that outputs digits corresponding to η (η is an integer greater than 2) based on a first reference voltage and a second reference voltage whose voltage level is lower than the first reference voltage. The voltage of the signal includes: a first capacitor element that can store electric charges corresponding to the values of the bits other than the uppermost bit of the digital signal; a second capacitor element that can be charged between the first capacitor element and the first capacitor element; Redistribution of stored charge; a third capacitor element that can store the charge corresponding to the highest order bit value of the aforementioned digital signal; and a charge control circuit that sequentially stores the highest value corresponding to the aforementioned digital signal in the aforementioned first capacitor element The charge of each bit value other than the order bit, the bits other than the uppermost order bit of the aforementioned digital signal are repeatedly executed to perform the redistribution process of the stored charge between the second capacitor element and the corresponding digital signal. The charge of the highest order bit value is stored in the third capacitor element, and thereafter, the second capacitor element and the Redistribution of stored charges is performed between the third capacitor elements. -71-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 526465 A8 B8 C8 D8 6. Application scope of patent 23. For example, the digital analog conversion circuit of item 22 of the scope of patent application includes: a first switching circuit which switches whether to switch between the aforementioned first capacitor element and the aforementioned second capacitor element Redistribution of stored charges between the two; a second switching circuit that switches whether to store charges corresponding to the highest order bit value of the aforementioned digital signal in the third capacitor element; and a third switching circuit that switches whether Redistribution of stored charge between the second capacitor element and the third capacitor element; the charge control circuit stores bits corresponding to the bits in the first capacitor element other than the highest order bit of the digital signal After the value of the charge, the first switching circuit is turned on, the redistribution of the stored charge is performed between the first capacitor element and the second capacitor element, and the second switching circuit is turned on, and the third capacitor element is turned on. Store the charge corresponding to the highest order bit value of the aforementioned digital signal, and then turn on the aforementioned A third switching circuit performs redistribution of stored charges between the second capacitor element and the third capacitor element. 24. For example, the digital analog conversion circuit of item 23 of the scope of patent application includes: a fourth switching circuit that switches whether to store a charge corresponding to the second reference voltage in the second capacitor element; the aforementioned charge control circuit When the charge corresponding to the lowest-order bit of the digital signal is stored in the first capacitor element, the fourth switching circuit is turned on, and the charge corresponding to the second reference voltage is stored in the second capacitor element. 25. For example, the digital analog conversion circuit in item 23 of the scope of patent application, which includes: -72- Feng paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) Decoration AB c D 526465 6. The patent-applied amplifier is to supply the voltage to the load capacitor in the second period in a way that the voltage of the load capacitor is equal to the voltage of the stored charge of the third capacitor element in the first period. And a fifth switching circuit that switches whether to short-circuit the input and output terminals of the amplifier; the charge control circuit stores bits corresponding to the bits in the first capacitor element other than the uppermost bit of the digital signal; After the charge of the element value is turned on, the first switching circuit is turned on, and the stored charge is redistributed between the first capacitor element and the second capacitor element. After that, the second switching circuit is turned on, and the third capacitor is turned on. The charge corresponding to the highest order bit value of the digital signal is stored in the element, and then the third switching circuit is turned on to perform the redistribution of the stored charge between the second capacitor element and the third capacitor element, and The second switching circuit is turned on and the third switching circuit is turned on. The fifth switching circuit is turned on, the input of the amplifier output terminal short-circuited. 26. The digital analog conversion circuit according to item 23 of the patent application scope, comprising: a sixth switching circuit that switches whether to supply the output of the amplifier to a load; and a seventh switching circuit that is connected to the sixth switch The connection point between the circuit and the load, and the connection point between the second switching circuit and the third capacitor element; the charge control circuit, except for the period during which the second switching circuit is turned on and the period during which the third switching circuit is turned on In addition, the above-mentioned sixth and -73- paper sizes are applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm) 526465 The patent application Fanyuan 7 switching circuit supplies the voltage of the second switching secondary slave connection point to the load third capacitor unit. A display device includes a number of switching elements near the point; Cross-signal line drive circuit of Qin, Quan and Sweep wires, which are drive signal lines; f plug-line drive circuit 'which is drive scan line; then the signal line drive circuit is converted into analogy for analogy: ·', information The digital signal-to-bit ratio conversion circuit, the number of the digital item in the patent Fanyuan No. 22 is as described in the digital analog conversion two lines. The output of the changeover circuit is supplied to the corresponding Xinshuangru: the display device of item 27 of the patent scope, which includes a reference voltage selection mechanism, which recognizes the image data of the two-action circuit. (2) To the aforementioned signal line element line, Weixincai, select two kinds of reference voltages based on the number of bits on the upper order bit side; and also select: the second and third capacitor elements store the two kinds of reference voltages selected according to the aforementioned reference voltage Of charge. A digital analog conversion method in China, which outputs the voltage between the first, that is, the voltage of the digital signal of the wheeler's office &amp; / Jian, and the electric signal corresponds to n (n is an integer greater than 2). According to the above-mentioned capacitor factors, the charge of each element value other than the order bit, the elements other than the previous' κ μ 疋 are repeatedly executed in the 27th. Bit-74- The size of this paper ___ Tear A BCD 526465 々, the redistribution of stored charge is performed between capacitor elements in the scope of patent application, and the charge corresponding to the highest order bit value of the aforementioned digital signal is stored in the Within the three capacitor elements, redistribution of stored charges is performed between the second capacitor element and the third capacitor element. -75- This paper size applies to China National Standard (CNS) A4 (210X 297mm)