Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F10/00—Individual photovoltaic cells, e.g. solar cells
  • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
  • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
  • H10F10/167—Photovoltaic cells having only PN heterojunction potential barriers comprising Group I-III-VI materials, e.g. CdS/CuInSe2 [CIS] heterojunction photovoltaic cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
  • H10F19/30—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
  • H10F19/31—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
  • H10F19/30—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
  • H10F19/31—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
  • H10F19/33—Patterning processes to connect the photovoltaic cells, e.g. laser cutting of conductive or active layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
  • H10F19/30—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
  • H10F19/31—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
  • H10F19/35—Structures for the connecting of adjacent photovoltaic cells, e.g. interconnections or insulating spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/10—Semiconductor bodies
  • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
  • H10F77/169—Thin semiconductor films on metallic or insulating substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/10—Semiconductor bodies
  • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
  • H10F77/169—Thin semiconductor films on metallic or insulating substrates
  • H10F77/1694—Thin semiconductor films on metallic or insulating substrates the films including Group I-III-VI materials, e.g. CIS or CIGS
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/10—Semiconductor bodies
  • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
  • H10F77/169—Thin semiconductor films on metallic or insulating substrates
  • H10F77/1696—Thin semiconductor films on metallic or insulating substrates the films including Group II-VI materials, e.g. CdTe or CdS
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/86—Series electrical configurations of multiple OLEDs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/80—Constructional details
  • H10K50/805—Electrodes
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/541—CuInSe2 material PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• This invention relates to optoelectronic devices and more particularly to mass-manufactura of optoelectronic devices such as solar cells.
• Optoelectronic devices can convert radiant energy into electrical energy or vice versa. These devices generally include an active layer sandwiched between two electrodes, sometimes referred to as the front and back electrodes, at least one of which is typically transparent.
• the active layer typically includes one or more semiconductor materials.
• a light-emitting device e.g., a light-emitting diode (LED)
• a voltage applied between the two electrodes causes a current to flow through the active layer.
• the current causes the active layer to emit light.
• a photovoltaic device e.g., a solar cell
• the active layer absorbs energy from light and converts this energy to electrical energy exhibited as a voltage and/or current between the two electrodes.
• TCO transparent conductive oxide
• ITO indium tin oxide
• a further problem associated with existing solar fabrication techniques arises from the fact that individual optoelectronic devices produce only a relatively small voltage. Thus, it is often necessary to electrically connect several devices together in series in order to obtain higher voltages in order to take advantage of the efficiencies associated with high voltage, low current operation (e.g. power transmission through a circuit using relatively higher voltage, which reduces resistive losses that would otherwise occur during power transmission through a circuit using relatively higher current).
• a further problem associated with series interconnection of optoelectronic devices arises from the high electrical resistivity associated with the TCO used in the transparent electrode.
• the high resistivity restricts the size of the individual cells that are connected in series.
• To carry the current from one cell to the next the transparent electrode is often augmented with a conductive grid of busses and fingers formed on a TCO layer.
• the fingers and busses produce shadowing that reduces the overall efficiency of the cell.
• the cells In order for the efficiency losses from resistance and shadowing to be small, the cells must be relatively small. Consequently, a large number of small cells must be connected together, which requires a large number of interconnects and more space between cells. Arrays of large numbers of small cells are relatively difficult and expensive to manufacture.
• shingling is also disadvantageous in that the interconnection of a large number of shingles is relatively complex, time-consuming and labor-intensive, and therefore costly during the module installation process.
• solar cells include cells with active absorber layers comprised of silicon (e.g. for amorphous, micro-crystalline, or polycrystalline silicon cells), organic oligomers or polymers (for organic solar cells), bi-layers or interpenetrating layers or inorganic and organic materials (for hybrid organic/inorganic solar cells), dye-sensitized titania nanoparticles in a liquid or gel-based electrolyte (for Graetzel cells), copper-indium- gallium-selcm ' um (for CIG solar cells), cells whose active layer is comprised of CdSe, CdTe, and combinations of the above, where the active materials are present in any of several forms including but not limited to bulk materials, micro-particles, nano-particles, or quantum dots.
• active absorber layers comprised of silicon (e.g. for amorphous, micro-crystalline, or polycrystalline silicon cells), organic oligomers or polymers (for organic solar cells), bi-layers or interpenetrating layers or inorgan
• FIG. 6A illustrates a portion of a prior art solar cell array 600.
• the array 600 is manufactured on a flexible insulating substrate 602.
• Series interconnect holes 604 are formed through the substrate 602 and a bottom electrode layer 606 is deposited, e.g., by sputtering, on a front surface of the substrate and on sidewalls of the holes.
• Current collection holes 608 are then formed through the bottom electrode and substrate at selected locations and one or more semiconductor layers 610 are then deposited over the bottom electrode 606 and the sidewalls of the series interconnect holes 604 and current collection holes 608.
• a transparent conductor layer 612 is then deposited using a shadow mask that covers the series interconnect holes 604.
• a second metal layer 614 is then deposited over the backside of the substrate 602 making electrical contact with the transparent conductor layer 612 through the current collection holes and providing series interconnection between cells through the series interconnect holes. Laser scribing 616, 618 on the front side and the back side separates the monolithic device into individual cells.
• FIG. 6B depicts another prior art array 620 that is a variation on the array 600.
• the array 620 is also manufactured on a flexible insulating substrate 622.
• Series interconnect holes 624 are formed through the substrate 622 and a bottom electrode layer 626 is deposited, e.g., by sputtering, on front and back surfaces of the substrate 622 and on sidewalls of the holes 624.
• Current collection holes 628 are then formed through the bottom electrode and substrate at selected locations and one or more semiconductor layers 630 and a transparent conducting layer 632 are then deposited over the bottom electrode 626 on the front side and on the sidewalls of the series interconnect holes 624 and current collection holes 628.
• a second metal layer 634 is then deposited over the backside of the substrate 622 using a shadow mask that covers everything except the current collection holes 628 making electrical contact with the transparent conductor layer 632.
• Laser scribing 636,638 on the front side and the back side separates the monolithic device into individual cells.
• the metal layers are deposited by sputtering, which is a vacuum technique. Vacuum techniques are relatively, slow, difficult and expensive to implement in large scale roll-to-roll manufacturing environments.
• the manufacturing process produces a monolithic array and sorting of individual cells for yield is not possible. This means that only a few bad cells can ruin the array and therefore increase cost.
• the manufacturing process is very sensitive to the morphology and size of the holes. Since the front to back electrical conduction is along the sidewall of the hole, making the holes larger does not increase conductivity enough. Thus, there is a narrow process window, which can add to the cost of manufacture and reduce yield of usable devices.
• vacuum deposition is practical for amorphous silicon semiconductor layers, it is impractical for highly efficient solar cells based, e.g., on combinations of Copper, Indium, Gallium and Selenium or Sulfur, sometimes referred to as CIGS cells.
• CIGS cells To deposit a CIGS layer, three or four elements must be deposited in a precisely controlled ratio. This is extremely difficult to achieve using vacuum deposition processes.
• FIG. IA is a vertical cross-sectional schematic diagram of a portion of an array of optoelectronic devices according to an embodiment of the present invention.
• FIG. IB is a plan view schematic diagram of the array of FIG. IA.
• FIGs. 1C- IE are plan view schematic diagrams illustrating alternative trace patterns for an optoelectronic device of the type shown in FIGs. 1 A-IB.
• FIG. 2 is a sequence of schematic diagrams illustrating fabrication of an array of optoelectronic devices according to an embodiment of the present invention.
• FIG. 3 is an exploded view schematic diagram illustrating fabrication of an array of optoelectronic devices according to an alternative embodiment of the present invention.
• FIG. 4A is an exploded view schematic diagram illustrating fabrication of an array of optoelectronic devices according to another alternative embodiment of the present invention.
• FIG. 4B is a cross-sectional schematic diagram illustrating a portion of the array of FIG. 4A.
• FIGs. 5A-5I are cross-sectional schematic diagrams illustrating formation of electrical contacts according to embodiments of the present invention.
• FIG. 6A is a cross-sectional schematic diagram of a portion of a solar cell array according to the prior art.
• FIG. 6B is a cross-sectional schematic diagram of a portion of an alternative solar cell array according to the prior art.
• FIGs. 1 A-IB illustrates an array 100 of optoelectronic devices according to an embodiment of the present invention. In some embodiments, this may be considered a series interconnection in an array 100 of optoelectronic devices,
• the array 100 includes a first device module 101 and a second device module 111.
• the device modules 101, 111 may be photovoltaic devices, such as solar cells, or light-emitting devices, such as light-emitting diodes. In a preferred embodiment, the device modules 101, 111 aie solar cells.
• the first and second device modules 101, 111 are attached to an insulating earner substrate 103, which may be made of a plastic material such as polyethylene terephthalate (PET), e.g., about 50 microns thick.
• PET polyethylene terephthalate
• the carrier substrate 103 may, in turn, be attached to a thicker structural membrane 105, e.g , made of a polymeric roofing membrane material such as thermoplastic polyolef ⁇ n (TPO) or ethylene propylene diene monomer (EPDM), to facilitate installing the array 100 on an outdoor location such as a roof.
• a thicker structural membrane 105 e.g , made of a polymeric roofing membrane material such as thermoplastic polyolef ⁇ n (TPO) or ethylene propylene diene monomer (EPDM)
• the device modules 101, 111 which may be about 4 inches in length and 12 inches wide, may be cut from a much longer sheet containing several layers that are laminated together.
• Each device module 101, 111 generally includes a device layer 102, 112 in contact with a bottom electrode 104, 114 and an insulating layer 106, 116 between the bottom electrode 104, 114 and a conductive back plane 108, 118.
• the back plane 108, 118 may be described as a backside top electrode 108, 118.
• the bottom electrodes 104, 114, insulating layers 106, 116 and back planes 108, 118 for substrates Si, S 2 on which the device layers 102, 112 are formed.
• the substrates are formed by depositing thin metal layers on an insulating substrate
• embodiments of the present invention utilize substrates Si, S 2 based on flexible bulk conducting materials, such as foils.
• bulk materials such as foils are thicker than prior art vacuum deposited metal layers they can also be cheaper, more readily available and easier to work with
• at least the bottom electrode 104, 114 is made of a metal foil, such as aluminum foil.
• copper, stainless steel, titanium, molybdenum or other suitable metal foils may be used.
• the bottom electrodes 104, 114 and back planes 108, 118 may be made of aluminum foil about 1 micron to about 200 microns thick, preferably about 25 microns to about 100 microns thick; the insulating layers 106, 116 may be made of a plastic foil material, such as polyethylene terephthalate (PET) about 1 micron to about 200 microns thick, preferably about 10 microns to about 50 microns thick.
• PET polyethylene terephthalate
• the bottom electrode 104,114, insulating layer 106, 116 and backplane 108, 118 are laminated together to form the starting substrates Si, S 2 .
• foils may be used for both the bottom electrode 104, 114 and the back plane 108, 118 it is also possible to use a mesh grid on the back of the insulating layer 106, 116 as a back plane.
• a grid may be printed onto the back of the insulating layer 106, 116 using a conductive ink or paint.
• a suitable conductive paint or ink is Dow Coming ® PI-2000 Highly Conductive Silver Ink available from Dow Corning Corporation of Midland Michigan, Dow Coming ® is a registered trademark of Dow Coming Corporation of Midland Michigan.
• the insulating layer 106, 116 may be formed by anodizing a surface of a foil used for the bottom electrode 104, 114 or back plane 108, 118 or both, or by applying an insulating coating by spraying, coating, or printing techniques known in the art.
• the device layers 102, 112 generally include an active layer 107 disposed between a transparent conductive layer 109 and the bottom electrode 104.
• the device layers 102, 112 may be about 2 microns thick.
• At least the first device 101 includes one or more electrical contacts 120 between the transparent conducting layer 109 and the back plane 108.
• the electrical contacts 120 are formed through the transparent conducting layer 109, the active layer 107, the bottom electrode 104 and the insulating layer 106.
• the electrical contacts 120 provide an electrically conductive path between the transparent conducting layer 109 and the back plane 108.
• the electrical contacts 120 are electrically isolated from the active layer 107, the bottom electrode 104 and the insulating layer 106.
• the contacts 120 may each include a via formed through the active layer 107, the transparent conducting layer 109, the bottom electrode 104 and the insulating layer 106.
• Each via may be about 0.] millimeters to about 1.5 millimeters, preferably 0.5 millimeters to about 1 millimeter in diameter.
• the vias may be formed by punching or by drilling, for example by mechanical, laser or electron beam drilling, or by a combination of these techniques.
• An insulating material 122 coats sidewalls Of 1 the via such that a channel is formed through the insulating material 122 to the back plane 108.
• the insulating material 122 may have a thickness between about 1 micron and about 200 microns, preferably between about 10 micions and about 200 microns.
• the insulating material 122 should preferably be at least 10 microns thick to ensure complete coverage of the exposed conductive surfaces behind it.
• the insulating material 122 may be formed by a variety of printing techniques, including for example inkjel printing or dispensing through an annular nozzle.
• a plug 124 made of an electrically conductive material at least partially fills the channel and makes electrical contact between the transparent conducting layer 109 and the back plane 108.
• the electrically conductive material may similarly be printed.
• a suitable material and method for example, is inkjet printing of solder (called "solderiet" by Microfab, Inc., Piano, Texas, which sells equipment useful for this memepose).
• the plug 124 may have a diameter between about 5 microns and about 500 microns, preferably between about 25 and about 100 microns.
• the device layers 102, 112 may be about 2 microns thick
• the bottom electrodes 104, 114 may be made of aluminum foil about 100 microns thick
• the insulating layers 106, 116 may be made of a plastic material, such as polyethylene terephthalate (PET) about 25 microns thick
• PET polyethylene terephthalate
• the backside top electrodes 108, 118 may be made of aluminum foil about 25 microns thick.
• the device layers 102, 112 may include an active layer 107 disposed between a transparent conductive layer 109 and the bottom electrode 104.
• at least the first device 101 includes one or more electrical contacts 120 between the transparent conducting layer 109 and the backside top electrode 108.
• the electrical contacts 120 are formed through the transparent conducting layer 109, the active layer 107, the bottom electrode 104 and the insulating layer 106.
• the electrical contacts 120 provide an electrically conductive path between the transparent conducting layer 109 and the backside top electrode 108.
• the electrical contacts 120 are electrically isolated from the active layer 107, the bottom electrode 104 and the insulating layer 106.
• the formation of good contacts between the conductive plug 124 and the substrate 108 may be assisted by the use of other interface-forming techniques such as ultrasonic welding.
• An example of a useful technique is the formation of gold stud-bumps, as described for example by J. Jay Wimer in "3-D Chip Scale with Lead-Free Processes" in Semiconductor International, October 1, 2003, which is incorporated herein by reference. Ordinary solders or conductive inks or adhesives may be printed on top of the stud bump.
• etching can be localized, e.g., by printing drops of etchant in the appropriate places using inkjet printing or stencil printing.
• a further method for avoiding shorts involves deposition of a thin layer of insulating material on top of the active layer 107 prior to deposition of the transparent conducting layer 109.
• This insulating layer is preferably several microns thick, and may be in the range of 1 to 100 microns. Since it is deposited only over the area where a via is to be formed (and slightly beyond the borders of the via), its presence does not interfere with the operation of the optoelectronic device.
• the layer may be similar to structures described in U.S. Patent Application Serial No. 10/810,072 to Karl Pichler, filed March 25, 2004, which is hereby incorporated by reference. When a hole is drilled or punched through this structure, there is a layer of insulator between the transparent conducting layer 109 and the bottom electrode 104 which may be relatively thick compared to these layers and to the precision of mechanical cutting processes, so that no short can occur.
• the material for this layer can be any convenient insulator, preferably one that can be digitally (e.g. inkjet) printed, Thermoplastic polymers such as Nylon PA6 (melting point (m.p.) 223 0 C), acetal (m.p. 165 0 C), PBT (structurally similar to PET but with a butyl group replacing the ethyl group) (m.p. 217°C), and polypropylene (m.p.165 0 C), are examples which by no means exhaust the list of useful materials. These materials may also be used for the insulating layer 122.
• Thermoplastic polymers such as Nylon PA6 (melting point (m.p.) 223 0 C), acetal (m.p. 165 0 C), PBT (structurally similar to PET but with a butyl group replacing the ethyl group) (m.p. 217°C), and polypropylene (m.p.165 0 C) are examples which by
• the vias it is useful to fabricate the optoelectronic device in at least two initially separate elements, with one comprised of the insulating layer 106, the bottom electrode 104 and the layers 102 above it, and the second comprised of the back plane 108. These two elements are then laminated together after the vias have been formed through the composite structure 106/104/102, but before the vias are filled. After this lamination and via formation, the back plane 108 is laminated Io the composite, and the vias are filled as described above.
• jet-printed solders or conductive adhesives comprise useful materials for forming the conductive via plug 124
• this plug by mechanical means.
• a wire of suitable diameter may be placed in the via, forced into contact with the back plane 108, and cut off at the desired height to form the plug 124, in a manner analogous to the formation of gold stud bumps.
• a pre-formed pin of this size can be placed into (lie hole by a robotic arm.
• Such pins or wires can be held in place, and their electrical connection to the substrate assisted or assured, by the printing of a very thin layer of conductive adhesive prior to placement of the pin. In this way the problem of long drying time for a thick plug of conductive adhesive is eliminated.
• the pin can have tips or serrations on it which punch slightly into the back plane 108, further assisting contact.
• Such pins may be provided with insulation already present, as in the case of insulated wire or coated wire (e.g. by vapor deposition or oxidation). They can be placed in the via before the application of the insulating material, making it easier to introduce this material. If the pin is made of a suitably hard metal, and has a slightly tapered tip, it may be used to form the via during the punching step. Instead of using a punch or drill, the pin is inserted into the composite 106/104/102, to a depth such that the tip just penetrates the bottom; then when the substrate 108 is laminated to this composite, the tip penetrates slightly into it and forms a good contact. These pins may be injected into the unpunched substrate by, for example, mechanical pressure or air pressure directed through a tube into which the pin just fits.
• One or more conductive traces 126 may be disposed on the transparent conducting layer 109 in electrical contact with the electrically conductive material 124. As shown in FIG. IB, the traces 126 may interconnect multiple contacts 120 to reduce the overall sheet resistance, By way of example, the contacts 120 may be spaced about 1 centimeter apart from one another with the traces 126 connecting each contact with its nearest neighbor or in some cases to the transparent conductor surrounding it. Preferably, the number, width and spacing of the traces 126 is chosen such that the contacts 120 and traces 126 cover less than about 1% of the surface of the device module 101.
• the traces 126 may have a width between about 1 micron and about 200 microns, preferably between about 5 microns and about 50 microns.
• the traces 126 may be separated by center-to-center distances between about 0.1 millimeter and about 10 millimeters, preferably between about 0.5 millimeter and about 2 millimeters. Wider lines require a larger separation in order to avoid excessive shadowing loss.
• a variety of patterns or orientations for the traces 126 may be used so long as the lines are approximately equidistant from each other (e.g., to within a factor of two).
• An alternative pattern in which the traces 126 fan out from the contacts 120 is depicted in FIG. 1C. In another alternative pattern, shown in FIG.
• the traces 126 form a "watershed" pattern, in which thinner traces 126 branch out from thicker traces that radiate from the contacts 120.
• the traces 126 form a rectangular pattern from the contacts 120.
• the number of traces 126 connected to each contact may be more or less than the number shown in FIG. IE. Some embodiments may have one more, two more, three more, or the like.
• the trace patterns depicted in the examples shown in FIG. IB, FIG. 1C, FIG. ID, and FIG. IE are for the purpose of illustration and do not limit the possible trace patterns that may be used in embodiments of the piesent invention.
• the conductive back planes 108, 118 cany electrical current from one device module to the next the conductive traces 126 can include "fingers” while avoiding thick "busses”. This reduces the amount of shadowing due to the busses and. also provides a more aesthetically pleasing appearance to the device array 100.
• the device modules 101, 111 may be between about 1 centimeter and about 30 centimeters long and between about 1 and about 30 centimeters wide. Smaller cells (e.g., less than 1 centimeter long and/or 1 centimeter wide) may also be made as desired.
• the pattern of traces 126 need not contain thick busses, as used in the prior art for this purpose. Instead, the pattern of traces 126 need only provide sufficiently conductive "fingeis" to carry current to the contacts 120. In the absence of busses, a greater portion of the active layers 102, 112 is exposed, which enhances efficiency. In addition, a pattern of traces 126 without busses can be more aesthetically pleasing.
• FIG. IB illustrates an example of one way, among others, for cutting back the back plane 118 and insulating layer 116.
• notches 117 may be formed in an edge of the insulating layer 116.
• the notches 117 align with similar, but slightly larger notches 119 in the back plane 118.
• the alignment of the notches 117, 119 exposes portions of the bottom electrode 114 of the second device module 111.
• Electrode contact may be made between the back plane 108 of the first device module 101 and the exposed portion of the bottom electrode 114 of the second device module 111 in a number of different ways.
• thin conducting layer 128 may be disposed over a portion of the carrier substrate 103 in a pattern that aligns with the notches 117, 119.
• the thin conducting layer may be, e.g., a conductive (filled) polymer or silver ink.
• the conducting layer can be extremely thin, e.g., about 1 micron thick.
• the first device module 101 may be attached to the carrier substrate 103 such that the back plane 108 makes electrical contact with the thin conducting layer 128 while leaving a portion of the thin conducting layer 128 exposed. Electrical contact may then be made between the exposed portion of the thin conducting layer 128 and the exposed portion of the bottom electrode 114 of the second device module 111.
• a bump of conductive material 129 e.g., more conductive adhesive
• the bump of conductive material 129 is sufficiently tall as to make contact with the exposed portion of the bottom electrode 114 when the second device module 111 is attached to the earlier substrate.
• the dimensions of the notches 117, 119 may be chosen so that there is essentially no possibility that the thin conducting layer 128 will make undesired contact with the back plane 118 of the second device module 111.
• the edge of the bottom electrode 114 may be cut back with respect to the insulating layer 116 by an amount of cutback CBi of about 400 microns.
• the back plane 118 may be cut back with respect to the insulating layer 116 by an amount CB 2 that is significantly larger than CBi.
• the device layers 102, 112 are preferably of a type that can be manufactured on a large scale, e.g., in a roll-to-roll processing system.
• the inset in FIG. IA shows the structure of a CIGS active layer 107 and associated layers in the device layer 102.
• the active layer 107 may include an absorber layer 130 based on materials containing elements of groups IB, IIIA and VIA.
• the absorber layer 130 includes copper (Cu) as the group IB, Gallium (Ga) and/or Indium (In) and/or Aluminum as group HIA elements and Selenium (Se) and/or Sulfur (S) as group VIA elements.
• Cu copper
• Ga Gallium
• In Indium
• Aluminum Aluminum
• Selenium Se
• Sulfur S
• Examples of such materials are described in US Patent 6,268,014, issued to Eberspacher et al on July 31, 2001, and US Patent Application Publication No. US 2004-0219730 Al to Bulent Basol, published November 4, 2004, both of which are incorporated herein by reference.
• a window layer 132 is typically used as a junction partner between the absorber layer 130 and the transparent conducting layer 109.
• the window layer 132 may include cadmium sulfide (CdS), zinc sulfide (ZnS), or zinc sclenide (ZnSe) or some combination of two or more of these. Layers of these materials may be deposited, e.g., by chemical bath deposition or chemical surface deposition, to a thickness of about 50 nm to about 100 nm.
• a contact layer 134 of a metal different from the bottom electrode may be disposed between the bottom electiode 104 and the absorber layer 130 to inhibit diffusion of metal from the bottom electrode 104. For example 5 if the bottom electrode 104 is made of aluminum, the contact layer 134 may be a layer of molybdenum.
• CIGS solar cells are described for the purposes of example, those of skill in the art will recognize that embodiments of the series interconnection technique can be applied to almost any type of solar cell architecture.
• solar cells include, but are not limited to: cells based on amorphous silicon, Graetzel cell architecture (in which an optically transparent film comprised of titanium dioxide particles a few nanometers in size is coated with a monolayer of charge transfer dye to sensitize the film for light harvesting), a nanostructured layer having an inorganic porous semiconductor template with pores filled by an organic semiconductor material (see e.g., US Patent Application Publication US 2005- 0121068 Al, which is incorporated herein by reference), a polymer/blend cell architecture, organic dyes, and/or C 6O molecules, and/or other small molecules, micro-crystalline silicon cell architecture, randomly placed nanorods and/or tetrapods of inorganic materials dispersed in an organic matrix, quantum dot-based cells, or combinations of the above.
• embodiments of the series interconnection include
• the optoelectronic devices 101, 111 may be light emitting devices, such as organic light emitting diodes (OLEDs).
• OLEDs include light-emitting polymer (LEP) based devices
• the active layer 107 may include a layer of poly (3,4) ethylendioxythiophene : polystyrene sulfonate (PEDOT:PSS), which may be deposited to a thickness of typically between 50 and 200 nm on the bottom electrodes 104, 114, e.g., by web coating or the like, and baked to remove water.
• PEDOT:PSS is available from Bayer Corporation of Leverkusen, Germany.
• a polyfluorene based LEP may then be deposited on the PEDOTiPSS layer (e.g., by web coating) to a thickness of about 60-70 nm.
• Suitable polyfluorene-based LEPs are available from Dow Chemicals Company.
• the transparent conductive layer 109 may be, e.g., a transparent conductive oxide (TCO) such as zinc oxide (ZnO) qr aluminum doped zinc oxide (ZnO:Al), which can be deposited using any of a variety of means including but not limited to sputtering, evaporation, CBD, electroplating, CVD, PVD, ALD, and the like.
• TCO transparent conductive oxide
• ZnO zinc oxide
• ZnO:Al aluminum doped zinc oxide
• the transparent conductive layer 109 may include a transparent conductive polymeric layer, e.g. a transparent layer of doped PEDOT (Poly-3,4-Ethylenedioxythiophene), which can be deposited using spin, dip, or spray coating, and the like.
• PEDOT Poly-3,4-Ethylenedioxythiophene
• PSS:PEDOT is a doped, conducting polymer based on a heterocyclic thiophene ring bridged by a diether.
• a water dispersion of PEDOT doped with poly(styrenesulfonate) (PSS) is available from H. C. Starck of Newton, Massachusetts under the trade name of Baytron ® P.
• Baytron ® is a registered trademark of Bayer Aktiengesellschaft (hereinafter Bayer) of Leverkusen, Germany.
• PSS :PEDOT can be used as a planarizing layer, which can improve device performance.
• PEDOT polystyrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-sulfon-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene-styrene
• the gap between the first device module 101 and the second device module 111 may be filled with a curable polymer epoxy, e.g., silicone.
• a curable polymer epoxy e.g., silicone.
• An optional encapsulant layer may cover the airay 100 to provide environmental resistance, e.g., protection against exposure to water or air.
• the encapsulant may also absorb UV-light to protect the underlying layers.
• suitable encapsulant materials include one or more layers of fluoropolymers such as THV (e.g.
• Dyneon's THV220 fluorinated terpolymer a fluorothermoplastic polymer of tetrafluoroethylene, hexafluoropropylene and vinylidene fluoride), Tefzel® (DuPont), Tefdel, ethylene vinyl acetate (EVA), thermoplastics, polyimides, polyamides, nanolaminate composites of plastics and glasses (e.g. barrier films such as those described in commonly- assigned, co-pending U.S.
• FIG. 2 illustrates one such method.
• the devices are fabricated on a continuous device sheet 202 that includes an active layer between a bottom electrode and a transparent conductive layer, e.g., as described above with respect to FIGs. 1A-1B.
• the device sheet 202 is also patterned with contacts 203 like the contact 120 depicted in FIG. IA.
• the contacts 203 may be electrically connected by conductive traces (not shown) as described above.
• An insulating layer 204 and a back plane 206 are also fabricated as continuous sheets. In the example shown in FIG.
• the insulating layer 204 has been cut back, e.g., to form notches 205 that align with similar notches 207 in the back plane layer 206.
• the notches in the back plane layer 206 are larger than the notches in the insulating layer 204.
• the device sheet 202, insulating layer 204 and back plane layer are laminated together to form a laminate 208 having the insulating layer 204 between the device sheet 202 and the back plane 206.
• the laminate 208 is then cut into two or more device modules A 3 B along the dashed lines that intersect the notches 205, 207.
• a pattern of conductive adhesive 210 (e.g., a conductive polymer or silver ink) is then disposed on a carrier substiate 211
• the modules are adhered to the carrier substrate 211.
• a larger area 212 of the conductive adhesive 210 makes electrical contact with the backplane 206 of module A.
• Fingers 214 of conductive adhesive 210 project out from the larger area 212.
• the fingers 214 align with the notches 205, 207 of module B.
• Extra conductive adhesive may be placed on the fingers 214 to facilitate electrical contact with the bottom electrode of module B through the notches 205, 207.
• the fingers 214 are narrower than the notches 207 in the back plane 206 so that the conductive adhesive 210 does not make undesired electrical contact with the back plane 206 of module B.
• first and second device modules A', B' may be respectively laminated from pre-cul device layers 302A, 302B, insulating layers 304A, 304B, and back planes 306A, 306B.
• Each device layer 302A, 302B includes an active layer between a transparent conducting layer and a bottom electrode.
• At least one device layer 302A includes electrical contacts 303 A (and optional conductive traces) of the type described above.
• the backplane layer 306B of module B has been cut back by simply making it shorter than the insulating layer 304B so that the insulating layer 304B overhangs an edge of the back plane layer 306B.
• the insulating layer 304B has been cut back by making it shorter than the device layer 302B or, more specifically, shorter than the bottom electrode of device layer 302B.
• FIGs. 4A-4B depict a variation on the method depicted in FIG. 3 that reduces the use of conductive adhesive.
• First and second device modules A", B" are assembled from pre-cut device layers 402A, 402B, insulating layers 404A, 404B and back plane layers 406A, 406B and attached to a earner substrate 408.
• Insulated electrical contacts 403A make electrical contact through the device layers 402A, a bottom electrode 405A and the insulating layer
• FIG. 4B Front edges of the insulating layer 404B and back plane 406B of module B" are cut back with respect to the device layer 402B as described above with respect to FIG 3.
• a back edge of the back plane 406A of module A" extends beyond the back edges of the device layer 402A and insulating layer 404A.
• the device layer 402B of module B" overlaps the back plane 406A of module A".
• a ridge of conductive adhesive 412 on an exposed portion 407A of the back plane 406A makes electrical contact with an exposed portion of a bottom electrode 405B of the device layer 402B as shown in FIG. 4B.
• individual modules may be fabiicated, e.g., as described above, and then sorted for yield.
• two or more device modules may be tested for one or more performance characteristics such as optoelectronic efficiency, open circuit voltage, short circuit current, fill factor, etc.
• Device modules that meet or exceed acceptance criteria for the performance characteristics may be used in an array, while those that fail to meet acceptance criteria may be discarded.
• acceptance criteria include threshold values or acceptable ranges for optoelectronic efficiency or open circuit voltage.
• FIGs. 5A-5H illustrate examples of how this may be implemented.
• a structure 500 (as shown in FIG, 5A) with a transparent conducting layer 502 (e.g., Al:ZnO, i:ZnO), an active layer 504 (e.g., CIGS), a bottom electrode 506 (e.g., lOOum Al), an insulating layer 508 (e.g., 50um PET), and a back plane 510 (e.g., 25um Al).
• a transparent conducting layer 502 e.g., Al:ZnO, i:ZnO
• an active layer 504 e.g., CIGS
• a bottom electrode 506 e.g., lOOum Al
• an insulating layer 508 e.g., 50um PET
• a back plane 510 e.g., 25um Al
• the back plane 510 is in the form of a thin aluminum tape that is laminated to the bottom electrode 506 using an insulating adhesive as the insulating layer 508. This can greatly simplify manufacture and reduce materials
• Electrical connection 512 may be made between the bottom electrode 506 and the back plane at one or more locations as shown in FIG. 5B, For example, a spot weld may be formed through insulating layer 508, e.g., using laser welding. Such a process is attractive by virtue of making the electrical connection in a single step.
• the electrical connection 512 may be formed through a process of drilling a blind hole through the back plane 510 and the insulating layer 508 to Hie bottom electrode and filling the blind hole with an electrically conductive material such as a solder or conductive adhesive.
• a trench 514 is then formed in a closed loop (e g., a ciicle) around the electrical connection 512.
• the closed-loop trench 514 cuts through the transparent conducting layer 502, active layer 504, and bottom electrode 506, to the back plane 510,
• the trench 514 isolates a portion of the bottom electrode 506, active layer 504, and transparent conductive layer 502 from the rest of the structure 500.
• Techniques such as laser machining may be used to form the trench 514. If laser welding forms the electrical connection 512 with one laser beam and a second laser beam forms the trench 514, the two laser beams may be pre-aligned with respect to each other from opposite sides of the structure 500. With the two lasers pre-aligned, the electrical connection 512 and trench 514 may be formed in a single step, thereby enhancing the overall processing speed.
• the process of forming the isolation trench may cause electrical short-circuits 511, 517 between the transparent conductive layer 502 and the bottom electrode 506.
• an isolation trench 516 is formed through the transparent conductive layer and the active layer to the bottom electrode 506 as shown in FIG. 5D.
• the isolation trench 516 su ⁇ ouiids the closed-loop trench 514 and electrically isolates the short circuits 511 on the outside wall 513 of the trench from the rest of the structure 500.
• a laser scribing process may form the isolation trench 516.
• a lesser thickness of material being scribed reduces the likelihood of undesired short circuits resulting from formation of the isolation trench 516.
• the insulating material 518 may be deposited in a way that provides a sufficiently planar surface suitable for forming the conductive fingers 520. Electrical contact is then made between the transparent conducting layer 502 in the nonisolated poitions outside the trench 514 and the back plane 510 through the fingers 520, the transparent conducting layer within the isolated portion, electrical shorts 517 on the inside wall of the trench 514, the portion of the bottom electrode 506 inside the trench 514 and the electrical connection 512. Alternatively, if. the shorts 517 do not provide sufficient electrical contact, a process of drilling and filling may provide electrical contact between the fingers 520 and the isolated portion of the bottom electrode 506. In an alternative embodiment depicted in FIGs.
• insulating material 518' covers the isolated portion when it is deposited as shown in FlG. 5G.
• the insulating material 518' covering the isolated portion may be removed, e.g., by laser machining or mechanical processes such as drilling or punching, along with corresponding portions of the transparent conductive layer 502 and the active layer 504 to expose the bottom electrode 506 through an opening 519 as shown in FIG. 5H.
• Electrically conductive material 520' forms conductive fingers, as described above. The electrically conductive material makes contact with the exposed bottom electrode 506 through the opening 519 and completes the desired electrical contact as shown in FlG. 51.
• the electrical connection 512 after the closed-loop trench has been formed and filled with insulating material.
• the process steps are simplified. It is easier to deposit the insulating layer without worrying about covering up the back plane.
• the process allows for a planar surface for depositing the fingers 520, 520'. Reliable electrical contact can be made between the bottom electrode 506 and the back plane 510 through laser welding. Furthermore, electrical shorts can be isolated without jeopardizing a 100% yield.
• Embodiments of the present invention facilitate relatively low cost manufacture of large-scale arrays of series-connected optoelectronic devices. Larger devices may be connected in series due to the reduced sheet resistance as a result of the connection between back planes and the transparent conducting layers through the contacts that penetrate the layers of the device modules. The conductive traces can further reduce sheet resistance. Larger devices can be arrayed with fewer connections.

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• 2005
  • 2005-08-16 US US11/207,157 patent/US7838868B2/en not_active Expired - Fee Related
• 2006
  • 2006-01-20 JP JP2007552312A patent/JP4794577B2/ja not_active Expired - Fee Related
  • 2006-01-20 EP EP06719145A patent/EP1849191A2/en not_active Withdrawn
  • 2006-01-20 WO PCT/US2006/002182 patent/WO2006078985A2/en not_active Ceased
• 2007
  • 2007-10-31 US US11/933,416 patent/US7919337B2/en not_active Expired - Fee Related
• 2008
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• 2010
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• 2011
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• 2012
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