WO2006059428A1 - 多層配線基板の製造方法 - Google Patents
多層配線基板の製造方法 Download PDFInfo
- Publication number
- WO2006059428A1 WO2006059428A1 PCT/JP2005/017926 JP2005017926W WO2006059428A1 WO 2006059428 A1 WO2006059428 A1 WO 2006059428A1 JP 2005017926 W JP2005017926 W JP 2005017926W WO 2006059428 A1 WO2006059428 A1 WO 2006059428A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- copper foil
- multilayer wiring
- wiring board
- stainless steel
- insulating layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000008569 process Effects 0.000 title claims abstract description 12
- 239000011889 copper foil Substances 0.000 claims abstract description 93
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 92
- 239000010410 layer Substances 0.000 claims abstract description 58
- 229910001220 stainless steel Inorganic materials 0.000 claims abstract description 31
- 239000010935 stainless steel Substances 0.000 claims abstract description 31
- 239000011888 foil Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 229920001721 polyimide Polymers 0.000 claims description 8
- 239000009719 polyimide resin Substances 0.000 claims description 7
- 238000000465 moulding Methods 0.000 abstract description 18
- 230000037303 wrinkles Effects 0.000 abstract description 3
- 230000006835 compression Effects 0.000 abstract 2
- 238000007906 compression Methods 0.000 abstract 2
- 238000005530 etching Methods 0.000 description 32
- 230000004888 barrier function Effects 0.000 description 10
- 239000004020 conductor Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000003825 pressing Methods 0.000 description 4
- 230000002378 acidificating effect Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000003373 anti-fouling effect Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 230000002087 whitening effect Effects 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
- B32B37/26—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer which influences the bonding during the lamination process, e.g. release layers or pressure equalising layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/08—PCBs, i.e. printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49163—Manufacturing circuit on or in base with sintering of base
Definitions
- the present invention relates to a method for manufacturing a multilayer wiring board that performs interlayer connection with bumps, and particularly relates to a technique for preventing sticking during molding (copper foil bonding).
- the invention described in Patent Document 1 relates to a selective etching method and a selective etching apparatus for forming a bump.
- a multilayer wiring circuit board manufacturing technique one of the main copper foils for forming a bump is used.
- a multilayer circuit board is formed by forming an etching noria layer on the surface and using a wiring circuit board forming member having a copper foil for forming a conductor circuit on the main surface of the etching barrier layer as a base and processing it appropriately.
- a technique for obtaining the above is disclosed.
- the copper foil of the wiring circuit board forming member is selectively etched to form bumps for interlayer connection, and the bumps are filled with an insulating layer. Insulate between.
- a copper foil for forming a conductor circuit is formed on the upper surface of the insulating layer and bumps.
- a wiring film is formed by selectively etching the upper and lower copper foils. As a result, a multilayer wiring board having upper and lower wiring films and having the wiring films connected by bumps is formed.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2003-129259
- the present invention has been proposed in view of such a conventional situation, and prevents sticking of a product after molding (copper foil sticking) to a stainless steel plate. It aims at providing the manufacturing method which can manufacture the multilayer wiring board excellent in dimensional stability, without producing. Another object of the present invention is to provide a method for producing a multilayer wiring board capable of ensuring adhesion between a copper foil to be bonded and a polyimide resin (insulating layer). [0013] In order to achieve the above-described object, the method of manufacturing a multilayer wiring board according to the present invention includes a step of forming an insulating layer on a base material on which bumps for interlayer connection are formed, and a stainless steel plate.
- a metal foil for example, copper foil
- the product multilayer wiring
- the substrate does not stick to the stainless steel plate. Therefore, the occurrence of unevenness, bending, distortion, curling, etc., which does not apply extra force to the product during disassembly after molding, is eliminated.
- no special tools are required for dismantling, and workability degradation is eliminated.
- the intervening metal foil serves as a cushioning material, and allows deformation of the copper foil to be bonded. Therefore, the copper foil is deformed following the slightly protruding bump, and the copper foil and the insulating layer are brought into close contact during the thermocompression bonding, thereby ensuring sufficient adhesion.
- FIG. 1 shows an example of a manufacturing process of a multilayer wiring board.
- the first stage is a sectional view showing a clad material
- the second stage is a sectional view showing a bump forming process
- the third stage is insulation.
- Sectional view showing the layer formation process Section 4 shows the copper foil placement process
- Section 5 shows the copper foil thermocompression bonding process (molding process)
- Section 6 shows the copper foil patterning It is sectional drawing which shows a process.
- FIG. 2 is a diagram showing a profile of temperature, pressure, and degree of vacuum in a thermocompression bonding process.
- FIG. 3 is a schematic diagram showing a state of sticking after thermocompression bonding.
- FIG. 4 is a cross-sectional view showing a superposed state of stainless steel plates in the embodiment.
- the etching barrier layer 2 has etching selectivity with respect to the copper foil 1, and becomes an etch stopper when the copper foil 1 is etched.
- the copper foil 3 is finally made into a wiring layer by patterning.
- the copper foil 3 also functions as a support for supporting the bumps formed by etching the copper foil 1 and the etching barrier layer 2. To do.
- the copper foil 1 is etched to form bumps 4.
- the etching of the copper foil 1 is preferably performed by a combination of etching with an acidic etching solution and etching with an alkaline etching solution. That is, after a resist film (not shown) serving as a mask is formed on the copper foil 1, an acidic etching solution (for example, salty cupric copper) is sprayed. The force with which the copper foil 1 is etched by this etching is carried out within the range where the etching depth by the acidic etching solution is shallower than the thickness of the copper foil 1 and the etching barrier layer 2 is not exposed.
- the remaining portion of the copper foil 1 is etched with an alkaline etching solution (for example, ammonium hydroxide).
- the alkaline etching solution hardly invades Ni constituting the etching barrier layer 2, and therefore the etching barrier layer 2 functions as a stopper for etching with the alkaline etching solution.
- the pH of the alkaline etching solution is preferably 8.0 or less.
- the insulating layer 5 is formed so as to fill the space between the bumps 4.
- the insulating layer 5 can be formed, for example, by applying a resin material such as polyimide or by thermocompression bonding a resin film.
- a resin material such as polyimide or by thermocompression bonding a resin film.
- the resin material used here it is not particularly necessary to consider adhesion to glass, glass transition point, linear expansion coefficient, etc. Any one can be selected according to necessary characteristics. Also, its thickness is not limited.
- the surface is polished so that the front end surface 4 a of the bump 4 is exposed, and a second wiring layer and a second wiring layer are formed thereon as shown in the fourth row in FIG. Arrange the copper foil 6 to be. Then, as shown in the fifth row in FIG. 1, the copper foil 6 is bonded onto the insulating layer 5 by thermocompression bonding.
- thermocompression bonding is performed by so-called thermocompression bonding.
- the laminated body shown in the fourth stage in FIG. 1 or the fifth stage in FIG. 1 is repeatedly arranged between, for example, stainless steel plates, and thermocompression bonding is performed collectively.
- the pressure during pressing is about 90 to 150 kgZcm 2 , and the pressing temperature is about 335 ° C.
- Figure 2 shows an example of the temperature profile, pressure profile, and vacuum profile during pressing (thermocompression bonding).
- the temperature is increased to 335 ° C and pressing is performed at a pressure of llOkgZcm 2 .
- the degree of vacuum is 1.3 kPa.
- FIG. 3 shows the product attached. As shown in FIG. 3, after thermocompression bonding, the copper foil 6 sticks to the stainless steel plate ST corresponding to the position where the bump 4 is formed. In Fig. 3, the point where sticking occurs is indicated by point p.
- a metal foil is interposed between the stainless steel plate 21 and the copper foil 6 to prevent the sticking.
- a copper foil 22 is interposed between the copper foil 3 and the stainless steel plate 21 as a support.
- cushion materials 23 are arranged on the outer sides of the outermost stainless steel plate 21, and are sandwiched between the press machines 24 through these.
- the copper foil 22 may be interposed between the copper foil 6 to be thermocompression bonded and the stainless steel plate 21. Further, the copper foil 22 between the copper foil 3 and the stainless steel plate 21 can be omitted.
- the copper foil 22 may be a metal foil made of any metal that is not necessarily a copper foil. However, it is preferable that the surface of the copper foil 22 (metal foil) to be used has releasability, that is, for example, a release layer is formed on the surface.
- the release layer in this case can be constituted by a fender layer formed on the surface of the copper foil 22, for example.
- Ni-Cr plating layer, Ni-Cr-Zn plating layer, etc. can be listed as the anti-corrosion layer.
- Sarakuko uses the oxide film formed on the surface of the copper foil 22 as the release layer. It can also be used.
- the conductor layers (copper foil 6 and copper foil 3) on both the front and back surfaces are patterned according to a desired wiring pattern, A wiring layer is used.
- the patterning can be performed by a normal photolithography technique and an etching technique. As a result, the force capable of obtaining a double-sided wiring board can be further increased.
- a barrier layer, an oxide layer, or the like formed on the surface of the copper foil 22 interposed between the stainless steel plate 21 and the copper foil 6 is a release layer.
- the product can be easily peeled off from the stainless steel plate 21 and can be disassembled with good workability without the need to use special tools.
- the copper foil 6 can be slightly deformed, which leads to improvement in the adhesion between the copper foil 6 and the insulating layer 5.
- the anti-corrosion treated copper foil 22 was interposed between the copper foil 6 and the stainless steel plate 21 during thermocompression bonding.
- the copper foil 22 used is 12 m thick and has a rope mouth file (3 m).
- the copper foil 3 was dealt with by leaving the antifouling treatment as it was on the surface facing the stainless steel plate 21.
- the copper foil 3 is subjected to a roughening treatment in order to adhere to the polyimide resin which is the insulating layer 5.
- a protective film was applied during the roughening treatment to leave an antifouling treatment.
- the finished product was strong with no creases, wrinkles, distortion, curl, unevenness, etc. due to sticking.
- This example is also an example in which a copper foil is interposed, as in the previous example, but in this example, as shown in FIG. They were interposed between the copper foil 6 and the stainless steel plate 21 and between the copper foil 3 and the stainless steel plate 21.
- the copper foil 22 used has a thickness of 12 m and a profile of about 5 ⁇ m.
- the finished product was strong without any folds, wrinkles, distortions, curls, irregularities or the like due to sticking.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Laminated Bodies (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020077013198A KR101168879B1 (ko) | 2004-12-03 | 2005-09-29 | 다층배선기판의 제조방법 |
US11/720,711 US8112881B2 (en) | 2004-12-03 | 2005-09-29 | Method for manufacturing multilayer wiring board |
EP05788279A EP1821588A4 (en) | 2004-12-03 | 2005-09-29 | PROCESS FOR MANUFACTURING A MULTILAYER CONDUCTOR PLATE |
CN200580041604XA CN101288349B (zh) | 2004-12-03 | 2005-09-29 | 多层布线基板的制作方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-352060 | 2004-12-03 | ||
JP2004352060A JP4761762B2 (ja) | 2004-12-03 | 2004-12-03 | 多層配線基板の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006059428A1 true WO2006059428A1 (ja) | 2006-06-08 |
Family
ID=36564868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/017926 WO2006059428A1 (ja) | 2004-12-03 | 2005-09-29 | 多層配線基板の製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8112881B2 (ja) |
EP (1) | EP1821588A4 (ja) |
JP (1) | JP4761762B2 (ja) |
KR (1) | KR101168879B1 (ja) |
CN (1) | CN101288349B (ja) |
TW (1) | TW200621105A (ja) |
WO (1) | WO2006059428A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2213148A4 (en) | 2007-10-10 | 2011-09-07 | Tessera Inc | ROBUST MULTILAYER WIRING ELEMENTS AND ASSEMBLIES INCLUDING MICROELECTRONIC ELEMENTS INCLUDED |
CN101626660B (zh) * | 2008-07-11 | 2012-08-29 | 惠阳科惠工业科技有限公司 | 结构不对称多层板铜面相靠压合工艺 |
WO2011037138A1 (ja) * | 2009-09-25 | 2011-03-31 | 住友化学株式会社 | 金属箔積層体の製造方法 |
KR101089986B1 (ko) * | 2009-12-24 | 2011-12-05 | 삼성전기주식회사 | 캐리어기판, 그의 제조방법, 이를 이용한 인쇄회로기판 및 그의 제조방법 |
KR101048597B1 (ko) * | 2010-05-25 | 2011-07-12 | 주식회사 코리아써키트 | 범프가 형성된 인쇄회로기판의 제조방법 |
TWI572261B (zh) * | 2014-10-29 | 2017-02-21 | 健鼎科技股份有限公司 | 線路結構及線路結構的製作方法 |
Citations (7)
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US5256474A (en) | 1986-11-13 | 1993-10-26 | Johnston James A | Method of and apparatus for manufacturing printed circuit boards |
JPH0946041A (ja) * | 1995-07-26 | 1997-02-14 | Toshiba Corp | 印刷配線板の製造方法 |
JPH1093242A (ja) * | 1996-09-18 | 1998-04-10 | Toshiba Corp | 印刷配線基板 |
JP2000196238A (ja) * | 1998-12-28 | 2000-07-14 | Shin Kobe Electric Mach Co Ltd | 内層回路入り多層金属箔張り積層板の製造法 |
JP2003008200A (ja) * | 2001-06-22 | 2003-01-10 | Matsushita Electric Ind Co Ltd | 配線基板とその製造方法 |
JP2003347728A (ja) * | 2002-05-30 | 2003-12-05 | Shin Kobe Electric Mach Co Ltd | 内層回路入り金属箔張り積層板の製造法 |
JP2004221310A (ja) * | 2003-01-15 | 2004-08-05 | Daiwa Kogyo:Kk | 配線基板部材及びその製造方法 |
Family Cites Families (6)
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2005
- 2005-09-29 WO PCT/JP2005/017926 patent/WO2006059428A1/ja active Application Filing
- 2005-09-29 US US11/720,711 patent/US8112881B2/en not_active Expired - Fee Related
- 2005-09-29 CN CN200580041604XA patent/CN101288349B/zh not_active Expired - Fee Related
- 2005-09-29 EP EP05788279A patent/EP1821588A4/en not_active Withdrawn
- 2005-09-29 KR KR1020077013198A patent/KR101168879B1/ko not_active IP Right Cessation
- 2005-10-28 TW TW094137944A patent/TW200621105A/zh not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
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JP2006165133A (ja) | 2006-06-22 |
EP1821588A4 (en) | 2009-11-11 |
US20080110018A1 (en) | 2008-05-15 |
CN101288349B (zh) | 2010-06-09 |
JP4761762B2 (ja) | 2011-08-31 |
TW200621105A (en) | 2006-06-16 |
CN101288349A (zh) | 2008-10-15 |
TWI371232B (ja) | 2012-08-21 |
US8112881B2 (en) | 2012-02-14 |
EP1821588A1 (en) | 2007-08-22 |
KR20070094896A (ko) | 2007-09-27 |
KR101168879B1 (ko) | 2012-07-26 |
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