Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3187—Built-in tests
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/31724—Test controller, e.g. BIST state machine
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318516—Test of programmable logic devices [PLDs]
  • G01R31/318519—Test of field programmable gate arrays [FPGA]
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/14—Implementation of control logic, e.g. test mode decoders
  • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
  • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/36—Data generation devices, e.g. data inverters
  • G11C2029/3602—Pattern generator
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
  • G11C2029/5604—Display of error information
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

Definitions

• Fig. 3 A is a definition of an alternative exemplary Algorithm Instruction word.
• Figs. 21 and 22 are exemplary approaches for determining the number of instructions loadable from an ATE to instruction memory.
• Fig. 29 is a schematic diagram of an exemplary circuit for use in shifting out diagnostic data.
• the Galloping/Walking 0 and 1 algorithms have two loops, the first loop is a base loop that marches through all addresses of the memory.
• the second loop is the inner (also called local) loop that loops through the address space in a specific order for a given base address.
• Butterfly is a variation of the GALPAT test that reduces the complexity of applying the test. Similar to the GALPAT algorithm, the memory is filled up, for example with background Os except for the base cell, which contains a 1. During test application, the base cell actually walks through the memory. While reading, only the four cells that are direct neighbors (east, west, north and south) of the base cells are read, i.e., a distance of one from the base cell. Depending on the implementation, other neighboring cells at a distance of 2, 4, 8, and 16 can be read successively.
• This class of algorithm in general does not target faults in the memory array and are primarily used to generate two pattern tests for stuck-open faults in the PMOS part of the address decoder. In this case, the algorithm has two levels of nested looping.
• the local address is related in a specific way to the base address.
• the local address may be generated by XORing base address and 2 n , where n is from 0 to N-I and N is the number of address bits.
• the exemplary architecture in some embodiments will also desirably be able to do a checksum of the bits by reading a memory location. This is useful for cases in which it becomes difficult to predict the data that is written into the memory. For example, if desired to write a memory in the functional mode and for the BIST controller to read the contents of the memory and generate a check-sum, this would be supported by the exemplary architecture. 2.1.3.5 Nested loops
• the programmable MBIST controller in one form also desirably is able to set the local addresses by a certain offset (1, 2, 4, ...) in every desired direction from the base address. This accommodates the Butterfly algorithm.
• a loop can contain one or more memory access operations. These operations can perform individual read or write accesses to the memories under test. Each access is desirably able to specify which level of loop's address register is to be used for that operation, hi one example, the operations in an outer loop, nesting level 0, can only use address register 0. However, those in an inner loop, for example at nesting level 3, can in this example use the address register for level 0, 1, 2 or 3.
• a programmable MBIST controller will, in one form, be able to perform a read without comparison operation. For example, in a read without comparison operation, the value read from memory can be ignored, unless MISR (multiple input shift register) compression is selected, in which case the value will be captured by a MISR. It can also be possible to update an internal data register with the value read from the memory.
• MISR multiple input shift register
• MISR multiple input shift register
• Control/Load/Block A multiple word command that loads a block number selection register of the programmable MBIST controller. In this example, this word is only usable if the programmable MBIST controller has been configured at generation time to support block selection.
• the exemplary pre-decoder 110 determines whether an instruction is either a algorithm or a Configuration Instruction. This is based on the LSB (least significant bit) of the instruction word in this example.
• the pre-decoder desirably also decodes the loop boundaries for the instructions that are in the instruction memory, thereby assisting in loading a single algorithm step for the base-loop to a base-loop buffer 120 along with all the operations related to a nested local-loop 122.
• the Algorithm Instruction decoder is activated only if the instruction is classified as pertaining to the operations that need to be actually performed on the memory under test (e.g., classified as an Algorithm Instruction).
• the control is passed back to a base-loop program counter. If there is a subsequent operation in the base loop, that is executed. Or else, the control is switched to bufl, where the next step for the base loop resides.
• a multiplexer 136 selects bufl and the operations corresponding to bufl are decoded and executed.
• the first loop nests all the other loops.
• the second loop nests the third and fourth loop. There are three levels of concurrently nested loops.
• the third and fourth loops are nested within the second loop and the first loop.
• the decoded information is placed into an address configuration buffer 502 (Fig. 8). This information, in this example, determines how the address will be manipulated and generated for the whole of the loop.
• Address buffer This contains the partially decoded address scheme for each address loop.
• the three most significant bits in this example specify the operation number, the next three bits specify the jump address of the current operation, the next two bits indicate the level of the loop whose last operation is the current operation, and the last bit ('Last word') indicates if the word is the last configuration word of the Configuration Instruction.
• the diagnostic monitor desirably comprises and more desirably consists of two finite state machines (FSM): one operating in the BIST clock domain and the second operating in the diagnostic clock domain.
• FSM finite state machines
• the two FSMs are explained below (See Figs. 27 and 28).
• cont_state BIST clock domain FSM
• this FSM will go to CONT-SCAN state and issue a start_diag signal for the diag state FSM.
• a synchronized diag done signal is sent from the diag state FSM.
• the instruction memory load clock and diagnostic clock can share the same input pin "shift_clk". If the clocks are not free-running, the "shift_clk" can be sent to the controller upon request, either via load_request or when fail_flag is asserted, or both.
• a suitable data generator for this March-only MBIST controller generates the data value to be written to or read from the current memory location of the current memory operation.
• Exemplary data generation scheme types that are supported by this example are listed below. In all cases, both data background and inverse of the data background are supported. The different data can be set by using configuration instructions.
• the design of the Base embodiments can be fairly modular in nature. The modularity is based on the functionality required by different groups of algorithms. Consequently, users can choose the group of algorithms they desire the controller to support, and accordingly, the architecture will be synthesized. This gives the flexibility to choose the complexity of the programmable hardware and attain better optimization between programmability and hardware overhead.
• the design of the alternative embodiments that accommodates loop within loops is not based on the groups. Instead such alternative embodiments are based on address schemes. Choosing different address schemes enables different algorithms. This provides flexibility in that users can choose address schemes to support a number of loops/operations and make a tradeoff between programming flexibility and hardware.
• Base cell a memory cell whose address will be updated for each iteration of base loop

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• For Increasing The Reliability Of Semiconductor Memories (AREA)
• Tests Of Electronic Circuits (AREA)

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• 2005
  • 2005-11-18 US US11/283,527 patent/US7428680B2/en active Active
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  • 2005-11-18 EP EP05849415A patent/EP1825479A4/en not_active Withdrawn
• 2009
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