WO2005114228A1 - 積層基板及びプローブカード - Google Patents
積層基板及びプローブカード Download PDFInfo
- Publication number
- WO2005114228A1 WO2005114228A1 PCT/JP2005/009439 JP2005009439W WO2005114228A1 WO 2005114228 A1 WO2005114228 A1 WO 2005114228A1 JP 2005009439 W JP2005009439 W JP 2005009439W WO 2005114228 A1 WO2005114228 A1 WO 2005114228A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- surface layer
- probe card
- circuit board
- thermal expansion
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
- G01R1/0441—Details
- G01R1/0458—Details related to environmental aspects, e.g. temperature
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07357—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with flexible bodies, e.g. buckling beams
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
Definitions
- the present invention relates to a laminated substrate and a probe card, and more particularly, to a laminated substrate and a probe card capable of suppressing thermal deformation.
- a laminated substrate is an indispensable component as a substrate for mounting electronic components conventionally used in precision instruments such as electronic instruments and measuring devices. Since these electronic and precision devices are used in a variety of environments, from low-temperature to high-temperature, the laminated boards must be weather-resistant according to the environment.
- the laminated substrate 1 has a base layer 2, a surface layer 3, and a plurality of electrodes 4. If the surface layer 3 has a higher coefficient of thermal expansion than the base layer 2, the surface layer 3 will extend more than the base layer 2 when the laminated substrate 1 is exposed to a high-temperature environment. It curves as indicated by the arrow. Note that in Fig. 8, the base layer 2 and the surface layer 3 are both shown as a single layer, but the laminated substrate 1 is generally configured as a multilayer board in which the base layer 2 is composed of multiple layers. It is a target.
- the probe device includes a loader chamber 1 for transporting the wafer W and a prober chamber 2 for inspecting the electrical characteristics of the wafer W delivered from the loader chamber 1. I have it.
- the prober chamber 2 has a mounting table (main chuck) 3 for mounting the wafer W transferred from the loader chamber 1 and having a built-in elevating mechanism, and an X and a main chuck 3.
- An XY table 4 that moves in the vertical direction, a probe card 5 that is placed above a main chuck 3 that moves through the XY table 4, and a card holding mechanism (hereinafter, “clamp”) that detachably holds the probe card 5 (Not shown) and the probe card 5
- the alignment mechanism 6 includes an upper camera 6A for imaging the wafer W and a lower camera 6B for imaging the probe 5A.
- a head plate 7 is mounted on the upper surface of the prober chamber 2, and a clamp mechanism for detachably holding the probe card 5 is provided in an opening of the head plate 7. It is installed.
- a test head (not shown) of a tester is pivotably disposed on the head plate 7, and the test head T and the probe card 5 are electrically connected via a connection ring (pogo ring) 8.
- the tester force also transmits a test signal to the probe 5A via the test head T, the noise board, and the pogo ring 8, and applies a test signal to the Ueno and W electrode pads from the probe 5A to form a test signal on the wafer W.
- a circuit board 5B constituting the probe card 5 is composed of a base material layer 5C made of an inorganic insulating material such as glass fiber and the like. If it is configured to include a surface layer 5D made of an organic insulating material such as resin and laminated on both sides of the main chuck 3 and the electrode 5E, the surface layer 5D on the main chuck 3 side during the high-temperature inspection (same as above). The lower side in the figure) is hotter than the surface layer 5D on the pogo ring 8 side (upper side in the figure) and expands greatly, so that the circuit board 5B is curved in the direction of the arrow and the electrode 5E is positioned from the pogo pin of the pogo ring 8. It may shift and reduce the reliability of the inspection.
- Patent Literature 1 proposes a jig (pin probe type jig) for inspecting a semiconductor device with a small amount of thermal deformation! /.
- the jig for semiconductor device inspection described in Patent Document 1 comprises a probe and a multilayer printed wiring board, wherein the multilayer printed wiring board has a conductor circuit 1 having at least a terminal connected to a probe, and a terminal connected to the inspection device.
- the circuit consists of a conductor circuit 2 having two conductors, two or more electrical insulation layers supporting these circuit conductor layers, and a through-hole cable electrically connecting these circuit conductor layers.
- the thermal expansion coefficient in the plane direction of the layer is smaller than the thermal expansion coefficient in the plane direction of the electrical insulating layer supporting the conductor circuit 2.
- Patent Document 1 Japanese Patent Application Laid-Open No. 9-133710 Disclosure of the invention
- the multilayer printed board used in the jig for semiconductor device inspection described in Patent Document 1 can suppress thermal deformation, but on the other hand, the electric insulating layer supporting the conductor circuit 1 cannot be used.
- Materials for forming the electrical insulation layer inorganic insulation materials such as glass fiber cloth) so that the thermal expansion coefficient in the plane direction is smaller than the thermal expansion coefficient in the plane direction of the electrical insulation layer supporting the conductor circuit 2.
- Materials for forming the electrical insulation layer inorganic insulation materials such as glass fiber cloth
- the layer configuration of the electrical insulation layer is a special specification, resulting in an increase in manufacturing costs.
- the present invention has been made to solve the above-mentioned problems, and a laminated substrate which can significantly suppress thermal deformation and can be manufactured at low cost without using a special material.
- a probe card For the purpose of providing a probe card!
- the laminated substrate of the present invention includes a substrate layer and a surface layer laminated on at least one surface of the substrate layer, and the surface layer has a larger coefficient of thermal expansion than the substrate layer.
- a groove for dividing the surface layer into a plurality is provided in the surface layer.
- the base layer may be exposed from the division grooves of the surface layer. Further, a second surface layer may be provided on the other surface of the base material layer. Further, the surface layer may be formed of an organic insulating material, or the base layer may be formed of an inorganic insulating material.
- a probe card is a probe card including at least one circuit board electrically connected to a probe that is in electrical contact with a device to be inspected.
- the present invention includes a contactor that is in electrical contact with a device under test, and the contactor includes a plurality of probes and a circuit board on which the probes are mounted.
- the circuit board comprises: a base layer; A surface layer laminated on at least the surface to be inspected, wherein the surface layer has a larger coefficient of thermal expansion than the base material layer, and the groove for dividing the surface layer into a plurality of grooves is formed. It is characterized by being provided on the surface layer.
- the base layer may be exposed from the dividing groove of the surface layer. Further, a second surface layer may be provided on the other surface of the base material layer. Further, the surface layer may be formed of an organic insulating material, and the base layer may be formed of an inorganic insulating material.
- thermal deformation can be remarkably suppressed, and a laminated substrate and a probe card can be manufactured at low cost without using a special material.
- FIG. 1 is a cross-sectional view showing a use mode of one embodiment of a probe card of the present invention.
- FIG. 2 is a cross-sectional view showing a main part of a contactor in the probe card of FIG. 1.
- FIG. 3 is a cross-sectional view showing a part of a circuit board in the probe card.
- FIG. 4 is a cross-sectional view schematically showing a relationship between a contactor and a main chuck in FIG. 2.
- FIG. 5] (a) to (c) are cross-sectional views for explaining the measurement site of the thermal expansion of the circuit board.
- FIG. 6 is a graph showing the relationship between the temperature of the circuit board of FIG. 3 and the coefficient of thermal expansion.
- FIG. 7 is a sectional view showing a main part of another embodiment of the laminated substrate of the present invention.
- FIG. 8 is a cross-sectional view for explaining thermal deformation of a conventional laminated substrate.
- FIG. 9 (a) is a cross-sectional view showing a part of the probe device to which the conventional probe card is applied, and (b) is the thermal deformation of the circuit board applied to the probe card shown in (a).
- FIG. 3 is a cross-sectional view for explaining.
- FIG. 1 is a cross-sectional view showing an embodiment of a probe card according to an embodiment of the present invention
- FIG. 2 is a cross-sectional view showing a main part of the contactor shown in FIG. 1
- FIG. Fig. 4 is a cross-sectional view schematically showing the relationship between the contactor and the main chuck shown in Fig. 2
- Figs. 5 (a) to 5 (c) are cross-sectional views for explaining the measurement site of the thermal expansion of the circuit board.
- FIGS. 6 and 7 are graphs showing the relationship between the temperature and the coefficient of thermal expansion of the circuit board shown in FIG. 3, and
- FIG. 7 is a cross-sectional view showing a main part of another embodiment of the laminated board of the present invention.
- the professional card 10 of the present embodiment includes a contactor 11 that makes electrical contact with an object to be inspected, for example, ⁇ , W, and is electrically conductive with the contactor 11.
- a circuit board 12 connected to the main board 30 and a reinforcing member 13 for reinforcing the circuit board 12 are mounted in a probe chamber (not shown) of a probe device via a card holder 20 and a wafer on the main chuck 30 is provided. It is arranged to face W.
- An interposer (connection relay medium) 14 is interposed between the contactor 11 and the circuit board 12, and the contactor 11 and the circuit board 12 are electrically connected via the interposer 14.
- the contactor 11 is fixed to the circuit board 12 by the fixture 15 and the fastening member 16 with the interposer 14 interposed.
- the contactor 11 is, for example, a second circuit as shown in a partially enlarged view in FIG. It has a substrate 11A and a plurality of probes 11B arranged on the lower surface of the second circuit board 11A so as to correspond to a plurality of electrode pads (not shown) of the wafer W.
- the second circuit board 11A is made of, for example, a base material layer 11C made of an inorganic insulating material such as ceramic, and an organic insulating material material such as a polyimide resin laminated on the lower and upper surfaces of the base material layer 11C, respectively.
- It has flat surface layers 11D and 11E, upper and lower surface layers 11D and 11E, terminal electrodes 11F and 11G formed corresponding to the probe 11B, and wiring 11H for connecting the upper and lower terminal electrodes 11F and 11G.
- it is configured so that a plurality of chips can be inspected at the same time.
- the contactor can be formed by using a fine processing technique such as a micromachine technique. Further, each of the base material layer 11C and the surface layers 11D and 11E may be formed as a single layer or may be formed as a plurality of layers.
- the wiring 11H is composed of via-hole conductors and conductor patterns formed on the base layer 11C and the surface layers 1ID and 11E.
- the base layer 11C is formed of an inorganic insulating material and the surface layers 1ID and 11E are formed of an organic insulating material, the surface layers 11D and 11E have a larger thermal expansion coefficient than the base layer 11C.
- the surface layers 11D and 11E expand more than the base layer 11C, respectively, and the lower surface layer 11D expands more than the upper surface layer 11E. And bulges downward and deforms.
- a plurality of grooves 111 are provided in the lower surface layer 11D, and the surface layer 11D is divided into a plurality of regions by these grooves 111.
- These grooves 111 can be formed simultaneously with the surface layer 11D, for example, by screen printing the surface layer 11D.
- the surface layer 11D is divided into a plurality of regions, and is dispersed as a plurality of independent thermal expansion regions. Since the thermal expansion of 11D is suppressed more than the thermal expansion of the upper surface layer 11E, the thermal deformation of the circuit board 11A and thus the contactor 11 can also be suppressed.
- These grooves 111 are vertically and / or laterally or misaligned with respect to the lower surface layer 11D within a range that does not impair the circuit pattern. May be provided in a plurality of directions, and may be provided in two directions in the vertical and horizontal directions. In the present embodiment, the groove 1 II is provided only in one direction!
- the circuit board 12 includes a base layer 12A formed of an inorganic insulating material such as ceramic or glass fiber, and a polyimide resin or the like laminated on both upper and lower surfaces of the base layer 12A.
- Surface layers 12B and 12C made of organic insulating material, and terminal electrodes 12D and 12E formed on the upper and lower surface layers 12B and 12C, respectively.
- a plurality of grooves 12F are formed by force screen printing or the like.
- a plurality of terminal electrodes 12D on the lower side of the circuit board 12 are in electrical contact with contact terminals (not shown) of the interposer 14, and a plurality of terminal electrodes 12E on the upper side are electrically connected to a plurality of pogo pins forming a pogo ring.
- the circuit board 12 has a role of electrically connecting the contactor 11 and a pogo ring (not shown) by being in contact with each other. Because the lower surface layer 12B faces the probe chamber side, the temperature during inspection is higher than the upper surface layer 12C, but the lower surface layer 12B is provided with a plurality of grooves 12F. Therefore, these grooves 12F suppress the bending of the circuit board 12 due to thermal deformation. Therefore, the upper and lower terminal electrodes 12D and 12E of the circuit board 12 can be reliably brought into contact with the interposer 14 and the pogo pins, and the reliability of the inspection can be improved.
- the wafer W is placed on the main chuck 30 and the wafer W is heated to, for example, about 150 ° C. by the heating source 31 of the main chuck 30 to perform a high-temperature inspection of the wafer W.
- the main chuck 30 moves in the Y direction to feed the index of the wafer W, and repeatedly moves up and down in the Z direction to repeat contact and separation between the contactor 11 and the wafer W. Therefore, the temperature of the probe card 10 rises to a temperature close to 150 ° C. like the wafer W.
- the lower surface of the second circuit board 11A rises to a higher temperature than the upper surface, and a large temperature difference occurs between the lower surface layer 11D and the upper surface layer 11E.
- the base layer 11C is formed of ceramic, and the surface layer 11D is formed of polyimide resin. Therefore, the surface layers 11D and 11E expand more than the base layer 11C, respectively, surface The layer 1 ID expands more than the upper surface layer 11D, and the second circuit board 11A expands downward and tries to curve downward.
- the lower surface layer 11D is divided into a plurality of parts via the grooves 111 as described above, the surface layer 11D thermally expands independently for each of the divided regions, and is adjacent to each other as shown by arrows in FIG.
- the circuit board 12 that is in electrical contact with the pogo ring also has the groove 12F in the lower surface layer 12B facing the inside of the probe device, like the second circuit board 11A of the contactor 11, so that the groove 12F is provided. Even if the lower surface layer 12B becomes hotter than the upper surface layer 12C, the area divided by the groove 12F expands independently, canceling out the thermal expansion between the adjacent areas. The thermal expansion of the surface layer 12B of the circuit board 12 is remarkably suppressed, and the bending due to the thermal deformation of the circuit board 12 is further suppressed. Therefore, the upper and lower terminal electrodes 12D and 12E maintain the initial contact state without being displaced from the interposer 14 and the pogo ring, respectively, and the inspection reliability can be improved.
- a circuit board having the same shape as the circuit board 12 was formed into a rectangular circuit board and prepared as a measurement board.
- the substrate for measurement was heated to 150 ° C at room temperature, and the elongation of the substrate for measurement at 50 ° C, 75 ° C, 100 ° C, 125 ° C, and 150 ° C was measured at multiple points. Based on the measurement results, the coefficient of thermal expansion at each measurement point was determined.
- the measurement substrate was provided with a 3 mm wide groove 12F in one direction parallel to each other on the lower surface layer 12B, and a non-groove substrate on the upper surface layer 12C.
- the surface layer 12B provided with the groove 12F has a high temperature of 75 to 150 ° C regardless of the direction across the groove 12F and the direction perpendicular thereto. It showed a coefficient of thermal expansion of 4 to 5.0 ppm.
- the grooved surface layer 12C shows a coefficient of thermal expansion of 6.6 to 6.7 ppm at a high temperature of 75 to 150 ° C, which is larger than the grooved surface layer 12B. It turned out that it showed.
- the groove 12F in the surface layer 12B the thermal expansion of the surface layer 12B can be suppressed, and thus the thermal deformation of the measurement substrate can be suppressed, and the groove 12F is effective in suppressing the thermal deformation of the substrate. It was confirmed that there was.
- the circuit board 12 has a base layer 12A and surface layers 12B and 12C laminated on both upper and lower surfaces of the base layer 12A.
- the surface layers 12B and 12C have a larger coefficient of thermal expansion than the base layer 12A.
- the groove 12F for dividing the surface layer 12B on the wafer W side into a plurality of parts is provided in the surface layer 12B, the thermal expansion of the surface layer 12B on the wafer W side is suppressed more than the thermal expansion of the surface layer 12C on the pogo ring side. Was completed. Therefore, the thermal deformation of the circuit board 12 is suppressed and the interposer 1
- the circuit board 12 can be manufactured at low cost without using special materials for the base layer 12A and the surface layer 12B. Can be.
- the second circuit board 11A constituting the contactor 11 is also Since the wafer W side surface layer 1 ID is provided with a plurality of grooves 1 II and is configured similarly to the circuit board 12, the thermal expansion of the wafer W side surface layer 11D is reduced by the thermal expansion of the interposer 14 side surface layer 11E. Therefore, the thermal deformation of the second circuit board 11A can be suppressed, and the misalignment of the contactor 11 with the wafer W and the interposer 14 can be reliably prevented. Can be enhanced.
- the base layer 12A of the circuit board 12 is made of an inorganic insulating material such as glass fiber and the surface layers 12B and 12C are made of an organic insulating material such as polyimide resin.
- the internal wiring and the electrodes 12D and 12E can be formed with high accuracy by a build-up method or the like.
- heat resistance and the like in which the base material layer 12A is made of ceramic can be imparted.
- the same operation and effect as the circuit board 12 can be expected for the second circuit board 11A constituting the contactor 11. Further, by forming the second circuit board 11A of ceramic, it is possible to cope with miniaturization of the probe 11B.
- FIG. 7 shows a laminated substrate having a surface layer only on one side. That is, the laminated substrate 50 has a base layer 51, a surface layer 52 stacked on the upper surface of the base layer 51, and an electrode 53 formed on the surface layer 52. It has a coefficient of thermal expansion greater than 51.
- a plurality of grooves 54 (only one groove is shown in FIG. 7) are formed.
- each of the base layer 51 and the surface layer 52 may be a single layer or a plurality of layers. Also in this case, since the plurality of grooves 54 are provided in the surface layer 52, the thermal expansion of the surface layer 52 can be suppressed, and the thermal deformation of the laminated substrate 50 can be suppressed.
- the present invention is not limited to the above-described embodiments, and the laminated substrate of the present invention is applicable to a high-temperature environment. It can be widely applied to exposed laminated substrates.
- the present invention can be suitably used for a laminated substrate or a probe card exposed to a high-temperature environment.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/597,476 US7750655B2 (en) | 2004-05-24 | 2005-05-24 | Multilayer substrate and probe card |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004153231A JP4727948B2 (ja) | 2004-05-24 | 2004-05-24 | プローブカードに用いられる積層基板 |
JP2004-153231 | 2004-05-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005114228A1 true WO2005114228A1 (ja) | 2005-12-01 |
Family
ID=35428494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/009439 WO2005114228A1 (ja) | 2004-05-24 | 2005-05-24 | 積層基板及びプローブカード |
Country Status (5)
Country | Link |
---|---|
US (1) | US7750655B2 (ja) |
JP (1) | JP4727948B2 (ja) |
KR (1) | KR100812418B1 (ja) |
TW (1) | TW200620519A (ja) |
WO (1) | WO2005114228A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2007066623A1 (ja) * | 2005-12-05 | 2007-06-14 | Nhk Spring Co., Ltd. | プローブカード |
WO2007077743A1 (ja) * | 2005-12-28 | 2007-07-12 | Nhk Spring Co., Ltd. | プローブカード |
US8018242B2 (en) | 2005-12-05 | 2011-09-13 | Nhk Spring Co., Ltd. | Probe card |
CN110244091A (zh) * | 2018-03-09 | 2019-09-17 | 东京毅力科创株式会社 | 位置修正方法、检查装置和探针卡 |
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KR100904388B1 (ko) * | 2007-05-08 | 2009-06-26 | 주식회사 파이컴 | 다층 기판 및 이를 포함하는 전기 검사 장치 |
JP5194215B2 (ja) * | 2008-03-21 | 2013-05-08 | 豊丸産業株式会社 | パチンコ機 |
KR20100019885A (ko) * | 2008-08-11 | 2010-02-19 | 삼성전기주식회사 | 프로브 카드 제조 방법 |
KR20100025900A (ko) * | 2008-08-28 | 2010-03-10 | 삼성전기주식회사 | 프로브 카드 및 그의 제조 방법 |
JP2010243302A (ja) * | 2009-04-04 | 2010-10-28 | Advanced Systems Japan Inc | 干渉防止構造プローブカード |
JP2010243303A (ja) * | 2009-04-04 | 2010-10-28 | Advanced Systems Japan Inc | 低熱膨張インターポーザ |
CN102033144B (zh) * | 2009-09-30 | 2013-10-23 | 株式会社神户制钢所 | 电接点构件 |
KR101048497B1 (ko) * | 2010-07-19 | 2011-07-12 | (주) 마이크로프랜드 | 프로브 카드 및 그 제조방법 |
WO2012011627A1 (ko) * | 2010-07-19 | 2012-01-26 | (주) 마이크로프랜드 | 프로브 카드 및 그 제조방법 |
JP5079890B2 (ja) * | 2011-01-05 | 2012-11-21 | 東京エレクトロン株式会社 | 積層基板及びプローブカード |
WO2013061486A1 (ja) * | 2011-10-26 | 2013-05-02 | ユニテクノ株式会社 | コンタクトプローブおよびそれを備えた検査ソケット |
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WO2007066623A1 (ja) * | 2005-12-05 | 2007-06-14 | Nhk Spring Co., Ltd. | プローブカード |
JP2007155507A (ja) * | 2005-12-05 | 2007-06-21 | Nhk Spring Co Ltd | プローブカード |
US8018242B2 (en) | 2005-12-05 | 2011-09-13 | Nhk Spring Co., Ltd. | Probe card |
CN101341412B (zh) * | 2005-12-05 | 2011-09-28 | 日本发条株式会社 | 探针卡 |
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US7795892B2 (en) | 2005-12-28 | 2010-09-14 | Nhk Spring Co., Ltd. | Probe card |
CN110244091A (zh) * | 2018-03-09 | 2019-09-17 | 东京毅力科创株式会社 | 位置修正方法、检查装置和探针卡 |
CN110244091B (zh) * | 2018-03-09 | 2021-06-29 | 东京毅力科创株式会社 | 位置修正方法、检查装置和探针卡 |
Also Published As
Publication number | Publication date |
---|---|
KR20070026632A (ko) | 2007-03-08 |
JP4727948B2 (ja) | 2011-07-20 |
TWI373084B (ja) | 2012-09-21 |
US7750655B2 (en) | 2010-07-06 |
TW200620519A (en) | 2006-06-16 |
JP2005337737A (ja) | 2005-12-08 |
US20080191720A1 (en) | 2008-08-14 |
KR100812418B1 (ko) | 2008-03-10 |
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