WO2005069487A1 - パルス幅調整回路、パルス幅調整方法、及び半導体試験装置 - Google Patents
パルス幅調整回路、パルス幅調整方法、及び半導体試験装置 Download PDFInfo
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- WO2005069487A1 WO2005069487A1 PCT/JP2005/000617 JP2005000617W WO2005069487A1 WO 2005069487 A1 WO2005069487 A1 WO 2005069487A1 JP 2005000617 W JP2005000617 W JP 2005000617W WO 2005069487 A1 WO2005069487 A1 WO 2005069487A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31922—Timing generation or clock distribution
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
Definitions
- Pulse width adjustment circuit Pulse width adjustment circuit, pulse width adjustment method, and semiconductor test apparatus
- the present invention relates to a pulse width adjustment circuit that outputs an output signal obtained by adjusting a pulse width of a given pulse signal, and a pulse width adjustment method.
- a pulse width adjustment circuit that outputs an output signal obtained by adjusting a pulse width of a given pulse signal
- a pulse width adjustment method for those designated countries that are allowed to be incorporated by reference to the literature, the contents described in the following application are incorporated into this application by reference and are incorporated as part of the description of this application.
- Patent application 2004 011412 Filing date January 20, 2004
- a pulse width adjustment circuit 300 as shown in FIG. 1 has been known as a circuit for adjusting the pulse width of a given pulse signal.
- the pulse width adjustment circuit 300 is a circuit that adjusts a pulse width in the adjustment unit 302.
- the adjustment unit 302 has a variable delay circuit 304 and an AND circuit 306, and calculates the AND of the inverted signal of the given pulse signal and the pulse signal delayed by the variable delay circuit 304, A pulse signal having a pulse width corresponding to the delay amount in the variable delay circuit 304 is generated (for example, see Patent Document 1). Further, the pulse signal generated by the adjustment unit 302 is delayed by a delay circuit 308 at a desired timing and output to the outside.
- the pulse width adjustment circuit 300 has a function of measuring the pulse width of the pulse signal generated by the adjustment unit 302. In this case, first, the pulse width adjustment circuit 300 generates a pulse based on the falling edge of the pulse signal generated by the adjustment section 302, and feeds back the generated pulse to the adjustment section 302 to form a loop. I do. Then, the cycle in the loop is calculated by the counter 316. Next, the pulse width adjustment circuit 300 generates a pulse on the basis of the rising edge of the pulse signal generated by the adjustment section 302, feeds back the generated pulse to the adjustment section 302, and calculates the period in the same manner. The pulse width of the pulse signal generated by the adjustment unit 302 is calculated from the difference between these periods.
- FIG. 2 is a diagram showing an operation when measuring a pulse width in the conventional pulse width adjustment circuit 300.
- Fig. 2 (a) shows a pattern generated based on the rising edge of the noise signal.
- Fig. 2 (b) shows the operation when the pulse generated by reference to the rising edge of the pulse signal is input as feedback.
- FIG. 2A first, an input pulse is given to the adjustment unit 302, and the AND circuit 306 outputs a pulse signal in which the pulse width of the pulse is adjusted to P1. Then, the delay circuit 308 delays and outputs the pulse signal.
- the delay amount is Tpdl for the rising edge of the pulse signal, and Tpdl 'for the falling edge of the pulse signal, which is a different delay amount.
- exclusive OR circuit 310 inverts the pulse signal and outputs the inverted pulse signal.
- the pulse signal is delayed in the exclusive OR circuit 310, but the delay amount with respect to the rising edge of the pulse signal is Tpd2, and the delay amount with respect to the falling edge of the pulse signal is Tpd2, similarly to the delay circuit 308. ', Resulting in different delay amounts.
- the differentiating circuit 312 generates a pulse signal having a pulse width of P2 based on the falling edge of the pulse signal received from the exclusive OR circuit 310, and the integrating circuit 314 generates the pulse signal received from the differentiating circuit 312. Adjust the pulse width of the signal to P2 + P3 and output.
- the pulse width P2 + P3 is the same as the pulse width of the input pulse initially given to adjustment section 302.
- the integration circuit 314 supplies the pulse signal having the adjusted pulse width to the adjustment unit 302, and loops the pulse signal.
- the exclusive OR circuit 310 uses the received pulse signal as it is. Output. Then, the differentiating circuit 312 generates a pulse signal having a pulse width of P2 based on the falling edge of the pulse signal received from the exclusive OR circuit 310, and the integrating circuit 314 generates a pulse signal having a pulse width of P2 + P3. Loop the signal.
- the cycle T2 of the loop is represented by the following equation.
- T2 Pl + Tpdl '+ Tpd2' + P2 + P3
- T2-T1 P1 + (Tpdl '-Tpdl) + (Tpd2, — Tpd2)
- FIG. 3 is a diagram showing a configuration of the variable delay circuit 304.
- the variable delay circuit 304 has a coarse delay circuit section 318 and a fine delay circuit section 305.
- the fine delay circuit 305 is a circuit that generates a delay in a smaller step than the coarse delay circuit 318.
- the coarse delay circuit unit 318 and the fine delay circuit unit 305 are connected in series, and the pulse signal is delayed by the sum of the delay amount in the coarse delay circuit unit 318 and the delay amount in the fine delay circuit unit 305.
- the coarse delay circuit unit 318 is a circuit that controls the amount of delay by, for example, providing a plurality of inverters connected in series in parallel and selecting the number of stages of inverter trains through which the pulse signal is passed. It is.
- the fine delay circuit unit 305 is a circuit that controls a delay amount by connecting a plurality of delay elements each including two inverters and a variable capacitance element in series, and changing the capacitance of the variable capacitance element.
- the maximum delay amount in the fine delay circuit unit 305 is the same as the delay resolution in the coarse delay circuit unit 318. With such a configuration, a circuit in which the variable width of the delay amount is large and the resolution of the delay amount is high and the delay setting step is small is provided.
- the fine delay circuit section 305 passes the inverters provided in series, a predetermined offset delay occurs even when the delay amount is minimized.
- the number of stages of the inverter and the variable capacitance element must be reduced.However, the delay amount of the fine delay circuit unit 305 varies within the range of the delay resolution of the coarse delay circuit unit 318. In this case, the number of stages of the inverter and the variable capacitance element in the fine delay circuit unit 305 is required to be about 5-6. For this reason, it is difficult to configure the fine delay circuit unit 305 with a reduced offset delay.
- the conventional pulse width adjustment circuit 300 has both of generating a pulse signal with a small pulse width and adjusting the pulse width with high resolution. It was difficult to stand.
- Patent Document 1 JP-A-10-303709
- the conventional circuit has a problem that it is difficult to generate a pulse signal with a small pulse width and to adjust the pulse width with high resolution. .
- the pulse width of the generated pulse signal cannot be accurately measured, and it is difficult to accurately adjust the pulse width.
- an object of the present invention is to provide a pulse width adjustment circuit and a pulse width adjustment method that can solve the above-mentioned problems, and a semiconductor test apparatus using the circuit. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous embodiments of the present invention.
- a first embodiment of the present invention is a pulse width adjustment circuit that outputs an output signal in which a pulse width of a given pulse signal is adjusted, and the pulse signal is a pulse width adjustment circuit that outputs a pulse signal.
- a first delay circuit that outputs a delayed first delay signal
- a second delay circuit that outputs a second delay signal obtained by delaying a pulse signal by a delay amount different from that of the first delay circuit
- a pulse width adjustment circuit including an output unit that outputs an output signal having a pulse width corresponding to a difference between a delay amount and a delay amount in a second delay circuit based on a first delay signal and a second delay signal.
- the first delay circuit and the second delay circuit may delay the pulse signal with different delay resolutions.
- the output unit may select an edge having the same change direction from each of the first delay signal and the second delay signal, and generate a rising edge and a falling edge of the output signal based on the selected two edges. .
- the output unit includes a set / reset latch circuit that outputs an H logic based on the first delay signal and outputs an L logic based on the second delay signal. And the first delay signal and the second delay signal have a pulse width that does not simultaneously operate the set-reset latch circuit, and the first delay signal has a pulse width of substantially the same magnitude.
- the signal processing apparatus may further include a pre-pulsor that adjusts the pulse width of the signal and the second delay signal and supplies the adjusted pulse width to the set / reset latch circuit.
- the pulse width adjustment circuit further includes a measurement unit that measures the pulse width of the output signal, and the output unit further has a function of passing the first delay signal and the second delay signal output by the prepulser, respectively.
- the measurement unit receives the first delay signal or the second delay signal passed by the output unit, adjusts the pulse width of the delay signal to a pulse width substantially equal to the pulse width of the pulse signal, Loop means for inputting a pulse signal to the second delay circuit, a first loop cycle when the loop means loops the first delay signal, and a second loop cycle when the loop means loops the second delay signal And a calculation unit that calculates the pulse width of the output signal based on the difference between the first loop period and the second loop period.
- the pre-pulser includes a first pulser for adjusting the pulse width of the first delay signal, a second pulser for adjusting the pulse width of the second delay signal, and a first pulser having the pulse width adjusted for the first pulser.
- First control means for controlling whether to output a delayed signal, a power for outputting a first delayed signal without adjusting a pulse width, or a signal for passing a second delayed signal to a set / reset latch circuit.
- Second control means for controlling a force for outputting a signal for causing the control signal to be output.
- the pulse width adjustment circuit includes an actual operation mode for generating an output signal to be output to the outside, a leading edge measurement operation mode for measuring a first loop period, and a trailing edge measurement operation for measuring a second loop period.
- the first control means causes the first pulser to output a first delay signal whose pulse width has been adjusted, and outputs the second delay signal to the first pulser when the pulse width adjustment circuit operates in the actual operation mode.
- the control means causes the second pulser to output a second delay signal whose pulse width has been adjusted, and when the pulse width adjustment circuit operates in the leading edge measurement operation mode, the first control means causes the first pulser to: The first delay signal is output without adjusting the pulse width, and the second control means causes the second pulser to output a signal for passing the first delay signal to the set / reset latch circuit, and the pulse width adjustment circuit Operates in the trailing edge measurement mode.
- Your means causes the first pulser to output a signal for passing the second delay signal to the set / reset latch circuit, and the second control means causes the second pulser to output the second delay signal without adjusting the pulse width. May be output.
- the set / reset latch circuit sets the skew between a path for generating a falling edge of the output signal in response to the second delay signal in the actual operation mode and a path for passing the second delay signal in the trailing edge measurement operation mode.
- Delay means for reducing the delay may be provided in a path through which the second delay signal passes.
- the first pulser receives the first delay signal, and outputs a logical product of the logical product of the first control signal and the first control signal received from the first control means.
- a second AND circuit that outputs an inverted signal of the AND of the first control means and the second control signal that is received, a third delay circuit that delays the signal output by the second AND circuit, A third AND circuit that outputs an inverted signal of a logical product of a signal output by the AND circuit and a signal output by the third delay circuit;
- H logic is output as the first control signal and the second control signal, and when the pulse width adjustment circuit operates in the trailing edge measurement operation mode, the first control signal or the second control signal is output.
- Outputs L logic when the pulse width adjusting circuit operates at the front edge measuring operation mode, the H logic and outputs a first control signal, may output logic L as the second control signal.
- the second pulser receives a second delay signal, and outputs a signal obtained by inverting a logical product of the third control signal and the third control signal received from the second control means.
- a fifth AND circuit that outputs an inverted signal of a logical product of the fourth control signal and the fourth control signal that is received, a fourth delay circuit that delays a signal output by the fifth AND circuit,
- a sixth AND circuit that outputs an inverted signal of a logical product of the signal output by the four AND circuit and the signal output by the fourth delay circuit, wherein the second control means is implemented by a pulse width adjusting circuit.
- H logic When operating in the operation mode, H logic is output as the third control signal and the fourth control signal, and when the pulse width adjustment circuit operates in the trailing edge measurement operation mode, the H logic is output as the first control signal and the second control signal. Outputs L logic, and pulse width adjustment circuit operates in leading edge measurement operation mode If that, the logic H is output as one of the first control signal or the second control signal, the first system L logic may be output as the other of the control signal and the second control signal.
- a pulse width adjusting method for outputting an output signal in which a pulse width of a given pulse signal is adjusted, wherein the first delayed signal obtained by delaying the pulse signal is output.
- a pulse width adjusting method including: an output step of generating an output signal having a pulse width corresponding to a difference between a delay amount in a first delay stage and a delay amount in a second delay stage.
- a leading edge measuring operation step for measuring the delay amount in the first delay stage a trailing edge measuring operation step for measuring the delay amount in the second delay stage, a leading edge measuring operation step, and a trailing edge measuring operation. Adjusting a delay amount in each of the first delay stage and the second delay stage based on each delay amount measured in the operation stage. After adjusting the amount, the output signal may be output externally.
- a semiconductor test apparatus for testing a semiconductor circuit, comprising: a pattern generator for generating a test pattern for testing a semiconductor circuit; and a pattern generator for supplying the semiconductor circuit based on the test pattern.
- a waveform shaper for shaping a test signal to be tested, a timing signal generating circuit for supplying a timing signal for defining a phase of the test signal to the waveform shaper, and a pass / fail judgment of the semiconductor circuit based on an output signal output from the semiconductor circuit
- a timing signal generating circuit that outputs a timing signal in which a pulse width of a given pulse signal is adjusted, and outputs a first delay signal obtained by delaying the pulse signal.
- a first delay circuit a second delay circuit that outputs a second delay signal obtained by delaying the pulse signal by a delay amount different from the first delay circuit, and a first delay circuit.
- a semiconductor test apparatus having an output unit that outputs a timing signal having a pulse width corresponding to a difference between a delay amount and a delay amount in a second delay circuit based on a first delay signal and a second delay signal.
- the present invention it is possible to generate an output signal having a high-resolution pulse width and a pulse width smaller than the offset delay amount in the delay circuit. Also, the pulse width of the output signal can be measured accurately.
- FIG. 1 is a diagram showing a conventional pulse width adjustment circuit 300.
- FIG. 2 is a diagram showing an operation when measuring a pulse width in a conventional pulse width adjustment circuit 300.
- Fig. 2 (a) shows the operation when a pulse generated based on the rising edge of the pulse signal is input as feedback
- Fig. 2 (b) shows the operation when the pulse generated based on the falling edge of the pulse signal is input. The operation when input is shown.
- FIG. 3 is a diagram showing a configuration of a conventional variable delay circuit 304.
- FIG. 4 is a diagram showing an example of a configuration of a pulse width adjustment circuit 100 according to the embodiment of the present invention.
- FIG. 5 is a diagram showing an example of a configuration of a pulse width adjustment unit 10.
- FIG. 6 is a diagram for explaining the operation of the pulse width adjustment unit 10 in an actual operation mode.
- FIG. 7 is a diagram illustrating the operation of the first pulser 26 in each operation mode.
- FIG. 7A illustrates the operation of the first pulser 26 in the actual operation mode.
- FIG. 7 (b) is a diagram illustrating the operation of the first pulser 26 in the leading edge measurement operation mode
- FIG. 7 (c) is a diagram illustrating the operation of the first pulser 26 in the trailing edge measurement operation mode. It is a figure.
- FIG. 8 is a flowchart showing an example of a pulse width adjustment method using the pulse width adjustment circuit 100.
- FIG. 9 is a diagram showing an example of a configuration of a semiconductor test apparatus 400 for testing a semiconductor circuit 450.
- ⁇ 'OR circuit 58 ⁇ ' buffer, 60 ⁇ ⁇ 'selection section, 100 ⁇ ' pulse width adjustment circuit, 102 ⁇ 'variable delay circuit, 104 differentiation circuit, 106 integration circuit , 108 "counter, 110 calculation unit, 112 loop loop, 114 loop means, 300 pulse width adjustment circuit, 302
- Adjustment unit 304 Variable delay circuit, 305 Fine delay circuit unit, 306 AND circuit, 3 08 delay circuit, 310 Exclusive OR circuit, 312 ⁇ Differentiator circuit, 314 ⁇ ⁇ ⁇ Integrator circuit, 316 ⁇ 'Counter, 318 ⁇ ⁇ ' Coarse delay circuit
- FIG. 4 is a diagram showing an example of a configuration of the pulse width adjustment circuit 100 according to the embodiment of the present invention.
- the pulse width adjustment circuit 100 outputs an output signal in which the pulse width of a given pulse signal is adjusted, and measures an actual operation mode for generating an output signal for external output and a pulse width of the output signal.
- a leading edge measurement operation mode and a trailing edge measurement operation mode In the leading edge measurement operation mode, for example, the same operation as the operation described with reference to FIG. 2A is performed, and in the rear edge measurement operation mode, for example, the same operation as the operation described with reference to FIG. 2B is performed.
- the pulse width adjustment circuit 100 includes a pulse width adjustment unit 10, a variable delay circuit 102, a loop unit 114, a counter 108, and a calculation unit 110.
- the pulse width adjustment unit 10 is supplied with a pulse signal, and outputs an output signal in which the pulse width of the pulse signal has been adjusted.
- the variable delay circuit 102 receives the output signal whose pulse width has been adjusted by the pulse width adjusting unit 10, delays the output signal by a desired time, and outputs it.
- the loop unit 114, the counter 108, and the calculation unit 110 function as a measurement unit that measures the pulse width of the output signal output by the pulse width adjustment unit 10.
- the loop means 114 adjusts the pulse width of the output signal to a pulse width substantially equal to the pulse width of the pulse signal supplied to the pulse width adjusting unit 10. Then, the pulse signal is input to the pulse width adjustment unit 10 as a pulse signal.
- the loop means 114 has a differentiating circuit 104, an integrating circuit 106, and a loop path 112.
- Differentiating circuit 104 reduces the pulse width of the output signal, adjusts the pulse width to a predetermined pulse width, and outputs the adjusted signal.
- the differentiating circuit 104 and the integrating circuit 106 may have substantially the same configuration as the pulse width adjusting unit 10. Further, the integrating circuit 106 enlarges the pulse width of the output signal whose pulse width has been adjusted by the differentiating circuit 104, and adjusts the pulse width to be substantially the same as the pulse signal. Then, the loop path 112 electrically connects the integration circuit 106 and the pulse width adjustment unit 10, and the output signal whose pulse width has been adjusted by the integration circuit 106 is input to the pulse width adjustment unit 10 as a pulse signal. Force to form a loop.
- the counter 108 counts pulses in the loop.
- the calculation unit 110 functions as a cycle measurement unit that measures the cycle of the loop based on the count result of the counter 108.
- the arithmetic unit 110 measures the pulse width of the output signal output by the pulse width adjusting unit 10 based on the measured cycle. The method of calculating the pulse width will be described later with reference to FIG.
- FIG. 5 is a diagram showing an example of the configuration of the pulse width adjustment unit 10.
- the pulse width adjustment unit 10 includes a first delay circuit 12, a second delay circuit 18, a first pulser 26, a second pulser 38, and an output unit 50.
- the first delay circuit 12 receives the pulse signal and outputs a first delay signal obtained by delaying the pulse signal.
- the first delay circuit 12 includes a plurality of inverter rows in which two inverters 16 are connected in series, and a selector 14.
- the inverter trains are connected in series, and a noise signal is input to the first inverter train.
- the selection unit 14 selects a signal output by the inverter train of any force, and outputs the selected signal as a first delay signal.
- the amount of delay in the first delay circuit 12 can be controlled by selecting which signal is selected by the selector 14.
- the second delay circuit 18 outputs a second delay signal obtained by delaying the pulse signal by a delay amount different from that of the first delay circuit 12.
- the second delay circuit 18 delays the pulse signal by a larger delay amount than the first delay circuit 12.
- the first delay circuit 12 and the second delay circuit 18 delay the pulse signal with different delay resolutions.
- the second delay circuit 18 has a higher delay resolution than the first delay circuit 12, that is, a smaller delay stage.
- the variable width of the delay amount of the second delay circuit 18 is preferably substantially the same as the delay resolution of the first delay circuit 12.
- the second delay circuit 18 has a plurality of delay elements (20-1-20-n, where n is an integer of 2 or more, hereinafter generically referred to as 20) connected in series.
- Each delay element 20 has two inverters 22 connected in series, and a variable capacitance element 24 provided between a connection path between the two inverters 22 and a ground potential. The amount of delay in each delay element 20 is controlled by controlling the capacitance of the variable capacitance element 24.
- the first delay circuit 12 and the second delay circuit 18 perform the above-described operation regardless of the operation mode of the pulse width adjustment circuit 100. Next, the operation of the first pulser 26, the second pulser 38, and the output unit 50 in the actual operation mode will be described.
- the output unit 50 outputs an output signal having a pulse width corresponding to the difference between the delay amount in the first delay circuit 12 and the delay amount in the second delay circuit 18 based on the first delay signal and the second delay signal. Output. Further, the output unit 50 selects edges having the same change direction as the first delay signal and the second delay signal, and determines the rising edge and the falling edge of the output signal based on the selected two edges. Generate. For example, the output unit 50 generates a rising edge of the output signal according to a falling edge of the first delayed signal, and generates a falling edge of the output signal according to a falling edge of the second delayed signal.
- the output unit 50 has a set / reset latch circuit 52 that outputs H logic based on the first delay signal and outputs L logic based on the second delay signal.
- the set / reset latch circuit 52 outputs H logic from the positive output terminal Q in response to the falling edge of the first delay signal, and outputs L logic in response to the falling edge of the second delay signal.
- the negative output terminal ZQ of the set / reset latch circuit 52 outputs an inverted signal of the positive output terminal Q.
- the output unit 50 can output a signal having a pulse width corresponding to the difference between the delay amount in the first delay circuit 12 and the delay amount in the second delay circuit 18.
- first pulser 26 and the second pulser 38 receive the first delay signal and the second delay signal, and the first delay signal and the second delay signal have pulse widths that do not simultaneously operate the set / reset latch circuit 52. And as a pre-pulser to supply to the set-reset latch circuit 52 Function.
- the first pulser 26 adjusts the pulse width of the first delay signal and supplies it to the set terminal ZS of the set / reset latch circuit 52
- the second pulser 38 adjusts the pulse width of the second delay signal to set and reset Supply to reset terminal ZR of latch circuit 52.
- the first pulser 26 and the second pulser 38 invert the first delay signal and the second delay signal whose pulse widths have been adjusted and perform the set reset latch circuit. Supply to 52.
- the configuration of the first pulsar 26 and the second pulsar 38 will be described with reference to FIG.
- the output unit 50 has a function of passing the first delay signal and the second delay signal output by the prepulser, respectively.
- the output unit 50 passes the first delay signal.
- the output unit 50 outputs the second delay signal. Pass the signal.
- the loop means 114 receives the first delay signal or the second delay signal passed by the output unit 50, and sets the pulse width of the delay signal to be substantially equal to the pulse width of the pulse signal. , And input the pulse signal to the first delay circuit and the second delay circuit.
- the counter 108 (see Fig. 4) counts the number of noises in the loop. Based on the counting result, the first loop period when the loop means 114 loops the first delay signal is measured. Similarly, the arithmetic unit 110 measures a second loop period when the loop unit 114 loops the second delay signal. Then, the arithmetic unit 110 calculates the pulse width of the output signal based on the difference between the first loop cycle and the second loop cycle. With such a configuration, the pulse width of the output signal generated by the pulse width adjustment unit 10 can be measured.
- FIG. 6 is a diagram illustrating the operation of the pulse width adjustment unit 10 in the actual operation mode.
- a pulse signal as shown in FIG. 6 is input to the first delay circuit 12 and the second delay circuit 18.
- the first delay circuit 12 outputs a first delay signal obtained by delaying the pulse signal by the delay amount Tpdl
- the second delay circuit 18 outputs a second delay signal obtained by delaying the pulse signal by the delay amount Tpd2.
- the first pulser 26 is an inverted signal of the signal obtained by adjusting the pulse width of the first delay signal.
- the second pulser 38 outputs an inverted signal of the signal obtained by adjusting the pulse width of the second delayed signal in response to the falling edge of the second delayed signal. I do.
- the output unit 50 outputs an H signal according to the falling edge of the signal output from the first pulser 26 and outputs an L signal according to the falling edge of the signal output from the second pulser 38. Is output. With such an operation, the output unit 50 generates an output signal having a pulse width corresponding to the difference between the delay amount in the first delay circuit 12 and the delay amount in the second delay circuit 18. According to the pulse width adjustment unit 10 in this example, the rising edge of the output signal is generated by the first delay signal, and the falling edge of the output signal is generated by the second delay signal.
- the pulse width can be controlled by the delay resolution of the second delay circuit 18 having a high resolution, and an output signal having a pulse width smaller than the offset delay amount in the second delay circuit 18 can be generated.
- the edge change The effect of the delay error based on the direction can be reduced, and the pulse width can be adjusted accurately.
- FIG. 7 is a diagram illustrating the operation of the first pulser 26 in each operation mode.
- FIG. 7A is a diagram illustrating the operation of the first pulser 26 in the actual operation mode
- FIG. 7B is a diagram illustrating the operation of the first pulser 26 in the leading edge measurement operation mode
- FIG. 7C is a diagram for explaining the operation of the first pulser 26 in the trailing edge measurement operation mode.
- the pre-pulser has the first pulser 26 and the second pulser 38 as described above.
- the first pulser 26 includes a first AND circuit 28, a second AND circuit 32, a third AND circuit 36, a third delay circuit 34, and an inverter 30.
- the first AND circuit 28 receives the first delay signal, and outputs an inverted signal of the logical AND with the first control signal received from the first control means (not shown).
- Inverter 30 receives the first delay signal, and outputs an inverted signal of the first delay signal.
- the second AND circuit 32 receives the inverted signal of the first delay signal, and outputs an inverted signal of the AND of the first delayed signal and the second control signal received from the first control means.
- the third delay circuit 34 The signal output by the product circuit 32 is output after being delayed.
- the third AND circuit 36 outputs an inverted signal of the logical product of the signal output from the first AND circuit 28 and the signal output from the third delay circuit 34.
- the first control means supplies the first control signal and the second control signal according to the operation mode of the pulse width adjustment circuit 100.
- the first control means causes the first pulser 26 to output the first delay signal with the adjusted pulse width, the force to output the first delay signal without adjusting the pulse width, or the set / reset latch. It controls whether the circuit 52 outputs a signal for passing the second delay signal.
- the second pulser 38 includes a fourth AND circuit 40, a fifth AND circuit 44, a sixth AND circuit 48, a fourth delay circuit 46, and an inverter 42.
- the fourth AND circuit 40 receives the second delay signal, and outputs an inverted signal of the logical AND with the third control signal received from the second control means (not shown).
- Inverter 42 receives the second delay signal, and outputs an inverted signal of the second delay signal.
- the fifth AND circuit 44 receives the inverted signal of the second delay signal, and outputs an inverted signal of the logical AND of the fourth control signal received from the second control means.
- the fourth delay circuit 46 delays the signal output from the fifth AND circuit 44 and outputs the delayed signal.
- the sixth AND circuit 48 outputs an inverted signal of the logical product of the signal output by the fourth AND circuit 40 and the signal output by the fourth delay circuit 46.
- the second control means supplies a third control signal and a fourth control signal according to the operation mode of the pulse width adjustment circuit 100.
- the second control means causes the second pulser 38 to output the second delay signal with the adjusted pulse width, output the second delay signal without adjusting the pulse width, or set / reset latch. It controls the force that causes the circuit 52 to output a signal for passing the first delay signal.
- the first control means and the second control means may be terminals for receiving a control signal from the outside and supplying the control signal to the first pulser 26 and the second pulser 38, respectively.
- the first control means supplies the first pulser 26 with the first delay signal having the adjusted pulse width. Output. That is, the first control means outputs H logic as the first control signal and the second control signal.
- the third AND circuit 36 of the first pulser 26 changes the pulse width of the first delay signal to a pulse width corresponding to the delay amount of the third delay circuit 34. Adjust and output.
- the second control means causes the second pulser 38 to output a second delay signal whose pulse width has been adjusted. That is, the second control means outputs H logic as the third control signal and the fourth control signal.
- the operation of the second pulser 38 is the same as the operation of the first pulser 26 shown in FIG. 7A, and the pulse width of the second delay signal is adjusted according to the delay amount of the fourth delay circuit 46. Adjust to pulse width and output.
- the set / reset latch circuit 52 receives the first delay signal and the second delay signal whose pulse widths have been adjusted from the first pulser 26 and the second pulser 38, and outputs the signal from the positive output terminal Q. Output a signal.
- the output unit 50 further includes a selection unit 60 that selects and outputs a difference between a signal output from the positive output terminal Q of the set / reset latch circuit 52 and a signal output from the negative output terminal ZQ.
- the selection unit 60 selects the signal output from the positive output terminal Q and outputs the signal to the variable delay circuit 102. With such an operation, the pulse width adjustment circuit 100 outputs the output signal whose pulse width has been adjusted to the outside.
- the first control means when the pulse width adjustment circuit 100 operates in the leading edge measurement operation mode, the first control means causes the first pulser 26 to adjust the pulse width. Output the first delay signal instead.
- the first control means outputs one of the first control signal or the second control signal in H logic, and outputs the other of the first control signal or the second control signal in L logic, thereby causing the first pulser 26 to pulse.
- the first delay signal can be output without adjusting the width.
- the first control means outputs an H logic as a first control signal and outputs an L logic as a second control signal.
- the output of the third delay circuit 34 is fixed to H logic, and the third AND circuit 36 passes the first delay signal.
- the second control means causes the second pulser 38 to output a signal for passing the first delay signal to the set / reset latch circuit 52. That is, the second control means outputs L logic as both the third control signal and the fourth control signal.
- the operation of the second pulser 38 in this case is the same as the operation of the first pulser 26 described later in FIG. A low-logic fixed signal is supplied to the reset terminal ZR of the latch circuit 52.
- a first delay signal whose pulse width is not adjusted is supplied to the set terminal ZS, and a signal of L logic fixed is supplied to the reset terminal ZR. Therefore, a signal obtained by inverting the first delay signal once is output from the positive output terminal Q of the set / reset latch circuit 52, and the negative output terminal ZQ is fixed at the H logic. Then, the selection section 60 outputs a signal that also receives the positive output terminal Q of the set / reset latch circuit 52. Then, the first delay signal output from the selection unit 60 is looped by the loop unit 114, and the calculation unit 110 calculates a first loop cycle in which the first delay signal is looped.
- the first control means controls the first pulser 26 to operate the set / reset latch circuit 52 To output a signal for passing the second delay signal.
- the first control means fixes the output of the first pulser 26 to L logic. That is, the first control means outputs L logic as the first control signal and the second control signal.
- the output of the first AND circuit 28 and the output of the third delay circuit 34 are fixed to H logic, and the output of the third AND circuit 36 is also fixed to L logic. Is done.
- the second control means causes the second pulser 38 to output the second delay signal without adjusting the pulse width.
- the second control means outputs one of the third control signal or the fourth control signal by H logic, and outputs the other of the third control signal or the fourth control signal by L logic, so that the second pulser 38 is pulsed.
- the second delay signal can be output without adjusting the width.
- the second control means outputs H logic as a third control signal and outputs L logic as a fourth control signal.
- the operation of the second pulser 38 in this case is the same as the operation of the first pulser 26 shown in FIG. 7 (b), the output of the fourth delay circuit 46 is fixed at H logic, and the sixth AND circuit 4 8 Pass the second delay signal.
- the set / reset latch circuit 52 a second delay signal whose pulse width is not adjusted is supplied to the reset terminal ZR, and a signal of L logic fixed is supplied to the set terminal ZR. Therefore, the positive output terminal Q of the set / reset latch circuit 52 is fixed to the H logic, and a signal obtained by inverting the second delay signal once is output from the negative output terminal ZQ.
- the selection section Reference numeral 60 denotes a negative output terminal of the set / reset latch circuit 52, which outputs a signal that also receives the ZQ force. Then, the second delay signal output from the selection unit 60 is looped by the loop unit 114, and the calculation unit 110 calculates a second loop cycle obtained by looping the second delay signal.
- operation unit 110 calculates the pulse width of the output signal that is output by pulse width adjustment unit 10 in the actual operation mode based on the difference between the second loop period and the first loop period.
- the difference between the second loop period and the first loop period is equal to the difference between the second delay amount in the second delay circuit 18 and the first delay amount in the first delay circuit 12. It is equal to the pulse width of the output signal output during the actual operation mode. Therefore, the arithmetic unit 110 can measure the pulse width of the output signal output in the actual operation mode.
- the pulse width adjustment unit 10 further includes means for adjusting the respective delay amounts in the first delay circuit 12 and the second delay circuit 18 such that the measured pulse width becomes substantially equal to the desired pulse width. It is preferred to have. In addition, the respective delay amounts in the first delay circuit 12 and the second delay circuit 18 are adjusted so that the measured first delay amount and second delay amount are substantially equal to the predetermined delay amount. Is also good. With such a configuration, it is possible to generate an output signal accurately controlled to a desired pulse width.
- the pulse width adjusting unit 10 in the present example the signal obtained by inverting the first delay signal and the second delay signal once is looped and the loop period is measured. And the like, the delay amounts of the respective delayed signals are equal. That is, in the variable delay circuit 102 and the like, no delay error occurs due to the direction of the signal edge. For this reason, the pulse width of the output signal output in the actual operation mode can be measured accurately, and an output signal whose pulse width has been adjusted accurately can be generated.
- the output unit 50 further include a buffer 58 between the negative output terminal ZQ of the set / reset latch circuit 52 and the selection unit 60.
- a path for generating a falling edge of the output signal according to the second delay signal in the actual operation mode is different from a path for passing the second delay signal in the trailing edge measurement operation mode. That is, in the actual operation mode, the second delay signal is input to the reset terminal ZR, and by operating the OR circuit 56 and the OR circuit 54, a signal corresponding to the second delay signal is output to the positive output terminal. Q force is output.
- the second delay signal is applied to the reset terminal ZR. The signal is input, passes through the OR circuit 56, and is output from the negative output terminal ZQ.
- the path in the actual operation mode is different from the path in the trailing edge measurement operation mode, and skew occurs.
- the skew causes a small error in the pulse width measurement.
- the buffer 58 functions as a delay unit for reducing the skew. With such a configuration, the pulse width can be measured more accurately.
- FIG. 8 is a flowchart showing an example of a pulse width adjustment method using the pulse width adjustment circuit 100.
- the pulse width adjustment and the pulse width measurement may be performed using all the functions of the pulse width adjustment circuit 100 described with reference to FIGS.
- an example of adjusting the pulse width will be described.
- a first delay signal is generated by delaying the pulse signal supplied to the pulse width adjustment circuit 100.
- S202 may be performed using the first delay circuit 12 described with reference to FIG.
- a second delay signal is generated by delaying the pulse signal by a delay amount different from that of the first delay stage.
- S204 may be performed using the second delay circuit 18 described in FIG.
- an output signal having a pulse width corresponding to the difference between the delay amount in the first delay step and the delay amount in the second delay step is converted into a first delay signal and a second delay signal.
- Generate based on S206 may be performed using the output unit 50 described with reference to FIG.
- the pulse width can be controlled by the delay resolution of the second delay circuit 18 with high resolution, and the pulse width is smaller than the offset delay amount in the second delay circuit 18.
- An output signal of a width can be generated.
- the pulse width adjustment circuit 100 described with reference to FIGS. 4 to 7 may be used as a timing signal generation circuit for defining a test timing in, for example, a semiconductor test apparatus for testing a semiconductor circuit.
- FIG. 9 is a diagram showing an example of a configuration of a semiconductor test apparatus 400 for testing a semiconductor circuit 450.
- the semiconductor test apparatus 400 includes a pattern generator 410, a timing signal generation circuit 420
- the pattern generator 410 generates a test pattern for testing the semiconductor circuit 450.
- the test pattern is, for example, a digital signal represented by a 1ZO pattern.
- the waveform shaper 420 receives the test pattern and shapes a test signal to be supplied to the semiconductor circuit 450 based on the received test pattern. For example, the waveform shaper 420 generates a test signal indicating a voltage level corresponding to the digital value of the test pattern and having substantially the same phase as the timing signal, in synchronization with the applied timing signal.
- Timing signal generation circuit 430 adjusts the pulse width of the given pulse signal to a predetermined pulse width, and supplies a timing signal obtained by delaying each pulse of the pulse signal to a predetermined phase to waveform shaper 420.
- the pulse signal is a rate signal having substantially the same cycle as the test cycle
- the timing signal generation circuit 430 adjusts the pulse width of each pulse of the noise signal to a predetermined pulse width, and The phase of each pulse of the signal is controlled to each desired phase.
- the timing signal generation circuit 430 may have the same function and configuration as the pulse width adjustment circuit 100 described with reference to FIGS. 4 to 7. In this case, the pulse width adjustment unit 10 adjusts the pulse width of each pulse of the pulse signal, and the variable delay circuit 102 controls the phase of each pulse.
- the determiner 440 determines pass / fail of the semiconductor circuit 450 based on the output signal output from the semiconductor circuit 450. For example, the determiner 440 determines the quality of the semiconductor circuit 450 by comparing the expected value signal given from the pattern generator 410 with the output signal.
- the pulse width of the timing signal can be accurately controlled. Therefore, the test of the semiconductor circuit 450 can be performed with high accuracy.
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Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2005517114A JP4956003B2 (ja) | 2004-01-20 | 2005-01-19 | パルス幅調整回路、パルス幅調整方法、及び半導体試験装置 |
DE112005000210T DE112005000210T5 (de) | 2004-01-20 | 2005-01-19 | Impulsbreiten-Einstellschaltung, Impulsbreiten-Einstellverfahren und Halbleiterprüfvorrichtung |
KR1020067016782A KR101179748B1 (ko) | 2004-01-20 | 2005-01-19 | 펄스폭 조정 회로, 펄스폭 조정 방법, 및 반도체 시험 장치 |
US11/487,897 US7460969B2 (en) | 2004-01-20 | 2006-07-17 | Pulse width adjustment circuit, pulse width adjustment method, and test apparatus for semiconductor device |
US12/102,540 US7574316B2 (en) | 2004-01-20 | 2008-04-14 | Pulse width adjustment circuit, pulse width adjustment method, and test apparatus for semiconductor device |
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JP2004011412 | 2004-01-20 | ||
JP2004-011412 | 2004-01-20 |
Related Child Applications (1)
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US11/487,897 Continuation US7460969B2 (en) | 2004-01-20 | 2006-07-17 | Pulse width adjustment circuit, pulse width adjustment method, and test apparatus for semiconductor device |
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WO2005069487A1 true WO2005069487A1 (ja) | 2005-07-28 |
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ID=34792334
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PCT/JP2005/000617 WO2005069487A1 (ja) | 2004-01-20 | 2005-01-19 | パルス幅調整回路、パルス幅調整方法、及び半導体試験装置 |
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US (2) | US7460969B2 (ja) |
JP (1) | JP4956003B2 (ja) |
KR (1) | KR101179748B1 (ja) |
DE (1) | DE112005000210T5 (ja) |
TW (1) | TWI348825B (ja) |
WO (1) | WO2005069487A1 (ja) |
Cited By (2)
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KR20150102548A (ko) * | 2014-02-28 | 2015-09-07 | 실리콘알엔디(주) | 초광대역 임펄스 발생기 |
WO2022190997A1 (ja) * | 2021-03-12 | 2022-09-15 | ソニーセミコンダクタソリューションズ株式会社 | 遅延調整回路および測距装置 |
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US7342407B2 (en) * | 2006-01-31 | 2008-03-11 | Advantest Corporation | Temperature compensation circuit and testing apparatus |
KR100794996B1 (ko) * | 2006-05-09 | 2008-01-16 | 주식회사 하이닉스반도체 | 반도체 메모리의 펄스 생성 장치 |
CN102124357A (zh) * | 2008-08-19 | 2011-07-13 | 爱德万测试株式会社 | 测试装置及测试方法 |
KR101008990B1 (ko) * | 2008-12-05 | 2011-01-17 | 주식회사 하이닉스반도체 | 버퍼인에이블신호 생성회로 및 이를 이용한 입력회로 |
KR101636497B1 (ko) * | 2009-07-10 | 2016-07-05 | 에스케이하이닉스 주식회사 | 클럭 전달회로 및 반도체 장치 |
JP2011081732A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びその調整方法並びにデータ処理システム |
US20130099835A1 (en) * | 2011-10-25 | 2013-04-25 | You-Wen Chang | Calibration apparatus for performing phase detection/edge distance detection upon signals and related calibration method thereof |
KR101451929B1 (ko) | 2013-01-18 | 2014-10-23 | 연세대학교 산학협력단 | 지연 동기 회로 및 듀티 사이클 교정 방법 |
CN103219970B (zh) * | 2013-04-02 | 2016-03-23 | 工业和信息化部电子第五研究所 | 单粒子瞬态脉冲宽度展宽方法与电路 |
US8917109B2 (en) * | 2013-04-03 | 2014-12-23 | United Microelectronics Corporation | Method and device for pulse width estimation |
TWI513985B (zh) * | 2013-04-03 | 2015-12-21 | United Microelectronics Corp | 脈波寬度估計方法與裝置 |
KR20150052634A (ko) * | 2013-11-06 | 2015-05-14 | 에스케이하이닉스 주식회사 | 반도체 장치 |
KR101699325B1 (ko) | 2014-10-20 | 2017-01-24 | 대우조선해양 주식회사 | 부유 저장식 발전플랜트 및 그 부유 저장식 발전플랜트의 냉각 가열 운전방법 |
US10276229B2 (en) * | 2017-08-23 | 2019-04-30 | Teradyne, Inc. | Adjusting signal timing |
US12041713B2 (en) | 2017-08-23 | 2024-07-16 | Teradyne, Inc. | Reducing timing skew in a circuit path |
US11442098B2 (en) | 2019-06-20 | 2022-09-13 | Teradyne, Inc. | Generating a waveform based on digital pulses |
CN111342821B (zh) * | 2020-03-03 | 2023-05-23 | 合肥工业大学 | 基于fpga的单粒子瞬态脉冲产生和测量系统及其方法 |
US11456729B1 (en) | 2021-03-26 | 2022-09-27 | Analog Devices, Inc. | Deskew cell for delay and pulse width adjustment |
US12028076B1 (en) * | 2023-02-27 | 2024-07-02 | Renesas Electronics America Inc. | Circuit and method for determining a delay of a delay circuit |
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- 2005-01-19 KR KR1020067016782A patent/KR101179748B1/ko not_active IP Right Cessation
- 2005-01-19 JP JP2005517114A patent/JP4956003B2/ja not_active Expired - Fee Related
- 2005-01-19 WO PCT/JP2005/000617 patent/WO2005069487A1/ja active Application Filing
- 2005-01-20 TW TW094101633A patent/TWI348825B/zh not_active IP Right Cessation
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2006
- 2006-07-17 US US11/487,897 patent/US7460969B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
DE112005000210T5 (de) | 2007-03-01 |
KR20070003866A (ko) | 2007-01-05 |
JPWO2005069487A1 (ja) | 2007-12-27 |
JP4956003B2 (ja) | 2012-06-20 |
TW200525891A (en) | 2005-08-01 |
US7574316B2 (en) | 2009-08-11 |
US20080201099A1 (en) | 2008-08-21 |
TWI348825B (en) | 2011-09-11 |
US20080018371A1 (en) | 2008-01-24 |
US7460969B2 (en) | 2008-12-02 |
KR101179748B1 (ko) | 2012-09-04 |
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