WO2005048331A1 - シリコンエピタキシャルウェーハの製造方法 - Google Patents
シリコンエピタキシャルウェーハの製造方法 Download PDFInfo
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- WO2005048331A1 WO2005048331A1 PCT/JP2004/012179 JP2004012179W WO2005048331A1 WO 2005048331 A1 WO2005048331 A1 WO 2005048331A1 JP 2004012179 W JP2004012179 W JP 2004012179W WO 2005048331 A1 WO2005048331 A1 WO 2005048331A1
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- oxide film
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 183
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 183
- 239000010703 silicon Substances 0.000 title claims abstract description 183
- 238000000034 method Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 134
- 239000013078 crystal Substances 0.000 claims abstract description 131
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000002019 doping agent Substances 0.000 claims abstract description 32
- 238000010306 acid treatment Methods 0.000 claims abstract description 18
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052796 boron Inorganic materials 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 6
- 239000011574 phosphorus Substances 0.000 claims abstract description 6
- 238000000407 epitaxy Methods 0.000 claims description 49
- 238000001947 vapour-phase growth Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000012298 atmosphere Substances 0.000 claims description 15
- 239000012808 vapor phase Substances 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000007598 dipping method Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 46
- 239000007789 gas Substances 0.000 description 15
- 239000001257 hydrogen Substances 0.000 description 12
- 229910052739 hydrogen Inorganic materials 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 10
- 239000012535 impurity Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000012071 phase Substances 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 2
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N hydrochloric acid Substances Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- -1 hydrochloric acid peroxide Chemical class 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 235000012771 pancakes Nutrition 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
- H01L21/02661—In-situ cleaning
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Definitions
- the present invention relates to a method for manufacturing a silicon epitaxy in which a silicon epitaxy layer is formed on a main surface of a silicon single crystal substrate.
- the vapor-phase epitaxial growth method is a method of growing a single-crystal thin film having the same plane orientation as a silicon single-crystal substrate, that is, a silicon epitaxy layer, by supplying a source gas onto a main surface of the silicon single-crystal substrate. It is.
- a high-resistivity silicon epitaxy layer is formed on a main surface of a low-resistivity silicon single crystal substrate having high-concentration boron, arsenic, or phosphorus as a dopant.
- a phenomenon in which a dopant is temporarily released from the silicon single crystal substrate into the gas phase and doped into the growing silicon epitaxial layer that is, a so-called auto-doping phenomenon occurs.
- the impurity profile at the interface between the crystal substrate and the silicon epitaxial layer may be moderate.
- the cap layer (sub-epitaxial) must be supplied without supplying the dopant gas from outside before forming the main epitaxy layer on the main surface of the silicon single crystal substrate.
- Layer may be previously formed at a low temperature (for example, see Patent Documents 1 and 2).
- the formation temperature of the cap layer is low.
- a low temperature of less than 1000 ° C. for example, 500 ° C. to 850 ° C. to perform a vapor phase growth of the cap layer while maintaining a good crystalline state.
- Patent Document 2 it is necessary to remove the native oxide film formed on the main surface of the silicon single crystal substrate by performing a treatment with hydrofluoric acid vapor or the like in advance in the main or sub chamber.
- a silicon oxide film for preventing autodoping may be formed on the back surface of the silicon single crystal substrate in advance.
- Patent Document 1 JP-A-58-41799
- Patent Document 2 JP-A-9-120947
- the present invention has been made to solve the above-mentioned problems, and has been made in order to solve the above-mentioned problems.
- a silicon epitaxy capable of vapor-phase growing a silicon epitaxy layer having a steeper impurity concentration profile on a main surface of a silicon single crystal substrate. The purpose is to provide a method for manufacturing an eha.
- the first of the methods for producing the silicon epitaxy of the present invention is boron, arsenic or lithium.
- the main epitaxy layer forming step of forming the main epitaxy layer on the sub epitaxy layer By performing the main epitaxy layer forming step of forming the main epitaxy layer on the sub epitaxy layer in this order, the main epitaxy layer and the sub epitaxy layer are formed on the main surface of the silicon single crystal substrate.
- a silicon oxide film for preventing auto-doping was formed on the back surface
- the oxide film formed on the main surface of the silicon single crystal substrate is wet-etched while the silicon oxide film for preventing autodoping is left. Even when a low-temperature cap layer is grown, a silicon oxide film can be applied to prevent autodoping. Therefore, it becomes possible to vapor-grow a silicon epitaxial layer having a steep impurity concentration profile on the main surface of the silicon single crystal substrate.
- the silicon single crystal substrate is exposed to the air between the hydrofluoric acid treatment step and the sub-epitaxial layer formation step, a natural oxide film is formed.
- the natural oxide film formed on the main surface of the silicon single crystal substrate is dry-etched.
- the baking step is performed while heating the silicon single crystal substrate to a temperature lower than the growth temperature of the main epitaxial layer, for example, 950 ° C. or lower.
- the silicon single crystal substrate is heated to a temperature higher than 950 ° C during the baking process, the auto-doping phenomenon cannot be ignored. How big it is.
- the sub-epitaxial layer may be formed to a thickness of, for example, less than 0.5 / im so as to suppress autodoping from the main surface of the silicon single crystal substrate.
- the thickness of the sub-epitaxial layer may be 0.5 xm or more, the thickness of the sub-epitaxial layer may be larger than the outward diffusion width of the dopant from the silicon single crystal substrate.
- the silicon single crystal substrate and the sub-epitaxial layer are almost indistinguishable due to outward diffusion of the dopant from the silicon single-crystal substrate during a series of heat treatments performed after the growth of the sub-epitaxial layer.
- the accuracy of the thickness and resistivity of the epitaxial layer does not matter much. Therefore, the productivity of the silicon epitaxy wafer can be increased by performing the sub-epitaxial layer formation step during the temperature rise of the silicon single crystal substrate whose thickness and resistivity are apt to change.
- the time for exposing the silicon single crystal substrate to the air between the hydrofluoric acid treatment step and the baking step is within 60 minutes. During this time, the thickness of the natural oxide film formed on the surface of the silicon single crystal substrate is very small, so for example, by performing a baking process in a hydrogen gas atmosphere while heating the silicon single crystal substrate to 900 ° C, The natural oxide film is instantly etched away.
- the time for exposing the silicon single crystal substrate to the atmosphere exceeds 60 minutes, the time for the baking process may be extended or the baking temperature for the silicon single crystal substrate may be increased to 950 ° C to etch away the natural oxide film. Higher than the above, and both are not preferred because they increase the effect of the autodoping phenomenon.
- the silicon single crystal substrate is heated to a temperature of 900 ° C or more and 1200 ° C or less, and the main epitaxy layer is formed on the sub-epitaxial layer. Even if a layer is formed, a silicon epitaxial wafer can be manufactured in a state where the auto-doping phenomenon is suppressed.
- the silicon single crystal substrate is heated to a temperature higher than 1200 ° C to grow the main epitaxy layer by gas phase, the sub-epitaxial layer or the silicon oxide film for preventing autodoping is used.
- the amount of the dopant that diffuses outward through the diffusion may become extremely large, and the autodoping phenomenon may no longer be able to be suppressed.
- the main epitaxial layer is vapor-phase grown by heating a silicon single crystal substrate to a temperature of less than 900 ° C., the amount of dopant release from the substrate itself is suppressed, and the significance of applying the present invention is reduced. I do.
- the second method of the present invention for producing silicon epitaxial # 18 is:
- Boron, arsenic, or phosphorus is added as a dopant to a concentration of 1 ⁇ 10 19 / cm 3 or more, and a silicon single crystal substrate with a silicon oxide film for preventing auto-doping formed on the back surface is used.
- the time for exposing the silicon single crystal substrate to the atmosphere is set to 60 minutes or less, and the silicon single crystal substrate is put into the vapor phase growth apparatus, and the silicon single crystal substrate is heated to a temperature of 950 ° C or less.
- a sub-epitaxial layer having a thickness of less than 0.5 xm is formed on the main surface of the silicon single crystal substrate.
- a steeper impurity profile is formed on the main surface of the silicon single crystal substrate.
- the silicon epitaxy layer can be vapor-phase grown by using
- FIG. 1 is a diagram showing a manufacturing process of a silicon epitaxial wafer according to the present embodiment and a cross-sectional view of a silicon single crystal substrate or the like in each process.
- FIG. 2 is a diagram showing a dopant profile when using a method for manufacturing a silicon epitaxial wafer according to the present invention and a dopant profile when using a conventional method for manufacturing a silicon epitaxial wafer. It is.
- FIG. 1 shows a manufacturing process of a silicon epitaxial wafer according to the embodiment of the present invention
- the left side shows a cross-sectional view of a silicon single crystal substrate CW and the like corresponding to each process.
- a silicon single crystal rod to which boron, arsenic or phosphorus is added as a dopant at a concentration of 1 ⁇ 10 19 / cm 3 or more is pulled up by the CZ (Czochralski) method.
- CZ Czochralski
- the second main surface (lower surface in Fig. 1) of the silicon single crystal substrate CW is subjected to CVD (
- a silicon oxide film 1 for preventing auto-doping (hereinafter simply referred to as a CVD oxide film) is formed using a Chemical Vapor D mark osition method (Step S2).
- a monosilane (SiH) gas and an oxygen gas are supplied as source gases to the second main surface of a silicon single crystal substrate CW heated to 350-450 ° C, and a CV having a thickness of about 500 nm is formed.
- the D oxide film 1 is grown in vapor phase.
- the first main surface opposite to the surface on which the CVD oxide film 1 is formed is subjected to mechanical and chemical polishing (step S3), and the first main surface in a mirror state is formed.
- This is a silicon single crystal substrate PW having a surface.
- the silicon single crystal substrate PW was cleaned with SC-1 (ammonia-hydrogen peroxide solution) and SC-2 (hydrochloric acid peroxide) to remove organic substances, metals, particles, etc. attached to the surface. Cleaning using hydrogen water) cleaning is performed (step S4).
- the silicon single crystal substrate PW A silicon oxide film is formed on the surface of the substrate.
- a natural oxide film with a thickness that cannot be removed by low-temperature heat treatment at 950 ° C or less will be formed.
- these oxide films 5 remain during the formation of the sub-epitaxial layer 2 to be grown at a low temperature in a later step, they adversely affect the crystallinity of the sub-epitaxial layer 2.
- a hydrofluoric acid treatment step of wet etching with hydrofluoric acid is performed, and the oxide film 5 formed on the surface of the silicon single crystal substrate PW is removed (step S5).
- the CVD oxide film 1 formed on the second main surface of the silicon single crystal substrate PW to prevent autodoping is also removed by etching by hydrofluoric acid treatment, use a diluted hydrofluoric acid having a concentration of about 1%.
- the oxide film 5 is removed by wet etching while the CVD oxide film 1 remains. Since the thickness of the silicon oxide film removed by etching during this period is about 6 nm, the oxide film 5 having a thickness of about 12 nm is completely removed, while the CVD oxide film 1 having a thickness of about 500 nm remains.
- the silicon single crystal substrate PW is put into a vapor phase growth apparatus without exposing it to the atmosphere for more than 60 minutes (step S6). After being put into the vapor phase growth apparatus, the silicon single crystal substrate PW is placed in a non-oxidizing atmosphere, so that the natural oxide film 6 is not formed thereafter.
- the input vapor phase growth apparatus is a pancake type or barrel type. In the case of (cylinder type), the silicon single crystal substrate PW is directly mounted on the susceptor in the vapor phase growth furnace, and the air in the vapor phase growth furnace is replaced with nitrogen, and then further replaced with hydrogen. The vapor phase growth process is performed.
- the silicon single-crystal substrate PW is temporarily stored in a load lock chamber maintained in a nitrogen atmosphere, and then transferred to a vapor-phase growth furnace maintained in a hydrogen atmosphere.
- the vapor phase growth step is performed in a hydrogen atmosphere.
- the silicon single crystal substrate PW placed in the vapor phase growth furnace is heated in a hydrogen atmosphere, and is heated at a temperature of 950 ° C or less (for example, 900 ° C) for 5 minutes or less (for example, for 1 to 12 minutes). It is baked for only the time (step S7).
- the natural oxide film 6 regenerated on the main surface of the silicon single crystal substrate PW during the period from the hydrofluoric acid treatment to the introduction into the vapor phase growth apparatus is removed by dry etching.
- the natural oxide film 6 and the like formed on the surface of the silicon single crystal substrate PW are removed in advance by wet etching by hydrofluoric acid treatment, and then the silicon oxide is prevented from being regenerated as much as possible.
- the crystal substrate PW By introducing the crystal substrate PW into the vapor phase growth equipment, the temperature required for SiO to be reduced by H and evaporate as Si
- the natural oxide film 6 regenerated on the silicon single crystal substrate PW can also be completely removed by dry etching using hydrogen baking under a relatively low temperature condition of 950 ° C. or lower. Therefore, outward diffusion of the dopant from the silicon single crystal substrate PW into the gas phase, which causes the autodoping phenomenon, can be suppressed. In addition, since the natural oxide film 6 is completely removed, the epitaxial layer having good crystallinity can be vapor-phase grown even at a relatively low temperature of 700 ° C or more and 950 ° C or less.
- the raw material gas eg, SiH CI
- Step S8 is supplied onto the silicon single crystal substrate PW together with the carrier gas hydrogen, whereby the sub-epitaxial layer 2 is vapor-phase-grown on the first main surface of the silicon single crystal substrate PW to form a silicon single crystal.
- the first main surface of the substrate PW is covered, and the autodoping phenomenon from the main surface of the silicon single crystal substrate PW is suppressed (Step S8).
- the sub-epitaxial layer 2 was grown in a gas phase after hydrogen baking under high temperature conditions. Therefore, in order to suppress the auto-doping phenomenon, the temperature was lowered and the silicon epitaxy was performed during hydrogen baking. It was necessary to purge the dopant released into the gas phase from the crystal substrate PW. However, in this embodiment, since the hydrogen blanking is performed under relatively low temperature conditions, the dopant is not released into the gas phase. , The onset of the auto-doping phenomenon can be kept to the minimum level that necessarily occurs at the starting temperature of the vapor phase growth.
- the sub-epitaxial layer 2 is formed at a predetermined temperature (for example, 1000 ° C.) immediately after the completion of the hydrogen baking while raising the temperature of the silicon single crystal substrate PW toward the vapor phase growth temperature of the main epi-layer 3. (° C), the deposition is carried out by vapor phase epitaxy of a thickness of less than 0.5 ⁇ m, for example 0.2 ⁇ m. As described above, by making the thickness of the sub-epiaxial layer 2 less than 0.5 zm, more preferably, the thickness of the sub-epiaxial layer 2 is further reduced to one-tenth of the thickness of the main epitaxy layer 3.
- a predetermined temperature for example, 1000 ° C.
- the thickness of the sub-epitaxial layer 2 By setting the thickness below, it is possible to prevent the thickness of the sub-epitaxial layer 2 from becoming larger than the out-diffusion width of the PW force of the silicon single crystal substrate and the like, so that the sub-epitaxial layer 2 becomes apparent. Without this, a sharp dopant profile can be realized at the interface between the silicon single crystal substrate PW and the epitaxial layer.
- a main epitaxy layer 3 of the same conductivity type as the silicon single crystal substrate PW is vapor-phase-grown on the surface of the sub-epitaxial layer 2 (Step S9). More specifically, the silicon single crystal substrate PW is heated to a temperature of 900 ° C or more and 1200 ° C or less (for example, about 1130 ° C), and a raw material gas is formed on the main surface of the sub-epitaxial layer 2 together with the carrier gas.
- a source gas for example, SiH CI, SiHCl or SiH, etc.
- the main epitaxy layer 3 is formed so that the resistivity of the main surface is at least 20 times that of the silicon single crystal substrate PW.
- the first main surface of the silicon single crystal substrate PW is covered with the sub-epitaxial layer 2
- the second main surface is covered with the CVD oxide film 1
- the baking step Since the dopant is hardly released from the silicon single crystal substrate PW into the gas phase during the pre-heat treatment such as (Step S7), the main epitaxy is formed on the first main surface of the silicon single crystal substrate PW with a steeper impurity profile.
- Layer 3 can be vapor grown.
- the silicon epitaxy layer was formed on the main surface of the silicon single crystal substrate PW by the method of manufacturing a silicon epitaxy wafer in the above embodiment.
- As the silicon single crystal substrate PW arsenic was added to a concentration of 2 ⁇ 10 19 / cm 3 and the resistivity was about 3.5 ⁇ .
- the silicon single crystal substrate PW was heated at 900 ° C.
- the thickness of the sub-epitaxial layer was 0.08 ⁇ m.
- the formation temperature of the main epitaxial layer was set at 1130 ° C, and the thickness of the entire silicon epitaxial layer was set at 1.
- the comparative example was performed under the same conditions as in the example except that the baking step was performed by raising the temperature of the silicon single crystal substrate PW to 1150 ° C.
- FIG. 2 shows the result of forming a silicon epitaxy layer by the method of manufacturing silicon epitaxy wafers of the above Examples and Comparative Examples.
- the dopant concentration is not constant up to the vicinity of the surface of the silicon epitaxial layer where the effect of autodoping is large, but in the example, the dopant concentration is 0.6 ⁇ m or more from the surface of the silicon epitaxial layer. A region with a flat dopant concentration was obtained up to a depth of.
- the silicon epitaxial layer can be formed with a steeper dopant profile according to the method of manufacturing a silicon epitaxial wafer according to the present invention.
- the method of manufacturing a silicon epitaxial layer 8 which is effective in the present invention is suitable for vapor-phase growing a silicon epitaxial layer having a steeper impurity concentration profile on the main surface of a silicon single crystal substrate. It is useful and is particularly suitable for vapor-phase growth of a silicon epitaxial layer on the main surface of a low-resistivity silicon single crystal substrate.
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Abstract
Description
Claims
Priority Applications (3)
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EP04772140A EP1684335A4 (en) | 2003-11-14 | 2004-08-25 | PROCESS FOR PRODUCING EPITAXIAL SILICON PLATEBOARD |
US10/578,369 US20070054468A1 (en) | 2003-11-14 | 2004-08-25 | Method for producing silicon epitaxial wafer |
KR1020067009216A KR101079176B1 (ko) | 2003-11-14 | 2004-08-25 | 실리콘 에피택셜 웨이퍼의 제조방법 |
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JP2003385333A JP4682508B2 (ja) | 2003-11-14 | 2003-11-14 | シリコンエピタキシャルウェーハの製造方法 |
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US (1) | US20070054468A1 (ja) |
EP (1) | EP1684335A4 (ja) |
JP (1) | JP4682508B2 (ja) |
KR (1) | KR101079176B1 (ja) |
CN (1) | CN100442442C (ja) |
WO (1) | WO2005048331A1 (ja) |
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US7485928B2 (en) | 2005-11-09 | 2009-02-03 | Memc Electronic Materials, Inc. | Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering |
KR100827038B1 (ko) * | 2006-12-21 | 2008-05-02 | 주식회사 실트론 | 헤이즈가 없는 실리콘 에피택셜 웨이퍼의 제조 방법 |
KR20080058841A (ko) * | 2006-12-22 | 2008-06-26 | 동부일렉트로닉스 주식회사 | 수직형 시모스 이미지 센서 및 그 제조 방법 |
JP5272329B2 (ja) * | 2007-05-22 | 2013-08-28 | 信越半導体株式会社 | Soiウエーハの製造方法 |
JP2009302397A (ja) * | 2008-06-16 | 2009-12-24 | Nuflare Technology Inc | 気相成長方法および気相成長装置 |
JP2010003735A (ja) * | 2008-06-18 | 2010-01-07 | Sumco Techxiv株式会社 | エピタキシャルウェーハの製造方法及びエピタキシャルウェーハ |
JP2010098284A (ja) * | 2008-09-19 | 2010-04-30 | Covalent Materials Corp | エピタキシャル基板用シリコンウェハの製造方法及びエピタキシャル基板の製造方法 |
JP5463693B2 (ja) * | 2009-03-03 | 2014-04-09 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法 |
EP2251897B1 (en) * | 2009-05-13 | 2016-01-06 | Siltronic AG | A method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side |
FR2955707B1 (fr) * | 2010-01-27 | 2012-03-23 | Commissariat Energie Atomique | Procede de realisation d'une cellule photovoltaique avec preparation de surface d'un substrat en silicium cristallin |
JP2014013835A (ja) * | 2012-07-04 | 2014-01-23 | Shin Etsu Handotai Co Ltd | シリコンエピタキシャルウェーハの製造方法 |
JP6241381B2 (ja) * | 2014-07-09 | 2017-12-06 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
CN107305839B (zh) * | 2016-04-18 | 2020-07-28 | 中芯国际集成电路制造(上海)有限公司 | 防止自掺杂效应的方法 |
KR102476797B1 (ko) | 2016-10-05 | 2022-12-09 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
KR102279113B1 (ko) * | 2017-04-06 | 2021-07-16 | 가부시키가이샤 사무코 | 에피택셜 실리콘 웨이퍼의 제조 방법 및 에피택셜 실리콘 웨이퍼 |
KR20190011475A (ko) * | 2017-07-25 | 2019-02-07 | 에스케이실트론 주식회사 | 웨이퍼 제조 방법 및 웨이퍼 |
CN109003885A (zh) * | 2018-07-04 | 2018-12-14 | 上海晶盟硅材料有限公司 | 双面抛光外延片的制作方法、外延片及半导体器件 |
CN110942986A (zh) * | 2018-09-21 | 2020-03-31 | 胜高股份有限公司 | 形成于硅晶圆的表面的氧化膜的去除方法 |
CN112553685A (zh) * | 2019-09-25 | 2021-03-26 | 丁欣 | 单晶硅片材的制造方法 |
CN113333374B (zh) * | 2021-06-10 | 2023-05-02 | 厦门士兰明镓化合物半导体有限公司 | 石墨盘的清洗方法 |
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- 2004-08-25 EP EP04772140A patent/EP1684335A4/en not_active Withdrawn
- 2004-08-25 WO PCT/JP2004/012179 patent/WO2005048331A1/ja active Application Filing
- 2004-08-25 CN CNB2004800336657A patent/CN100442442C/zh active Active
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Also Published As
Publication number | Publication date |
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US20070054468A1 (en) | 2007-03-08 |
CN1883032A (zh) | 2006-12-20 |
CN100442442C (zh) | 2008-12-10 |
EP1684335A1 (en) | 2006-07-26 |
KR101079176B1 (ko) | 2011-11-02 |
KR20060123147A (ko) | 2006-12-01 |
JP4682508B2 (ja) | 2011-05-11 |
JP2005150364A (ja) | 2005-06-09 |
EP1684335A4 (en) | 2009-05-06 |
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