Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0135—Manufacturing their gate conductors
  • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0144—Manufacturing their gate insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0147—Manufacturing their gate sidewall spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0172—Manufacturing their gate conductors
  • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• This invention relates to making integrated circuits using metal gates, and more particularly, to making integrated circuits using metal gates of differing structures.
• titanium nitride for the P channel transistors and tantalum silicon nitride for N channel transistors.
• the etchants typically used for these materials are not sufficiently selective to the gate dielectric and silicon substrate thus gouging may occur in the silicon substrate. This arises because in the P channel active regions, the titanium nitride is under the tantalum silicon nitride.
• the etch process that is used for the removal of the tantalum silicon nitride over the P channel active regions is necessary to expose the titanium nitride for subsequent etching also exposes the gate dielectric in the N channel active regions.
• the etch of the titanium nitride is also applied to the exposed gate dielectric in the N channel active regions where source/drains are to be formed.
• This etch of the titanium nitride may have the adverse effect of also removing the exposed gate dielectric and gouging the underlying silicon where the source/drains are to be formed.
• FIGs. 1-4 are cross sections of a semiconductor device according to a first embodiment of the invention at sequential stages in processing. Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
• a semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric.
• the N channel gate stack and a portion of the P channel gate stack are etched by a dry etch process.
• the etch of P channel gate stack is completed with a wet etch process.
• the wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely affected by completing the etch of the P channel gate stack.
• FIG. 1 Shown in FIG. 1 is a semiconductor device 10 comprising a silicon on insulator (SOI) substrate 12, a gate dielectric 14 directly on a top surface of SOI substrate 12, a layer 16 of titanium nitride, a layer 18 of tantalum silicon nitride, a layer 20 of polysilicon, an antireflective coating (ARC) layer 22 of silicon-rich silicon nitride, and patterned photoresist portions 24 and 26.
• SOI substrate 12 has a silicon substrate 28, an insulator layer 30, an N region 34, an isolation region 32, and a P region 36.
• Insulating layer 30 is preferably silicon oxide but may be another insulating material. Further a bulk silicon substrate may be used instead of a SOI substrate.
• Layer 16 overlies N region 34 but not region 36 and is in direct contact with gate dielectric 14.
• Layer 18 overlies SOI substrate 12 including layer 16 and P region 36.
• Layer 20 overlies layer 18.
• Layer 22 overlies layer 20.
• Patterned photoresist portion 24 overlies a portion of N region 34 where a P channel gate stack is to be formed.
• patterned photoresist portion 26 overlies P region 36 where an N channel gate stack is to be formed.
• the thickness of layers 16 and 18 is preferably 50 Angstroms but could be as low as 30 Angstroms or could be higher than 50 Angstroms.
• the width of patterned photoresist portions 24 and 26, which is going to be used for determining the length of transistor gates, is preferably 500 Angstroms, about ten times the thickness of the metal layers 16 and 18.
• the width of isolation region 32 is about the same as the width of patterned photoresist portions 24 and 26. These dimensions can be either smaller or larger depending on the particular technology that is being used.
• lithography challenges may limit, in production, the minimum dimension for the patterned photoresist portions 24 and 26 to be only 500 Angstroms or even 1000 Angstroms but the thicknesses of layers 16 and 18 could still be held at 50 Angstroms.
• ARC layer 22 is preferably 200 Angstroms thick.
• FIG. 2 Shown in FIG. 2 is the result of the dry etch that leaves gate stacks 37 and 39 over N region 34 and P region 36, respectively.
• Gate dielectric 14 is exposed over P region 36 except as covered by gate stack 39.
• Layer 16, which is over N region 34, is exposed except as covered by gate stack 37.
• Patterned photoresist portions 24 and 26 may have been eroded.
• Both gate stacks 37 and 39 have portions of ARC 22, layer 20, and layer 18.
• This dry etch which forms gate stacks 37 and 39 of FIG. 2 is preferably achieved in three etch steps.
• One step is for the silicon nitride ARC layer 22 and is preferably a reactive ion etch (RIE) that is halogen based.
• RIE reactive ion etch
• etch of layer 20 of polysilicon by RIE in a halogen based chemistry.
• the etch of layer 18 which is performed by RIE that is halogen. based.
• RIE halogen. based.
• the typical etch of titanium nitride is by RIE that is also halogen based.
• the difficulty with this is that the titanium nitride is not sufficiently selective to the gate dielectric, which in this case is preferably silicon oxynitride. Silicon oxynitride has a higher dielectric constant than silicon oxide and is more resistant to the halogen based RIE etch as well but not sufficiently resistant to avoid being penetrated by it during such an etch of titanium nitride of the needed thickness.
• halogen based RIE etches vary somewhat and are ultimately determined experimentally based on the actual layers being etched. These etches of these materials are conventional and conventionally determined. If silicon oxide is used as the gate dielectric, the same etch issues are present and in fact are even worse because the typical dry etch for metal-containing materials such as those used for layers 16 and 18 is even less selective to silicon oxide than to silicon oxynitride.
• the thickness of the titanium nitride is desirably thin for processing purposes but also desirably has enough thickness to be deterministic of the work function that controls the channel of the subsequently formed transistor.
• the gate dielectric preferably has a dielectric constant that is greater than 3.9.
• the optimum work function for N channel transistor gates and P channel transistor gates is generally considered to be at the silicon energy band edges, i.e., 4.1 electron volts (eV) and 5.2 eV, respectively. This is true for both bulk silicon and for partially depleted SOI.
• the N channel metal gate should have a work function of less than or equal to 4.4 eV and the P channel metal gate should have a work function of more than 4.6 eV for a partially depleted SOI substrate or bulk semiconductor substrate, which is the present case.
• Layer 16 of titanium nitride has a work function of 4.65 ev
• layer 18 of tantalum silicon nitride has a work function of 4.4 eV.
• a lesser work function differential may be satisfactory for fully depleted SOI substrates.
• a wet etch is used instead of using the conventional RIE etch to etch layer 16, a wet etch is used.
• the wet etch is preferably a piranha clean which is comprised of sulfuric acid and hydrogen peroxide in solution with water. Other wet etches may also be effective for this.
• a piranha clean is particularly beneficial because it is commonly available in a fabrication facility and is thus well understood how to apply and control. This piranha clean is very selective to both tantalum silicon nitride and silicon oxynitride, as well as silicon oxide.
• FIG. 3 This shows the completion of gate stack 37 and minimal change to gate stack 39.
• Patterned photoresist portions 24 and 26 are removed during this piranha clean. Removal of a material in a wet clean it is generally isotropic so that it etches laterally as well as vertically.
• This undercutting is generally not greater than the thickness of the layer being etched. In this case the preferred thickness of layer 16 is 50 Angstroms so the undercutting at the interface between layers 16 and 18 could be around 50 Angstroms, which is about 10% of the gate length and with less undercutting toward the gate dielectric 14.
• gate stacks 37 and 39 are in condition to complete the formation of transistors in a conventional manner.
• transistors 38 and 40 Shown in FIG. 4 are completed transistors 38 and 40 using gate stacks 37 and 39. ARC layer 22 is removed from both gate stacks 37 and 39 and transistors 38 and 40 are able to be made in conventional fashion.
• Transistor 38 is a P channel transistor having source/drains 42 and 44, a sidewall spacer 46, a liner 48, and suicide regions 50, 52, and 54. Suicide regions 50 and 52 are formed over and in contact with source/drains 42 and 44, respectively. Similarly, suicide region 54 is formed over and in contact with the portion of layer 20 that is part of gate stack 37 as shown in FIG. 3.
• Transistor 40 is an N channel transistor having source/drain regions 56 and 58, a sidewall spacer 60, a liner 62, and suicide regions 64 and 66. Suicide regions 64 and 66 are on and in contact with source/drains 56 and 58, respectively.
• the overlying conductor to itself be layered or be an alloy with a graded concentration of one of the materials.
• the two different layers 16 and 18 may be different materials than that specified herein.

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• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Electrodes Of Semiconductors (AREA)
• Thin Film Transistor (AREA)

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• 2003
  • 2003-04-09 US US10/410,043 patent/US6790719B1/en not_active Expired - Lifetime
• 2004
  • 2004-04-08 KR KR1020057019065A patent/KR101159339B1/ko not_active Expired - Fee Related
  • 2004-04-08 WO PCT/US2004/010814 patent/WO2004093182A1/en not_active Ceased
  • 2004-04-08 JP JP2006509809A patent/JP4653735B2/ja not_active Expired - Fee Related
  • 2004-04-08 CN CNB2004800094963A patent/CN100487880C/zh not_active Expired - Fee Related
  • 2004-04-09 TW TW093110018A patent/TWI342044B/zh not_active IP Right Cessation

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