TWI342044B - Process for forming dual metal gate structures - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Description
1342044 九、發明說明: [先前申請案之參考] 此申請案已於2003年4月9曰在美國提出申請,其專利申 請案號為10/410,043。 【發明所屬之技術領域】 本發明係關於使用金屬閘極來製造積體電路,且更明確 地說,本發明係關於使用不同結搆之金屬閉極來製造積體 電路。 【先前技術】 隨著半導體裳置在幾何學方面·Γ直按比例縮減,習知之 多晶石夕問極正變得缺乏(inadequate)。_個問題為相對高的 電阻率,且個問題為會在位於多曰曰曰石夕閑極與間極介電 之間的介面附近的位置中耗盡多晶矽閘極中的摻雜劑。為 克服此等多晶矽之不足,正將金屬閘極作為替代物來推 行。就P通道電晶體及N通道電晶體之所需功能而言,用於 N通道及p通道電晶體之金屬的工作函數應不相同。因此, 可將兩種不同種類的金屬用作直接位於閘極介電上的金 屬。通常不能簡單地來沈積或蝕刻能有效用於此目的之金 屬。兩種已發現有效的金屬為用於P通道電晶體之氮化鈦及 用於N通道電晶體之氮化矽钽。然而,一般用於此等材料之 蝕刻劑並不對閘極介電及矽基板具有充足的選擇性,因此 可在矽基板中出現挖鑿(gouging)現象。産生此現象的原因 係:在P通道之活性區域中,氮化鈦位於氮化矽鈕之下。用 於移除P通道活性區域之上的氮化矽鈕的蝕刻程序有必要 92528.doc 1342044 將用於隨後之姓刻的氛化鈦曝光,該㊣後之餘刻亦將n通道: 活性區域中之閘極介電曝光。結果,亦將敗化欽之餘刻施: 用於其中將形成源極/汲極之N通道活性區域中的已曝光之 、 閘極介電。此對氮化鈦之蝕刻亦具有以下不利影響:移除 已曝光之閘極介電並在纟中㈣成源極/汲極㈣域來挖 馨位於下面(underlying)的石夕。 因此,需要一種用於形成雙閘極電晶體之方法,該方法 能解決上述問題。 【發明内容】 ^ —種用於形成一個雙金屬閘極結搆之程序,其包括: 提供一具有一第一區域及一第二區域之半導體基板,其 中。亥第一區域具有一第一導電類型且該第二區域具有一第 導電類型,其不同於該第一導電類型; 形成一覆蓋該半導體基板之該第一區域及該第二區域的 介電層; t成覆蓋該介電層之第一含金屬層,其中該第一含金春 屬層覆蓋該半導體基板之第一區域; 形成一覆蓋該第一含金屬層及該介電層之第二含金屬 層其中4第二含金屬層與覆蓋該半導體基板之第二區域 的該介電層之—部分直接接觸; 幵/成t蓋該第二含金屬層之圖案化遮罩層以界定一第 一閘極堆疊及一第二閘極堆疊丨 使用。亥圖案化遮罩層來對該第二含金屬層進行乾式蝕 」乂形成忒第-閘極堆疊之一閘極電極;及 92528.doc
.jM 1342044 使用該圖案化遮罩層來對該第一含金屬層之至少一第一 部分進行濕式I虫刻,以形成該第二閉極堆疊<一閉極電極。 【實施方式】 在-實施财,-I導體t置具有一卩通冑閘極堆疊及一 N通道閉極堆豐,其中該p通道閘極堆疊包含第—金屬類型 及位於該第-金屬類型之上的第二金屬類型,該N通道閘極 堆疊包括直接與一閘極介電接觸之第二金屬類型。藉由一 乾式蝕刻程序來蝕刻N通道閘極堆疊及一部分p通道閘極堆 疊。藉由一濕式蝕刻來完成P通道閘極堆疊之蝕刻。濕式蝕 刻對閘極介電及對第二金屬類型非常具有選擇性,使得N 通道電晶體不會受到完成P通道閉極堆疊之蝕刻的不利影 響。此可藉由參考圖示及以下描繪來更好地理解。 圖1展示了 -半導體裝置10 ’其包括一絕緣物上矽⑽” 基板12、一直接位於S0I基板12之頂面上的閘極介電Μ、一 氮化鈦層16、一氮化矽鈕層18、一多晶矽層2〇、富矽之氮 化矽的一抗反射塗層(ARC)22及圖案化之光阻部分以及 26。SOI基板12具有一矽基板28、一絕緣物層3〇、_n區域 34、一隔離區域32及一 p區域36。絕緣物層3〇較佳為二氧化 矽但亦可為另一絕緣材料。另外,可使塊矽基板,而非使 用soi基板層16覆蓋於N區域34上而非覆蓋於區域刊上, 且該層16直接與閘極介電14接觸。層18覆蓋於s〇i基板u 上,該SOI基板12包括層16及p區域36。層2〇覆蓋於層18上。 層22覆蓋於層20上《圖案化之光阻部分24覆蓋於n區域μ 之其中將形成P通道閘極堆疊的一部分上。類似地,圖案化 92528.doc -8- 1342044 ^光阻部分26覆蓋於其中將形成N通道閘極堆#的?區域% 上0 在此點上(at this P〇int)來執行一乾式㈣,其不會渗透 過問極介電14。層16及18之厚度較佳為50埃,但亦可低至 3〇埃或高於5〇埃。圖案化之光阻部分2⑽的寬度較佳為 5⑻埃,約為金屬層16及18之厚度的十倍,該圖案化之光阻 部分24及26的寬度可用於確定電晶體開極的長度。 域32之寬度與圖案化之光阻部分24及26的寬度近似相等。 視正使用之特殊技術而定,此等尺寸可要麽更小或要麼更 大。舉例而言,在生産中,微影技術挑戰可將圖案化之光 阻部分24及26的尺寸限制於僅為5〇〇埃或甚至丨〇〇〇埃,但是 層16及18之厚度仍可保持5〇埃。親層22之厚度較佳為_ 埃。 圖2展示了乾式蝕刻之結果:將閘極堆疊37及39分別放置 於N區域34及P區域36之上。使P區域36上之閘極介電14曝 光’除了被閘極堆疊39所覆蓋的部分之外。使位於n區域34 上之層16曝光’除了被閘極堆疊37所覆蓋的部分之外。圖 案化光阻部分24及26可能已經受到侵蝕。閘極堆疊37及39 兩者皆具有ARC 22、層20及層18部分。 較佳以三個触刻步驟來達成此能形成圖2之閘極堆疊3 7 及39的乾式餘刻。第一步係針對氮化石夕arc層22且較佳為 一基於鹵素之反應性離子蝕刻(RIE)隨後為藉由基於_素 之化學中的RIE來對多晶矽層20進行蝕刻。緊隨層20之蝕刻 的為對層18進行蝕刻,其由基於鹵素之RIE來執行。此等為 92528.doc 1342044 用於此等類型之層的習知钱刻。氮化鈦之典型钱刻係藉由 亦基於鹵素之RIE來達成的。達成此的困難在於氮化鈦對閘 極介電不具有充分的選擇性,在此情況下,較佳使用氮氧 化矽。氮氮氧化矽比氧化矽具有更高的介電常數,且對基 於鹵素之RIE蝕刻更具有抵抗性,但是並非具有足夠的抵抗 性,從而使得不能在對具有所需厚度之氮化鈦進行此類蝕 刻期間來避免氮氧化矽被該基於鹵素之R丨E蝕刻所滲透。基 於鹵素之RIE蝕刻各略有不同,且其在實驗中最終基於該等 經爻蝕刻之貫際層來決定。對此等材料所進行之此等蝕刻 係習知的且傳統上已加以確定。若將氧化矽用作閘極介 電,則會呈現相同的蝕刻問題且事實上將變得更糟糕,因 為對含金屬之材料(諸如彼等用於層16及18)所進行的典型 乾式蝕刻對氧化矽的選擇性比對氮氧化矽更差。 出於處理的目的,氮化鈦之厚度需要薄些,但是亦需要 具有足夠的厚度以確定能控制隨後形成之電晶體的通道的 工作函數。閘極介電較佳具有一大於3 9之介電常數。N通 道電晶體閘極與P通道電晶體閘極的最佳工作函數通常被 δ忍為處於矽能帶邊緣,意即分別為4_丨電子伏(eV)及 5.2 eV。對於塊矽及對於部分耗盡之s〇I而言,此係正確 的。實際上,此可能難以達成,但是對於部分耗盡之s〇i 基板或塊半導體基板而言,較佳地,N通道金屬閘極應具有 一少於或等於4.4 eV的工作函數且p通道金屬應具有一大於 4.6 eV的工作函數,此為杳前情形。氮化鈦層16具有4.65 eV 之工作函數,且氮化矽钽層18具有4 4eV之工作函數。一較 92528.doc 1342044 少之工作函數差異可滿足完全耗盡之s〇I基板。 因此使用濕式姓刻來對層1 6進行钱刻,而非使用習知 之RIE蝕刻。該濕式蝕刻較佳為一種由硫酸及過氧化氫與水 形成的溶液所組成的piranha c|ean。其它濕式蝕刻亦具有相 同的效果。piranha Clean尤其有利,因為其通常可自製造工 廠獲得且因此吾人已熟知如何來施用並控制該…⑽以 clean。此piranha Clean對氮化矽钽與氮氧化矽兩者以及二 氧化矽皆非常具有選擇性。因此,在將曝露於piranhac丨ean 之層16移除時,對層18及閘極介電14産生最小的蝕刻。若 閘極介電14為氧化矽,則此亦為正確的。 圖3展示了施用piranha c丨ean之結果。此展示了閘極堆疊 37的完成及對閘極堆疊39所産生的最小變化。在此 clean期間’來移除圖案化之光阻部分24及26。以濕式清洗 之方法來移除一材料通常係各向同性的,使得其可橫向地 以及縱向地來蝕刻。因此,存在層丨6之底切,使得可自層 18之一部分(其為閘極堆疊37之一部分)的下面來移除層w 之一部分。此底切通常不比正經受蝕刻之層的厚度大。在 此情況下,層16之較佳厚度為50埃,使得在層16與18之間 的介面所進行的底切能在5〇埃左右,此約為閘極長度的 1 0 /〇’而對閘極介電丨4所進行的底切則較小。如圖3所示, 閘極堆疊37及39適於以習知之方式來完成電晶體之形成。 圖4展示了使用閘極堆疊37及39所完成之電晶體38及 4〇 °自問極堆疊37與39兩者來移除arc層22,且電晶體38 及40能夠以習知之方式來製得。電晶體38係一 p通道電晶 92528.doc 1342044 體’其具有源極/沒極42及44、側壁間隔片46、襯塾48及石夕 化物區域50、52及54。矽化物區域50及52分別形成於源極/ 沒極42及44上,並分別與其接觸。類似地,矽化物區域54 形成於層20之一部分上並與其接觸,其中該層2〇之一部分 為如圖3所示之閘極堆疊37的一部分。電晶體40係一 N通道 電晶體’其具有源極/沒極區域56及58、側壁間隔片60、襯 墊62及矽化物區域64及66。矽化物區域64及66分別位於源 極/汲極5 6及5 8之上並分別與其接觸。 在上述說明書中’已藉由特定實施例來描述了本發明。 然而,知·熟習此項技術者將瞭解,可作出各種修改及變 化,而不背離申請專利範圍中所闡述之本發明的範疇。舉 例而言,圖1中所展示之裝置結構的一替代結構為使覆蓋導 體自身形成層次或係一種具有該等材料令之一種材料的分 級濃度的合金。同樣,兩個不同的層16及丨8可為不同於本 文所指定的材料。此等兩個層可實際上具有相同的材料但 疋具有此等材料之不同的比率,以達成所需之工作函數差 異。另外,可首先沈積層18,使得層16位於p區域%區中之 層18上。結果將為N通道電晶體閘極堆疊將具有兩種金屬, 而非如圖2-4所示之具有兩個金屬層的p通道閘極堆疊。一 替代結構之另-實施例為:以一種具有較低薄層電阻的材 料(諸如鶴)來置換覆蓋之多晶石夕層。因此,將說明書及附圖 ⑽為係6兒明性的而非具有限制意義且意欲使所有此等修 改包含於本發明之範疇内。 已將關於特定實施例的利益、其它優點及問題的解決方 92528.doc -12- 2述如上。然而,並非將該等利益、㈣、問題的解決 =及任何可導致任何利益、優點,或解決方案會出現或 支仔更加明顯的元件看作是任何或所有巾請專利範圍之一 關鍵性的、需要的,或必要的特徵或元件。如本文所用, 包括或其任何其它的變體意欲涵蓋一非專用之包涵 勿,使得一程序、方法、物件,或包括一列元件之設備不 包含彼等元件而且可包含未明顯列出或為此程序、方 法、物件或裝置所固有之其它元件。
【圖式簡單說明】 藉由實例來㈣本發明,且本發明並非受到隨附圖示的 限制,其令相同的參考數字指示相同的元件,且其中: 广-4為一根據本發明之第-實施例之處於連續處理階 段的半導體裝置之截面。 熟習此項技術者將瞭解,為簡單及清楚起見,對圖中^ 儿件進行了說明且已並無必要來按比例製圖。舉例而t 【主要元件符號說明】 可相對於其它元件來放大圖中之—些元件的尺寸,以幫马 改進對本發明之實施例的理解。 10 半導體裝置 12 基板 14 閘極介電 > 18 , 20 , 22 層 24,26 光阻部分 28 矽基板 92528.doc •13· 1342044 30 絕緣物層 32 隔離區域 34 N區域 36 P區域 37, 39 閘極堆疊 38 > 40 通道 42, 44 汲極 46, 60 側壁間隔片 48, 62 襯塾 50, 52 , 54 , 64 , 66 矽化物區域 56, 58 汲·極區域 92528.doc -14-
Claims (1)
1342044 第093110018號專利申請案行年口修(更)正替換 中文申請專利範圍替換本(99 ^Τ\2 η) 十、申請專利範圍: 1. 一種用於形成—個雙金屬閘極結搆之程序,其包括: 提供一具有一第一區域及—第二區域之半導體基板, 其中該第-區域具有一第一導電類型且該第二區域具有 一第二導電類型,其不同於該第一導電類型; 形成一覆蓋該半導體基板之該第一區域及該第二區域 的介電層; 形成一覆盘該介電層之第—含金屬層,其中該第一含 金屬層覆蓋該半導體基板之第—區域; 形成一覆蓋該第-含金屬層及該介電層之第二含金屬 層,其中該第二含金屬層與覆蓋該半導體基板之第二區 域的該介電層之一部分直接接觸; 形成一覆蓋該第二含金屬層之圖案化遮罩層以界定— 第一閘極堆疊及一第二閘極堆疊; 使用§亥圖案化遮罩層央斜兮楚 π旱層术對6玄第—含金屬層進行乾式蝕 刻以形成該第一閘極堆疊之一 .. 罨極並在該第一令 二屬:上界定該第二含金屬層之一第_部分之側壁,立 二含金屬層之該第-部分係該第二問極堆疊之: 上部分;及 且〈 使用·»玄第一含金屬層之該第一^^八# & 楚一口戸刀作為—遮罩來對該 3 ·屬屬之至少-部分進行濕式蝕刻,以在該第Λ 部分下形成該第二閑極堆疊之—問極電極。冬 2.如請求項】之程序,其中第一及第二含金屬層令之 有-至少為4.6電子伏(eV)的工作函數,且第一及心 9252S-99l20S.doc ----------- 咖修⑻正替換頁 ---- 金屬層中之另—-- 3· 4. 個具有一至多為4.4 eV的工作 如請求項1之轻疼,甘丄 數 之程序其中第一及第二含金屬層中之—加^ 括氮化鈦(ΉΝ),且筮 匕 )且苐一及第二含金屬層申之另 氣化石夕纽(TaSiN)。 $個包括 如請求項1之程序,苴 ..^ '、卞第一及第二含金屬層之每一個具 至〉、為30埃的厚度。 5. 6· 如請求項1之程序, 如請求項1之程序, 包括—合金。 其中該第二含金屬層包括—合金。 其t第一及第二含金屬層中之每一個 7. 如請求们之程序,其進一步包括: 覆蓋該第二含金屬層之切層,其中該圖案化 遮罩層覆蓋該含石夕層;及 使用該圖案化遮罩層來對該含石夕層進行乾式敍刻。 8. 如請求項7之程序,其進一步包括: 形成1蓋該含碎層之抗反射塗層(ARC),其 化遮翠層覆蓋該ARC層;及 ^ 使用該圖案化遮罩層來對該ARC層進行乾式姓刻。 9.如請求項8之程序,其進一步包括: ^半導體基板之第—及帛二區域t來形成摻雜區 域:其鄰近於第一及第二閘極堆疊,且形成鄰近於第一 及第二閉極堆疊的側壁間隔片,從而形成一第一 及一第二電晶體。 曰 92528-99I208.doc
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