Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/18—Timing circuits for raster scan displays
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0404—Matrix technologies
  • G09G2300/0408—Integration of the drivers onto the display substrate
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

• the present invention relates to a logic circuit, a timing generation circuit, a display device, and a portable terminal, and particularly to a transistor having a large variation in characteristics on an insulating substrate.
• the present invention relates to a logic circuit configured using the same, a timing generation circuit using the logic circuit, a display device using the timing generation circuit as one of peripheral driving circuits, and a mobile terminal equipped with the display device as a screen display unit.
• FIG. 7 shows a conventional example of a timing generation circuit which is a kind of logic circuit.
• the timing generation circuit according to this conventional example is composed of a level shift circuit 101 and two flip-flops cascade-connected to the output thereof in this order.
• a T-type flip-flop hereinafter referred to as “d”) 1 0 2 and 10 3.
• the level shift circuit 101 performs a level shift (level conversion) of the externally supplied low-voltage amplitude master clock MCK to a high-voltage amplitude master clock 1 smck.
• the master clock 1 smck is supplied to a circuit operating based on the master clock 1 smck via the buffer 104.
• the TFF 102 generates the dot clock D CK by dividing the master clock 1 smck.
• This dot clock DCK is a buffer for circuits that operate based on the dock clock DCK.
• Is supplied via The TFF103 generates a horizontal clock HCK by further dividing the dot clock DCK.
• This horizontal clock HCK is supplied to a circuit that operates based on the horizontal clock HCK.
• TFF 102 and 103 are reset by a reset pulse externally provided, for example, at a cycle of 1 H (H is a horizontal period).
• the wiring for transmitting the reset pulse to TFT 102, 103 has the wiring capacity, the input capacity of the transistor, and the cross capacity with other wiring. For this reason, a configuration is generally adopted in which the driving capability for the load capacity is increased by using a buffer 106 capable of driving the load capacity.
• the timing generation circuit having the above configuration when each circuit portion is formed of a transistor having a large variation in element characteristics, the timing difference between the input clock pulse of TFF 102 and the reset pulse of 103 is not affected. More likely to occur. Then, if the timing deviation becomes large, a malfunction occurs, and there is a problem that an operation margin for a variation in element characteristics is reduced.
• TFFs 102 and 103 repeat the operation of inverting the state in synchronization with the rising edge of the input clock pulse, so that the period of the input clock pulse is 2 Generates twice the output pulse. Also, when a low-level reset pulse is given, the output pulse goes low by being reset at the falling timing, and the first input clock pulse after the transition of the reset pulse to high level. The output pulse transitions to the high level at the rising timing, and thereafter remains the same as the input clock pulse until the next reset pulse is applied. The output pulse is continuously generated.
• the relative timing relationship between the incoming pulse and the reset pulse is determined by the circuits that generate these pulses, namely the level shift circuit 101, TFF 102, 103 and buffer 103. It is generated from the difference of the delay amount of 7.
• these circuits are formed of thin film transistors (Thin Film Transistoi TFT) having a large variation in element characteristics and a rough process rule (for example, 3.5 ⁇ ), the delay amount is large and a difference tends to occur.
• the present invention has been made in view of the above problems, and has as its object to provide a large operation margin even when a transistor having a large characteristic variation and a rough process rule is used.
• An object of the present invention is to provide a logic circuit capable of performing the above, a timing generation circuit using the same, a display device using the same as one of peripheral driving circuits, and a mobile terminal equipped with the same as a display output unit. Disclosure of the invention
• the flip-flop circuit includes a plurality of flip-flops formed on an insulating substrate and generating a plurality of pulse signals having different frequencies in synchronization with a clock signal input from outside the substrate; With flip-flops It is formed on the same substrate and has a reset circuit that divides a plurality of flip-flops into at least two systems and resets them separately at different timings.
• As the logic circuit there is a timing generation circuit that generates a plurality of timing signals having different frequencies in synchronization with a master clock input from outside the substrate.
• This timing generation circuit is used as a timing generation circuit in a display device mounted on the same transparent insulating substrate as the timing generation circuit display unit that generates a plurality of timing signals having different frequencies required for driving the display unit.
• Can be A display device using this timing generation circuit is mounted as a screen display unit on a portable terminal represented by a PDA (Personal Digital Assistant) or a portable telephone.
• PDA Personal Digital Assistant
• a timing generation circuit using the same, a display device using the same as one of peripheral driving circuits, or a mobile terminal equipped with the same as a screen display unit at least two systems are provided.
• flip-flops are reset separately at different timings
• flip-flops that need to be reset at an earlier timing and flip-flops that need to be reset at a later timing The reset operation can be performed separately.
• the optimal reset timing can be set for each flip-flop, so that the device characteristics vary widely and the operating margin can be increased even when each circuit is formed using transistors with rough process rules. Becomes possible.
• FIG. 1 is a circuit diagram showing a configuration example of a timing generation circuit according to one embodiment of the present invention.
• FIG. 2 is used to explain the circuit operation of the timing generation circuit according to the present embodiment.
• FIG. 2 is used to explain the circuit operation of the timing generation circuit according to the present embodiment.
• FIG. 3 is a timing chart showing an enlarged main part of FIG.
• FIG. 4 is a block diagram showing a configuration example of the liquid crystal display device according to the present invention.
• FIG. 5 is a circuit diagram illustrating an example of the configuration of a pixel.
• FIG. 6 is an external view schematically showing the configuration of the PDA according to the present invention.
• FIG. 7 is a circuit diagram showing an example of a configuration of a timing generation circuit according to a conventional example.
• FIG. 1 is a block diagram illustrating a configuration example of a logic circuit, for example, a timing generation circuit according to an embodiment of the present invention.
• the timing generation circuit according to the present embodiment includes a level shift circuit 11, for example, two flip-flops (here, TFF) 12 and 13, a level shift circuit 14 and a pulse
• TFF flip-flops
• the transistor has a generation circuit 15, is formed of a transistor having a large variation in element characteristics on an insulating substrate such as a glass substrate, and has a rough process rule, for example, a TFT.
• the level shift circuit 11 converts a low-voltage master clock MCK (for example, 0 V to 3.3 V) input from the outside into a high-voltage amplitude (for example, 0 V to 6.5 V) master clock lsmck. Perform level shift (level conversion).
• the master clock 1 smck is supplied to the TFF 12 and the pulse generation circuit 15, and is also supplied to a circuit operating based on the master clock 1 smck via the buffer 16.
• TFF 1 2 and 1 3 are cascaded to the output of the level shift circuit 11 in order. It is connected.
• the TFF 12 generates the dot clock DCK by dividing the master clock 1 smck.
• the dot clock DCK is supplied to a circuit operating based on the dot clock DCK via a buffer 17.
• TFF 13 generates the horizontal clock HCK by further dividing the dot clock D CK.
• the horizontal port HCK is supplied to a circuit that operates based on the horizontal port HCK.
• the dot clock D CK and the horizontal clock HCK are generated in order to provide flexibility in the timing of the external input signal, that is, in order to provide the input timing with a certain width.
• the reset operation of TFF 12 and 13 needs to be performed once in the cycle of the reference signal from the outside, in this example, the cycle of the horizontal sync signal Hsync, that is, once in one horizontal period.
• the present invention is characterized by a specific configuration of a reset circuit for resetting the TFFs 12 and 13. The configuration will be described below.
• the level shift circuit 14 level shifts the externally input horizontal sync signal H sync with a low voltage amplitude (0 V to 3.3 V) to a high voltage amplitude (0 V to 6.5 V) to perform panoramic operation. This is supplied to the generation circuit 15.
• the pulse generation circuit 15 detects an edge portion of the horizontal sync signal Hsync after the level shift, generates a horizontal sync pulse hd at the edge portion based on the master clock 1 smck, and further generates a plurality of reset pulses and a reset pulse. In the example, two reset pulses drst and hrst corresponding to two TFFs 12 and 13 are generated.
• the reset pulse drst is used to reset TFF12.
• the reset pulse h r st is used to reset TFF 13.
• Figure 2 shows the master clock MCK and the horizontal synchronization signal Hsync input from the outside, and the master generated in this timing generation circuit.
• the reset pulse drst, the horizontal synchronization pulse hd, and the reset pulse hrst generated by the pulse generation circuit 15 have their falling edges during the low level period of the horizontal synchronization signal Hsync. It can be seen that the master is generated based on one clock per smck. .
• the wiring for the reset pulses d rst and h r st has the wiring capacitance, the input capacitance of the transistor, and the cross capacitance with other wirings.
• a buffer with sufficient driving capacity to drive the load capacity is required.
• delay occurs in the reset pulses d rst and h r st.
• the master clock 1 smck, the dot clock DCK, and the horizontal clock HCK also have a delay because they pass through the level shift circuit 11 and the TFFs 12 and 13.
• the master clock 1 smck generates a delay amount Da with respect to the master clock MCK by passing through the level / shift circuit 11
• the delay amount Db occurs in the dot clock DCK by passing through the TFF 12
• the delay amount of the dot clock DCK with respect to the master clock MCK becomes Da + Db
• the TFF 1 When a delay amount Dc is generated in the horizontal clock HCK by passing through 3, the delay amount of the horizontal clock HCK with respect to the master clock MCK becomes Da + Db + Dc.
• the TFF 12 for dividing the master clock lsmck is reset.
• the delay amount of the reset pulse drst needs to be as small as possible.
• the reset pulse drst is different from the reset pulse hrst. Then, the pattern arrangement of the TFF 12 with respect to the pulse generation circuit 15 is set close. As a result, the load capacitance of the reset pulse drst wiring can be reduced, and the driving capability of the buffer for driving the load capacitance can be reduced.
• the delay amount can be kept small.
• the reset noise drst ′ is generated at the falling timing of one master clock 1 smck during the low-level period of the horizontal synchronization signal Hsync.
• the delay amount Da in the pulse generation circuit 15 is generated in the reset pulse drst with respect to the fall of the master clock 1 smck.
• the reset pulse r st is generated in a timing relationship that is delayed from the reset signal d r st by about half a clock of the master clock 1 smck.
• the reset pulse hrst is different from the reset pulse drst not only in the timing relationship between the master clock 1 smck and the reset pulseless drst, but also in the timing relationship between the dot clock DCK and the reset pulse hrst. Therefore, if necessary, the amount of delay can be adjusted by adding a buffer.
• TFF 12 changes its state in response to the falling timing of master clock 1 smck. Generate dock clock DCK. Similarly, TFF 13 generates the horizontal clock HCK by inverting the state in response to the falling timing of the dock clock DCK.
• multiple timing signals that are formed on an insulating substrate and have different frequencies in synchronization with the master clock MCK input from outside the substrate.
• the reset can be performed at an early timing.
• the reset operation can be performed separately for the necessary TFF 12 and the TFF 13 that needs to be reset at a later timing.
• the optimum reset timing can be set for each of the TFFs 12 and 13, so that each circuit was formed using transistors with large variations in element characteristics and rough process rules, for example, TFTs. Even in such a case, it is possible to increase the operation margin.
• the timing generation circuit has been described as an example of the logic circuit.
• the present invention is not limited to application to the timing generation circuit, and a plurality of cascaded flip-flops may be used.
• the present invention can be applied to all logic circuits that generate a plurality of pulse signals having different frequencies in synchronization with a single close-up signal using a tap.
• an example of a circuit configuration in which flip-flops are cascaded in two stages is given as an example, but the frequency is different by cascading flip-flops in three or more stages.
• the same can be applied to the circuit configuration that generates the above pulse signal.In this case, the flip-flops of three or more stages are divided into at least two systems and separately at different timings. Just reset it.
• the operation speed can be increased by setting the reset pulse to a pulse having a relatively small delay amount variation from the input clock.
• the timing generation circuit is, for example, a drive circuit integrated type in which a peripheral drive circuit is integrally formed on the same transparent insulating substrate as a display unit in which pixels are arranged in a matrix.
• the display device is suitable for use as a timing generator for generating various timing signals necessary for driving the display unit based on a master clock MCK input from outside the substrate.
• FIG. 4 is a block diagram illustrating a configuration example of a display device according to the present invention, for example, a liquid crystal display device.
• a display section (pixel section) 32 in which pixels are arranged in a matrix is formed on a transparent insulating substrate, for example, a glass substrate 31.
• the glass substrate 31 is opposed to another glass substrate with a predetermined gap, and a liquid crystal material is sealed between the two substrates to form a display panel (LCD panel).
• LCD panel display panel
• FIG. 5 shows an example of the configuration of each pixel in the display unit 32.
• Each of the pixels 50 arranged in a matrix has a TFT (Thin Film Transistor) 51, which is a pixel transistor, and a pixel electrode connected to the drain electrode of the TFT 51.
• Oncoming electricity formed by It means the liquid crystal capacity generated between the poles. .
• TFT 51 has a gate electrode connected to a gate line (scanning line) 54 and a source electrode connected to a data line (signal line) 55.
• the liquid crystal cell 52 has a common electrode connected to the VCOM line 56 in common for each pixel. Then, a common voltage VCOM (VC OM potential) is commonly applied to the opposite electrode of the liquid crystal cell 52 via the VC OM line 56 for each pixel.
• the storage capacitor 53 has the other electrode (terminal on the counter electrode side) connected to each pixel with respect to the CS line 57.
• the display signal written to each pixel performs the polarity inversion based on the VCOM potential.
• the VCOM inversion drive which inverts the polarity of the VCOM potential in 1H or 1F cycles, is used together with the IH inversion drive or 1F inversion drive, the polarity of the CS potential applied to the CS line 57 is also Inverts in synchronization with the VCOM potential.
• the liquid crystal display device according to the present embodiment is not limited to the VCOMM inversion drive. Referring again to FIG.
• an interface (IF) circuit 33 on the same glass substrate 31 as the display section 32, for example, on the left side of the display section 32, an interface (IF) circuit 33, a timing generator (TG) 34, and a reference voltage driver 35
• the horizontal driver 36 is located above the display 32
• the vertical driver 37 is located to the right of the display 32
• the CS driver 38 and the VCOM driver 39 are located below the display 32. It is installed.
• These peripheral drive circuits are fabricated using low-temperature polysilicon or CG (Continuous Grain: continuous grain silicon) together with the pixel transistors of the display section 32.
• a master clock MCK having a low voltage amplitude (for example, 3.3 V amplitude), a horizontal synchronization pulse Hsync, a vertical synchronization pulse Vsync and R (red) are applied to the glass substrate 31.
• Parallel input display data D ata is input from outside the board via flexible cable (board) 40, and level shift to high voltage amplitude (for example, 6.5 V) in interface circuit 33. (Level conversion).
• the master clock MCK, the horizontal synchronization pulse Hsync, and the vertical synchronization pulse Vsync, which have been shifted, are supplied to the timing generator 34.
• the timing generator 34 based on the master clock MCK, the horizontal synchronization pulse Hsync and the vertical synchronization pulse Vsync, generates a reference voltage driver 35, a horizontal driver 36, a vertical driver 37, a CS driver 38 and a VC. Generates various timing pulses required to drive the OM Dryno 39.
• the level-shifted display data D ata is supplied to the next-stage serial / parallel (S / P) conversion circuit 42.
• the serial-parallel conversion circuit 42 converts the display data D ata into two bits for each bit in synchronization with a dot clock DCK, which will be described later, provided from the timing generator 34. Reduce the frequency to 1 Z2.
• the display data whose frequency has been dropped by the serial-parallel conversion circuit 42 is stepped down to a low voltage amplitude of O V-3.3 V and supplied to the horizontal driver 36.
• the horizontal driver 36 includes, for example, a horizontal shift register 361, a data sampling latch circuit 362, and a DA (digital-to-analog) conversion circuit (DAC) 363.
• the horizontal shift register 36 1 starts the shift operation in response to the horizontal start pulse HST supplied from the timing generator 34, and is synchronized with the horizontal clock pulse HCK also supplied from the timing generator 34. Generates sampling pulses that are transferred sequentially during one horizontal period.
• the data sampling latch circuit 36 2 is a horizontal shift register 36 1
• the display data Data supplied from the interface circuit 33 through the serial-parallel conversion circuit 43 is sequentially sampled and latched in one horizontal period in synchronization with the sampling pulse generated in the step S1.
• the latched digital data for one line is further transferred to a line memory (not shown) during the horizontal blanking period. Then, the digital data for one line is converted into an analog display signal by the DA conversion circuit 363.
• the DA conversion circuit 36.3 selects, for example, a reference voltage corresponding to digital data from among reference voltages for the number of gradations provided from the reference voltage driver 35, and outputs the reference voltage as an analog display signal. It has the configuration of a selective DA conversion circuit.
• the analog display signal S ig for one line output from the DA conversion circuit 363 is connected to the data line 55-1 to 55-n which is wired corresponding to the number n of pixels in the horizontal direction of the display unit 32. Is output.
• the vertical driver 37 is constituted by a vertical shift register and a gate buffer.
• the vertical shift register starts the shift operation in response to the vertical start pulse VST supplied from the timing generator 34, and the vertical clock pulse VCK also supplied from the timing generator 34.
• a scanning pulse that is sequentially transferred during one vertical period is generated in synchronization with.
• the generated scan pulse is sequentially output to the gate lines 54-1 to 54-m arranged corresponding to the number m of pixels in the vertical direction of the display unit 32 through the gate buffer.
• each pixel of the display unit 32 is sequentially selected in units of rows (lines). . Then, for one pixel of the selected one line, the analog display signal Sig of one line output from the DA conversion circuit 363 passes through the data lines 55-1-55-n. Are written all at once. By repeating this line-by-line write operation, 1 Image display of the screen is performed.
• the CS driver 38 generates the CS potential described above, and applies the same to the other electrode of the storage capacitor 53 via the CS line 57 in FIG.
• the amplitude of the display signal is, for example, 0 to 3.3 V
• the CS potential is 0 V (ground level) for the low level and 3.3 V for the high level.
• the AC reversal is repeated as an interval.
• the V CAM driver 39 generates the above-described V CAM potential.
• the VCOM potential output from the VCOM driver 39 is once output to the outside of the glass substrate 31 via the flexible cable 40.
• the VCOM potential output outside the board passes through the VCOM adjustment circuit 41 and then is input again into the glass board 31 via the flexible cable 40, and the VCOM line 56 in FIG.
• the common electrode is provided to the counter electrode of the liquid crystal cell 52 via the pixel.
• an AC voltage having substantially the same amplitude as the CS potential is used as the VCOM potential.
• a signal is written from the data line 54 to the pixel electrode of the liquid crystal cell 52 through the TFT 51, a voltage drop occurs in the TFT 51 due to parasitic capacitance and the like.
• the VCOM adjustment circuit 41 takes charge of the DC shift of the VCOM potential.
• the VCOM adjustment circuit 41 includes a capacitor connected to the VCOM potential, a variable resistor VR connected between the output terminal of the capacitor C and the external power supply VCC, and an output terminal of the capacitor C and the ground. And adjusts the DC level of the VCOM potential applied to the opposing electrode of the liquid crystal cell 52, that is, applies a DC offset to the VCOM potential.
• the same panel (glass-based On board 3 1), in addition to horizontal driver 36 and vertical driver 37, interface circuit 33, timing generator 34, reference voltage driver 35, CS driver 38 and VCOM driver 3
• peripheral drive circuits such as 9 as one
• a display panel integrated with all drive circuits can be configured, and there is no need to provide another board, IC, or transistor circuit outside, so the overall system is small. And cost reduction.
• the timing generation circuit according to the above-described embodiment is used as the timing generator 34 that generates various timing signals for driving the display unit 32. In the timing generation circuit shown in FIG.
• the level shift circuits 11 and 14 correspond to the interface circuit 33, and the TFFs 12 and 13, the pulse generation circuit 15 and the buffers 16 and 17 are timing generators. Corresponds to Nerator 34.
• the master clock 1 smck that has been level-shifted by the level shift circuit 11 1 is a circuit that operates based on the master clock 1 smck, specifically, the data sampling latch of the horizontal driver 36. Circuit 36 is provided.
• the dot clock D CK generated by the TFF 12 is supplied to a circuit that operates based on the dot clock D CK, specifically, a serial-parallel conversion circuit 42, and is generated by the TFF 13.
• the horizontal clock HCK is supplied to a circuit that operates on the basis of the horizontal clock HCK, specifically, a horizontal shift register 36 1 of a horizontal driver 36.
• the timing generation circuit has a large variation in element characteristics and uses a transistor with a rough process rule to connect each circuit to the insulating substrate. Since a large operating margin can be obtained even when formed on a liquid crystal display device, a peripheral driving circuit is formed integrally with the display section 31 on a transparent insulating substrate using a TFT, and thus has a large operating margin. Can be produced.
• the present invention is not limited to this application example.
• the present invention can be applied to all display devices having a level shift circuit mounted on the same substrate as the display unit, such as an EL display device using an electroluminescence (EL) element.
• the display device typified by the liquid crystal display device according to the application example described above is a screen display section of a small and lightweight portable terminal typified by a portable telephone or a PDA (Personal Digital Assistant). It is suitable for use as FIG. 6 is an external view schematically showing the configuration of a portable terminal, for example, a PDA according to the present invention.
• the PDA according to the present example has, for example, a foldable configuration in which a lid 62 is provided on the apparatus main body 61 so as to be freely opened and closed. On the upper surface of the device main body 61, an operation section 63 in which various keys such as a keyboard are arranged is arranged. On the other hand, a screen display section 64 is arranged on the lid 62. As the screen display unit 64, a liquid crystal display device in which the timing generation circuit according to the above-described embodiment is mounted as a timing generator on the same substrate as the display unit is used.
• a driving circuit integrated liquid crystal display device having a large operation margin can be configured, so that the liquid crystal display device is mounted as a screen display unit 64.
• the configuration of the entire PDA can be simplified, which can contribute to miniaturization and cost reduction.
• a plurality of flip-flops that are formed on an insulating substrate and generate a plurality of timing signals having different frequencies in synchronization with a clock signal input from outside the substrate are provided.
• these multiple flip-flops are separated into at least two series guns and reset separately at different timings, so that flip-flops that need to be reset at an early timing and The reset operation can be performed separately from the flip-flops that need to be reset at a slow timing, and the optimal reset timing can be set for each flip-flop. Large operating margin even if each circuit is formed using transistors with large variations in characteristics and rough process rules It is possible to take.

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