WO2003052512A1 - Appareil et procede permettant de corriger un motif de masque, procede de fabrication d'un masque et procede de fabrication d'un dispositif a semiconducteur - Google Patents
Appareil et procede permettant de corriger un motif de masque, procede de fabrication d'un masque et procede de fabrication d'un dispositif a semiconducteur Download PDFInfo
- Publication number
- WO2003052512A1 WO2003052512A1 PCT/JP2002/013284 JP0213284W WO03052512A1 WO 2003052512 A1 WO2003052512 A1 WO 2003052512A1 JP 0213284 W JP0213284 W JP 0213284W WO 03052512 A1 WO03052512 A1 WO 03052512A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pattern
- correction
- transfer
- allowable range
- mask
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/72—Repair or correction of mask defects
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
Definitions
- the present invention relates to, for example, a mask pattern correction apparatus and a mask pattern correction method for correcting a design pattern of a mask used in a lithography process of a semiconductor device or the like, a mask manufacturing method, and a semiconductor device manufacturing method.
- a photomask used in a semiconductor device manufacturing process has a structure in which a light-shielding film is formed on a glass substrate. In a lithography process of a semiconductor device, the photomask is projected and exposed on a wafer.
- the photomask used in one lithography process must convert the designed CAD data into data for the drawing device, and faithfully pattern it on the light-shielding film on the glass substrate.
- the finished dimensions of the pattern resolved on the aeha may be different, or the accuracy of the finished dimensions on both the short and long sides of a rectangular pattern There is a self-optical proximity effect that is significantly different. Also, as a result of the interference with the stepper light diffracted from other patterns, the mutual optical proximity effect that results in different finished dimensions on the wafer There is fruit.
- the mask dimension correction value that minimizes the pattern dimension error with respect to the design pattern is determined by the shape simulation or the exposure experiment result. I do.
- the data obtained by correcting the dimensions of the design pattern with the correction values are used in the mask EB drawing apparatus.
- the highest line width controllability is required when the gate electrode is processed.
- the gate pattern width of a transistor, or gate length in general, determines transistor characteristics such as gate threshold voltage and transconductance. Therefore, the line width variation of the gate length directly affects the characteristic variation, and thus the line width control of the gate electrode pattern is the most important in the MOS transistor formation.
- the present invention has been made in view of the above circumstances, and an object of ⁇ is to provide a mask pattern correction apparatus capable of optimizing a pattern portion functionally related to element characteristics while suppressing an increase in pattern correction time. And a mask pattern correction method.
- Another object of the present invention is to provide a method for manufacturing a mask having a pattern optimized as described above.
- a mask pattern correction apparatus of the present invention includes: a light proximity effect correction unit that performs light proximity effect correction on a design pattern; and a correction pattern obtained by the light proximity effect correction.
- Simulation means for obtaining, by simulation, a transfer pattern obtained when exposure is performed under predetermined transfer conditions; and transfer for measuring the size or position of a portion of the obtained transfer pattern that is functionally related to element characteristics.
- Pattern measuring means; and pattern deforming means for deforming the correction pattern so that the measured portion of the transfer pattern falls within the allowable range when the size or position is out of the allowable range.
- a mask pattern correction method of the present invention includes a first step of performing optical proximity effect correction on a design pattern, and a predetermined pattern obtained by the correction pattern obtained by the optical proximity effect correction.
- the mask manufacturing method of the present invention includes a first step of performing optical proximity effect correction on a design pattern, and exposing under a predetermined transfer condition by a correction pattern obtained by the optical proximity effect correction.
- a second step of obtaining a transfer pattern obtained by performing the simulation by simulation a third step of measuring a dimension or a position of a portion of the obtained transfer pattern that is functionally related to element characteristics,
- a sixth step of making a click is a third step of measuring a dimension or a position of a portion of the obtained transfer pattern that is functionally related to element characteristics.
- a method for manufacturing a semiconductor device includes a first step of performing optical proximity correction on a design pattern, and a predetermined transfer condition obtained by a correction pattern obtained by the optical proximity effect correction.
- FIG. 1 is a block diagram illustrating an example of a configuration of the mask pattern correction apparatus according to the first embodiment.
- FIG. 3 is a schematic diagram showing the transfer pattern of the gate electrode calculated by the simulation means of the mask pattern correction device according to the present embodiment with respect to the pattern after the optical proximity effect correction.
- FIG. 5A and FIG. 5B are diagrams for explaining a method of measuring the gate length at each measurement point of the gate electrode by the transfer pattern measurement means.
- FIG. 6A is a schematic diagram for explaining the process of determining whether or not the gate electrode pattern extracted from the design pattern overlaps with the transfer pattern, and FIG. 6B shows the minimum line width of the transfer pattern. It is a schematic diagram for explaining the measuring method.
- FIG. 7A is a schematic diagram for explaining a method for measuring the central portion of the transfer pattern
- FIG. 7B is a schematic diagram for explaining a method for measuring the maximum line width of the transfer pattern.
- FIG. 8 shows the distribution of deviation of the maximum line width of the transfer pattern from the design value.
- FIG. 9 shows a deviation distribution from the design value at the center of the transfer pattern.
- FIG. 10 shows the distribution of deviation of the minimum line width of the transfer pattern from the design value.
- FIG. 11 is a flowchart of a mask pattern correcting method, a mask manufacturing method, and a semiconductor device manufacturing method according to the present embodiment.
- FIG. 12 is a perspective view of an essential part showing an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment.
- FIG. 13 is a block diagram showing another example of the configuration of the mask pattern correction device. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram illustrating an example of a configuration of a mask pattern correction apparatus 1 according to the present embodiment.
- the mask pattern correction apparatus 1 includes an input unit 2, an optical proximity effect correction unit 3, a simulation unit 4, a transfer pattern measurement unit 5, a measured value distribution generation unit 6, a determination unit 7, It has a pattern deformation means 8 and an output unit 9.
- the input unit 2 receives a design pattern of an exposure mask pattern designed in a layout by CAD or the like, a transfer condition, important point information required for a circuit, and the like.
- the design pattern and the transfer condition input to the input unit 2 are output to the optical proximity effect correction unit 3.
- the design pattern and important point information input to the input unit 2 are output to the transfer pattern measuring means 5.
- the design pattern input to the input unit 2 may be output to the measured value distribution unit 6.
- the design pattern is, for example, as shown in FIG. 2A, a target for forming a mask pattern, for example, a pattern of an active region composed of a diffusion layer and the like in addition to a pattern 102 of a gate electrode to be subjected to pattern correction. It has 101.
- the optical proximity correction means 3 inputs the design pattern and the transfer condition from the input unit 2, performs the optical proximity correction, and simulates the corrected pattern after the optical proximity correction with the simulation means 4 and the pattern deformation means. Output to 8.
- the optical proximity correction means 3 determines, for example, a correction rule of the optical proximity effect corresponding to the line width and the interval of the design pattern for each transfer condition by a simulation 1 and an exposure experiment in advance, and obtains the determined design. By applying the correction rule to the line width and interval of the power line, a correction pattern after the optical proximity effect correction is obtained.
- an optical proximity effect correction means 3 there are means for correcting the shape of a design pattern or providing a dummy pattern near the design pattern.
- the optical proximity correction means 3 receives the design pattern after the optical proximity correction as shown in FIG. 2B according to the transfer condition.
- a correction pattern 103 for the gate electrode is generated.
- the simulation means 4 inputs the transfer condition together with the correction pattern after the optical proximity effect correction by the optical proximity effect correction means 3, and based on the transfer condition and the correction pattern after the optical proximity effect correction, writes the transfer pattern to a resist or the like.
- the transfer pattern is simulated, and the transfer pattern after the simulation is output to the transfer pattern measuring means 5. This transfer pattern is a transfer image obtained by simulation.
- simulation means 4 for example, a commercially available light intensity simulation that can simulate a transfer pattern by inputting a transfer condition and a correction pattern is used.
- the simulation means 4 inputs, for example, the correction pattern 103 of the gate electrode after the optical proximity effect correction shown in FIG. 2B, and based on the transfer conditions, as shown in FIG.
- the gate electrode transfer pattern 104 is generated.
- the transfer pattern measuring means 5 inputs the transfer pattern generated by the simulation means 4 and, in accordance with the important point information (information on the performance required for the element) input from the input section 2, The dimension or position of the pattern portion functionally related to the element characteristics in the transfer pattern is measured, and the measured value is output to the measured value distribution generating means 6.
- the dimensions here include the area of the pattern, the amount of distortion with respect to the design pattern, and the like.
- the transfer pattern measuring means 5 inputs the design pattern shown in FIG. 5A from the input section 2 and performs an AND operation on the pattern 102 of the gate electrode of the design pattern and the pattern 101 of the active region. A pattern 102 a that substantially functions as a gate as shown by the hatched portion of A is extracted. Further, the transfer pattern measuring means 5 receives the transfer pattern 104 of the gate electrode shown in FIG. 5B from the simulation means 4 and transfers the transfer pattern 104 of the gate electrode and the pattern 101 of the active region. Is AND-processed to extract a transfer pattern 104a of a portion substantially functioning as a gate, as indicated by the hatched portion in FIG. 5B.
- the design pattern includes a plurality of gate electrode patterns with gate lengths of 150 nm, 260 nm, and 330 nm
- the gate extracted from the design pattern The pattern 102 a of the portion functioning as an electrode is divided for each gate length.
- the gate length of the corresponding gate electrode transfer pattern 104 a was measured. Will be described.
- the pattern 102 a of the gate electrode and the gate electrode are extracted. It is checked whether or not the transfer pattern 104 a of the portion functioning as a part overlaps at least partially.
- the transfer pattern 104a of the gate electrode is recognized as a measurement target.
- a center line Z1 which is the center of the design pattern 102a in the gate length direction is set.
- the detection line X1 is located at a position away from the center line Z1 by a distance of, for example, 50 nm from the center line Z1 with respect to the transfer pattern 104a of the gate electrode.
- the detection line X1 is expanded outward from the inside in steps of 1 to 2 nm, and a line between the detection line X1 in a portion where the transfer pattern 104a of the gate electrode is first detected first.
- the width is determined as the minimum line width A of the transfer pattern 104a of the gate electrode.
- a case where the line width B at the center of the transfer pattern 104a of the gate electrode is measured will be described.
- a center line Z2 that is the center of the active region pattern 101 in the gate width direction is set for the gate electrode design pattern 102a. With reference to the center line Z 2, the line width of the transfer pattern 104 a of the gate electrode at the position of the center line Z 2 is measured.
- a center line Z1 which is the center of the gate electrode design pattern 102a in the gate length direction is set.
- a detection line X2 is set at a position away from the center line Z1 in the gate length direction, for example, by 100 nm, with respect to the transfer pattern 104a of the gate electrode.
- the detection line x2 is narrowed inward in steps of 1 to 2 nm from the inner side, and between the detection lines X2 in the portion where the transfer pattern 104a of the gate electrode is detected first.
- the line width is determined as the maximum line width C of the transfer pattern 104a of the gate electrode.
- the transfer pattern measuring means 5 calculates the gate length of the transfer pattern 104 a of each gate electrode at a position corresponding to the pattern 102 a of each gate electrode divided for each gate length from the design pattern. The measurement is performed on the entire chip.
- the measured value distribution generating means 6 receives the measured values of the entire chip input from the transfer pattern measuring means 5 and generates a distribution of deviation amounts of a plurality of measured values from the design value in the entire chip. For example, if the transfer pattern measuring means 5 measures the gate length of the transfer pattern of the gate electrode, enter one of the minimum line width A, the center line width B, and the maximum line width C of the gate length. Then, a distribution of the amount of deviation of the gate length of the entire chip from the design value is generated. The distribution is made separately for each gate length that should have the same dimensions in the design pattern.
- the transfer pattern measuring means 5 measures the minimum line width A of the transfer pattern of the gate electrode, a deviation distribution from the design value shown as an example in FIG. 10 is generated. Then, it is determined whether or not the deviation distribution of the measured values of the transfer pattern generated by the measured value distribution generating means 6 falls within an allowable range.
- the deviation from the design value is set to +5 nm or less as the allowable range Ra. Max. Then, it is determined whether or not all deviation distributions from the design values exist within the allowable range Ra.Max.
- the deviation from the design value of the line width B at the center of the transfer pattern from the design value is within a tolerance of 15 nm or more + 5 nm or less.
- C en is set, and it is determined whether or not all deviation distributions from the design values exist within the allowable range Ra. Cen.
- the judging means 7 If even a part of the measured value does not fall within the allowable range, the judging means 7 outputs information (position and shift amount) of the transfer pattern having the measured value out of the allowable range to the pattern deforming means 8. I do.
- the output unit 9 is instructed to output the input signal input from the pattern deformation unit 8. .
- the pattern deformation means 8 inputs the correction pattern after the optical proximity effect correction by the optical proximity effect correction means 3, and the information (position) of the transfer pattern having a dimension or position outside the permissible range input by the determination means 7. And the shift amount), the correction pattern after the optical proximity effect correction is deformed.
- the pattern deforming means 8 determines the corresponding position of the corrected pattern after the optical proximity correction input from the optical proximity effect correction means 3. Shift by one d.
- the pattern deforming means 8 performs a desired deformation on the corrected pattern after the optical proximity effect correction, and outputs the re-corrected pattern after the deformation to the simulation means 4 and outputs it to the output unit 9. I do.
- the output unit 9 outputs the re-correction pattern after deformation input by the pattern deformation unit 8 to the outside when the determination result that the measured value distribution is within the allowable range is input by the determination unit 7. Output.
- the transfer pattern measurement unit 5 measures the transfer pattern of the gate electrode (the minimum line width). A, center part B, and maximum line width C) can be changed.
- the above-mentioned important point information includes, for example, circuit speed, reduction of leak current, or circuit stability.
- the transfer pattern measuring unit 5 measures the maximum line width C of the transfer pattern of the gate electrode.
- the gate line width has a large effect on speed, and the thinner the gate line width, the faster the operation. If the gate electrode has a large line width, the speed of the circuit will be slowed down by that part, and the operation of the circuit will be slow. Therefore, it is necessary to remove such a large line width. Accordingly, for example, in the deviation distribution of the maximum line width C from the design value shown in FIG. 8, the determination means 7 sets the allowable range Ra. Max to +5 nm or less from the design value. Then, if there is a transfer pattern of the gate electrode of +5 nm or more in the deviation distribution, it is to be corrected.
- the reason for setting the allowable range in this way is that the minimum unit that can generate a transfer pattern by the simulation means is 2.5 nm at this stage, and if the design value is +5 nm or less, the speed This is because it is judged that there is no problem in the above. Also, if the allowable range is set narrower, the correction time increases due to an increase in the number of correction targets.
- the transfer pattern measuring means 5 measures the line width B at the center of the transfer pattern of the gate electrode.
- the allowable range R a .C en is set by ⁇ 5 nm or more and 5 nm or less from the design value by the determination means 7. Then, if there is a transfer pattern outside the permissible range in the deviation distribution, it is determined to be a correction target.
- the reason for setting the allowable range in this way is that if the difference from the design value is within ⁇ 5 nm from the design value, it is a level at which it is determined that there is no effect on the circuit characteristics. Further, if the allowable range is set to be narrower, the correction time increases due to an increase in the number of correction targets.
- the transfer line measuring unit 5 measures the minimum line width A of the transfer pattern of the gate electrode. If the gate line width is too narrow, a leakage current will occur, and the leakage current will affect the transistor. For this reason, it is necessary to remove a portion having a small line width that would cause a leakage current.
- the determination means 7 sets 15 nm or more from the design value as the allowable range Ra.Min where no leak current will occur. . Then, if there is a transfer pattern of a gate electrode of 15 nm or less which is out of the allowable range Ra.Min in the shift distribution, it is set as a correction target.
- the reason for setting the allowable range in this manner is that if the design value is equal to or more than 15 nm, it is determined that no leak current is generated. Also, if the allowable range is set to be narrower, the correction time increases due to an increase in the number of correction targets.
- a pattern correction method, a mask manufacturing method, and a semiconductor device manufacturing method using the pattern correction apparatus having the above configuration will be described with reference to the flowchart shown in FIG.
- a method of correcting a pattern of a wiring pattern having a portion to be a gate of a transistor, a method of manufacturing a mask having the wiring pattern, and a method of manufacturing a semiconductor device that forms a wiring pattern will be described.
- step ST 1 when a design pattern and a transfer condition having a gate electrode pattern 102 and an active area pattern 101 as shown in FIG. 2A are input to the input unit 2 (step ST 1), the design The pattern and the transfer condition are input to the optical proximity correction means 3, and the optical proximity correction means 3 performs the optical proximity correction on the design pattern based on the transfer condition.
- An electrode correction pattern 103 is generated (step ST 2).
- the simulation means 4 When the correction pattern 103 of the gate electrode as shown in FIG. 2B is input to the simulation means 4 together with the transfer condition, the simulation means 4 performs, for example, light intensity based on the transfer condition. Simulations are performed, for example, A transfer pattern 104 of the gate electrode after transfer to a resist or the like as shown in 3 is generated (step ST3).
- the transfer pattern 104 of the gate electrode after the simulation is generated by the simulation means 4
- the transfer pattern of the gate electrode is later transferred by the transfer pattern measuring means 5 according to the important point information input to the input section 2.
- the 104 measurement points (minimum line width A, center line width B, maximum line width C) will be changed (step ST4).
- the transfer pattern measuring means 5 measures the maximum line width C of the transfer pattern 104 of the gate electrode on the entire chip (step ST5-1) and measures The deviation distribution from the design value of the maximum line width C as shown in FIG. 8 is generated by the value distribution generating means 6 (step ST 6). For example, in the deviation distribution as shown in FIG. Determines whether the deviation distribution is within the allowable range Ra. Max (step ST7). If there is a transfer pattern of the gate electrode outside the allowable range Ra. Max in the deviation distribution shown in FIG. 8, the transfer pattern of the gate electrode outside the allowable range Ra. The information (the position and the amount of deviation from the design value) is output to the pattern deformation means 8.
- the pattern deformation means 8 based on the information of the transfer pattern of the gate electrode outside the allowable range R a.Max extracted by the determination means 7, the light proximity correction after optical proximity effect input from the optical proximity effect correction means 3 is performed. The corresponding portion of the correction pattern is shifted by the amount of deviation so as to approach the design value (step ST8).
- the re-correction pattern after the deformation by the pattern deformation means 8 is output to the simulation means 4 again, and the processing from step ST3 to step ST7 is repeated, and the maximum line width C of the transfer pattern of the gate electrode is obtained.
- the reason why the feedback needs to be applied in this way is that it is unlikely that the once-pattern-deformed portion is detected again as the maximum line width. However, as shown in FIG. This is because other parts of the pattern are detected next as the maximum line width, and the maximum line width may be out of the allowable range.
- the transfer pattern measuring means 5 measures the line width B of the center of the transfer pattern of the gate electrode on the entire chip (step ST). 5-2) The deviation distribution from the design value of the line width B at all the central portions as shown in FIG. 9 is generated by the measured value distribution generating means 6 (step ST6).
- the judging means 7 judges whether or not the shift distribution falls within the allowable range Ra.Cen (Step ST7). If a transfer pattern of the gate electrode outside the allowable range Ra.Cen exists in the shift distribution shown in FIG. 9, the transfer pattern of the gate electrode outside the allowable range Ra.Cen The information (the position and the amount of deviation from the design value) is output to the pattern deformation means 8.
- the pattern deformation means 8 based on the information of the transfer pattern of the gate electrode outside the allowable range R a .Cen extracted by the judgment means 7, the light proximity effect corrected light input from the light proximity effect correction means 3 is input.
- the corresponding portion of the correction pattern is shifted by the amount of deviation so as to approach the design value (step ST8).
- the re-correction pattern after the deformation by the pattern deformation means 8 is output to the simulation means 4 again, and the processing from step ST3 to step ST7 is repeated. Then, the deformation is performed until the line width B at the center of the transfer pattern of the gate electrode falls within the allowable range Ra.Cen.
- the judgment means 7 performs pattern deformation means 8.
- the output unit 9 is instructed to output the re-correction pattern input from the control unit, and the output unit 9 outputs the final correction pattern (step ST9).
- the determination means 7 determines whether or not the shift distribution is within the allowable range Ra.Min (step ST7). If there is a transfer pattern of the gate electrode that is outside the allowable range Ra.Min in the deviation distribution shown in (a), the information (position and position) of the transfer pattern of the gate electrode that is outside the allowable range Ra. The deviation from the design value) is output to the pattern deformation means 8.
- the pattern deformation means 8 based on the information of the transfer pattern of the gate electrode outside the allowable range Ra.Min extracted by the determination means 7, the light proximity correction after the light proximity correction input from the light proximity effect correction means 3 is performed. The corresponding portion of the correction pattern is shifted by the amount of deviation so as to approach the design value (step ST8).
- step ST 3 the processing from step ST 3 to step ST 7 is repeated to obtain the minimum line width A of the transfer pattern of the gate electrode. Is within the allowable range Ra.Min. Until the pattern is deformed.
- a mask having the final correction pattern is manufactured using an EB lithography apparatus (step ST10).
- the gate electrode 12 is formed on the active region 11 formed of the diffusion layer formed on the chip 10.
- the part (center, minimum line width, and maximum line width) corrected in accordance with the point of emphasis achieves particularly high line width controllability.
- the optical proximity effect correction unit 3 performs the optical proximity effect correction on the design pattern, and the pattern after the optical proximity effect correction is simulated by the simulation unit 4.
- a transfer pattern of the gate electrode is generated, and a measurement position in the transfer pattern of the gate electrode can be changed according to characteristics required for the circuit.
- the point required for the circuit is that the deviation from the design value at the measurement point of the gate electrode transfer pattern as described above is within an allowable range in accordance with the improvement of speed, stability, and reduction of leakage current. It is determined whether or not there is a gate electrode by repeating the feed pack until the measurement point falls within the allowable range. The optimum correction can be performed in accordance with the characteristics required for the circuit within the range in which the circuit functions.
- the correction time for pattern correction can be shortened, and cost reduction in mask fabrication can be achieved. It's not easy.
- the present invention is not limited to the above embodiments.
- the measurement value distribution generating means 6 has described an example of generating a distribution of a deviation amount of a measured value of a transfer pattern measured by the transfer pattern measuring means 5 from a design pattern.
- a distribution of measured values of the transfer pattern of the gate electrode itself may be generated.
- the determination means 7 may determine whether or not there is a transfer pattern that is out of the allowable range of the gate length.
- the transfer pattern measuring means 5 and the measured value distribution means 6 provide, for example, the line width of the transfer pattern of the gate electrode, the pattern area and the distribution of the transfer pattern distortion with respect to the design pattern, and the like. Any data related to the accuracy of the data may be generated as a distribution.
- the determination means 7 shown in FIG. 1 may be omitted, and the data output from the measured value distribution generating means 6 may be directly output to the pattern deformation means 8. If the judging means 7 is not provided, the shift amount data is output to the sequential pattern deforming means 8 without judging whether or not there is a transfer pattern having a measured value outside the allowable range, and only the amount of the shift amount is output.
- the correction pattern can be modified. Further, in the present embodiment, for example, an example in which a wiring pattern having a portion serving as a gate of a transistor or the like is corrected has been described. However, the present invention is not limited to this, and is similarly applied to various design patterns. It is possible. That is, other design Also, in the case of a semiconductor device, a portion functionally related to the element characteristics may be set in advance, and this portion may be set as a correction target.
- information (a shift amount from a position and a design value) of a transfer pattern of a gate electrode having a line width outside a permissible range is input from the determination means 7, and the pattern deformation
- the pattern is deformed by the shift amount, but there is no particular limitation on the shift amount as long as it can be kept within the allowable range.
- the shift amount can be set to match the gate length with the largest distribution within the allowable range.
- gate electrodes Even if it deviates from the design value, if it is within the allowable range, it may be preferable to form gate electrodes having the same gate length from the viewpoint of characteristic variations. is there.
- the deviation distribution from the design value of the transfer pattern of the gate electrode in the entire chip is generated by using the measured value distribution generating means 6, but the transfer pattern measuring means 5 individually generates the deviation distribution.
- the gate length of the measured transfer pattern of the gate electrode is determined by the determination means 7, and information (position and shift amount) of the transfer pattern of the gate electrode that is out of the allowable range is output to the pattern deformation means 8.
- a configuration may be adopted in which pattern correction is performed by applying feedback.
- the present embodiment as an important point, a reduction in circuit speed, stability, and leakage current is taken as an example, and the maximum line width of the transfer pattern of the gate electrode and the central The example of correcting the line width and the minimum line width has been described.However, the present invention is not limited to this, and if measurement points corresponding to other important points can be extracted, the number of measurement points may be increased. it can.
- the example of the measurement method by the transfer pattern measuring means 5 has been described.
- the maximum line width, the line width at the center, and the minimum line width of the transfer pattern of the gate electrode can be measured by other methods.
- the optical proximity correction means 3 Method and Simulation Method The simulation method using the simulation means 4 is not particularly limited, and various known methods can be adopted.
- the mask pattern correcting apparatus, the mask pattern correcting method, the mask manufacturing method, and the semiconductor device manufacturing method according to the present invention include, for example, a semiconductor device
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003553337A JP4165401B2 (ja) | 2001-12-19 | 2002-12-19 | マスクパターン補正装置およびマスクパターン補正方法、並びにマスク作製方法および半導体装置の製造方法 |
US10/468,211 US7139996B2 (en) | 2001-12-19 | 2002-12-19 | Mask pattern correction apparatus and mask pattern correction method and mask preparation method and method of production of a semiconductor device |
KR1020037010560A KR100932521B1 (ko) | 2001-12-19 | 2002-12-19 | 마스크패턴 보정장치 및 마스크패턴 보정방법과 마스크제작방법 및 반도체장치의 제조방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-386443 | 2001-12-19 | ||
JP2001386443 | 2001-12-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003052512A1 true WO2003052512A1 (fr) | 2003-06-26 |
Family
ID=19187940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/013284 WO2003052512A1 (fr) | 2001-12-19 | 2002-12-19 | Appareil et procede permettant de corriger un motif de masque, procede de fabrication d'un masque et procede de fabrication d'un dispositif a semiconducteur |
Country Status (6)
Country | Link |
---|---|
US (1) | US7139996B2 (ja) |
JP (1) | JP4165401B2 (ja) |
KR (1) | KR100932521B1 (ja) |
CN (1) | CN1235087C (ja) |
TW (1) | TWI237745B (ja) |
WO (1) | WO2003052512A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006053248A (ja) * | 2004-08-10 | 2006-02-23 | Toshiba Corp | 設計パターンデータ作成方法、マスクパターンデータ作成方法、マスク製造方法、半導体装置の方法およびプログラム |
JP2006303099A (ja) * | 2005-04-19 | 2006-11-02 | Ricoh Co Ltd | スタンダードセル構造 |
JP2007081326A (ja) * | 2005-09-16 | 2007-03-29 | Dainippon Screen Mfg Co Ltd | 配線形成システムおよびその方法 |
JP2008107847A (ja) * | 2003-08-28 | 2008-05-08 | Toshiba Corp | 工程の管理方法、半導体装置の製造方法、フォトマスクの製造方法およびプログラム |
KR101095062B1 (ko) * | 2008-06-26 | 2011-12-20 | 주식회사 하이닉스반도체 | 광학 근접 효과 보정의 검증 방법 |
TWI392957B (zh) * | 2007-02-09 | 2013-04-11 | Sony Corp | A light proximity effect correction method, a light proximity effect correction device, a light proximity effect correction program, a manufacturing method of a semiconductor device, a pattern design protocol determination method, and a light proximity effect correction condition calculation method |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3871949B2 (ja) * | 2002-03-27 | 2007-01-24 | 株式会社東芝 | マスクデータ作成装置及びマスクデータ作成方法 |
JP4383752B2 (ja) * | 2003-02-19 | 2009-12-16 | パナソニック株式会社 | マスクパタン生成方法およびマスクパタン生成装置 |
JPWO2004099874A1 (ja) * | 2003-04-16 | 2006-07-13 | 株式会社ニコン | パターン決定方法及びシステム、マスクの製造方法、結像性能調整方法、露光方法及び装置、並びにプログラム及び情報記録媒体 |
JP3828552B2 (ja) * | 2003-06-23 | 2006-10-04 | 株式会社東芝 | 寸法測定方法と寸法測定システム及び寸法測定プログラム |
JP4455469B2 (ja) * | 2004-09-14 | 2010-04-21 | エーエスエムエル マスクツールズ ビー.ブイ. | フルチップ製造信頼性チェックおよび補正を行うための方法 |
EP1863071B1 (en) * | 2005-03-25 | 2016-09-21 | Nikon Corporation | Shot shape measuring method, mask |
KR100822584B1 (ko) * | 2005-09-16 | 2008-04-15 | 다이니폰 스크린 세이조우 가부시키가이샤 | 배선 형성 시스템 및 그 방법 |
KR100655428B1 (ko) * | 2005-10-24 | 2006-12-08 | 삼성전자주식회사 | 광근접효과보정 시스템 및 방법 |
US8024675B1 (en) * | 2006-08-04 | 2011-09-20 | Tela Innovations, Inc. | Method and system for wafer topography-aware integrated circuit design analysis and optimization |
US7958495B2 (en) * | 2007-03-08 | 2011-06-07 | Systemware, Inc. | Program test system |
CN101329506B (zh) * | 2007-06-18 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | 光学近距修正方法、光掩模版制作方法及图形化方法 |
US8020120B2 (en) * | 2007-10-01 | 2011-09-13 | International Business Machines Corporation | Layout quality gauge for integrated circuit design |
KR101652830B1 (ko) * | 2010-07-02 | 2016-08-31 | 삼성전자주식회사 | 포토마스크 형성 방법, 이를 수행하는 프로그래밍된 명령을 저장하는 컴퓨터에서 판독 가능한 저장 매체 및 마스크 이미징 시스템 |
KR102185558B1 (ko) * | 2013-08-27 | 2020-12-02 | 삼성전자주식회사 | 광학적 근접 보정 방법 |
CN104570585B (zh) * | 2013-10-23 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | 光学邻近修正方法 |
CN104698761B (zh) * | 2013-12-05 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | 基于面积的opc模型校准方法 |
CN105159026B (zh) * | 2015-07-29 | 2019-10-25 | 上海华力微电子有限公司 | 栅极区域的光学临近修正验证方法 |
CN112859508A (zh) * | 2019-11-27 | 2021-05-28 | 台湾积体电路制造股份有限公司 | 集成电路制造方法 |
CN113325661A (zh) * | 2020-02-28 | 2021-08-31 | 中芯国际集成电路制造(上海)有限公司 | 光罩图形测量方法及其系统 |
CN113168086A (zh) * | 2021-03-19 | 2021-07-23 | 长江存储科技有限责任公司 | 用于设计光掩模的系统和方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0876348A (ja) * | 1994-09-07 | 1996-03-22 | Matsushita Electric Ind Co Ltd | マスクデータ検証装置、マスクデータ作成装置、マスクデータ検証方法、マスクデータ作成方法及び補助パターンマスク作成方法 |
US5879844A (en) * | 1995-12-22 | 1999-03-09 | Kabushiki Kaisha Toshiba | Optical proximity correction method |
JP2000047366A (ja) * | 1998-07-31 | 2000-02-18 | Hitachi Ltd | 半導体装置の製造方法 |
US6482662B1 (en) * | 1999-10-18 | 2002-11-19 | Samsung Electronics Co., Ltd. | Semiconductor device fabricating method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6470489B1 (en) * | 1997-09-17 | 2002-10-22 | Numerical Technologies, Inc. | Design rule checking system and method |
US7093229B2 (en) * | 1997-09-17 | 2006-08-15 | Synopsys, Inc. | System and method for providing defect printability analysis of photolithographic masks with job-based automation |
JP4226729B2 (ja) * | 1999-06-30 | 2009-02-18 | 株式会社東芝 | マスクパターンの補正方法 |
US6868175B1 (en) * | 1999-08-26 | 2005-03-15 | Nanogeometry Research | Pattern inspection apparatus, pattern inspection method, and recording medium |
JP2001350250A (ja) * | 2000-06-05 | 2001-12-21 | Mitsubishi Electric Corp | パターン歪み補正装置、パターン歪み補正方法、およびパターン歪み補正プログラムを記録した記録媒体 |
US6634018B2 (en) * | 2000-08-24 | 2003-10-14 | Texas Instruments Incorporated | Optical proximity correction |
-
2002
- 2002-12-11 TW TW091135831A patent/TWI237745B/zh not_active IP Right Cessation
- 2002-12-19 US US10/468,211 patent/US7139996B2/en not_active Expired - Fee Related
- 2002-12-19 JP JP2003553337A patent/JP4165401B2/ja not_active Expired - Fee Related
- 2002-12-19 CN CNB02806755XA patent/CN1235087C/zh not_active Expired - Fee Related
- 2002-12-19 WO PCT/JP2002/013284 patent/WO2003052512A1/ja active Application Filing
- 2002-12-19 KR KR1020037010560A patent/KR100932521B1/ko not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0876348A (ja) * | 1994-09-07 | 1996-03-22 | Matsushita Electric Ind Co Ltd | マスクデータ検証装置、マスクデータ作成装置、マスクデータ検証方法、マスクデータ作成方法及び補助パターンマスク作成方法 |
US5879844A (en) * | 1995-12-22 | 1999-03-09 | Kabushiki Kaisha Toshiba | Optical proximity correction method |
JP2000047366A (ja) * | 1998-07-31 | 2000-02-18 | Hitachi Ltd | 半導体装置の製造方法 |
US6482662B1 (en) * | 1999-10-18 | 2002-11-19 | Samsung Electronics Co., Ltd. | Semiconductor device fabricating method |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008107847A (ja) * | 2003-08-28 | 2008-05-08 | Toshiba Corp | 工程の管理方法、半導体装置の製造方法、フォトマスクの製造方法およびプログラム |
JP2006053248A (ja) * | 2004-08-10 | 2006-02-23 | Toshiba Corp | 設計パターンデータ作成方法、マスクパターンデータ作成方法、マスク製造方法、半導体装置の方法およびプログラム |
JP2006303099A (ja) * | 2005-04-19 | 2006-11-02 | Ricoh Co Ltd | スタンダードセル構造 |
JP2007081326A (ja) * | 2005-09-16 | 2007-03-29 | Dainippon Screen Mfg Co Ltd | 配線形成システムおよびその方法 |
TWI392957B (zh) * | 2007-02-09 | 2013-04-11 | Sony Corp | A light proximity effect correction method, a light proximity effect correction device, a light proximity effect correction program, a manufacturing method of a semiconductor device, a pattern design protocol determination method, and a light proximity effect correction condition calculation method |
KR101095062B1 (ko) * | 2008-06-26 | 2011-12-20 | 주식회사 하이닉스반도체 | 광학 근접 효과 보정의 검증 방법 |
Also Published As
Publication number | Publication date |
---|---|
US7139996B2 (en) | 2006-11-21 |
JP4165401B2 (ja) | 2008-10-15 |
TW200307187A (en) | 2003-12-01 |
KR100932521B1 (ko) | 2009-12-17 |
CN1498359A (zh) | 2004-05-19 |
JPWO2003052512A1 (ja) | 2005-04-28 |
CN1235087C (zh) | 2006-01-04 |
TWI237745B (en) | 2005-08-11 |
US20040073885A1 (en) | 2004-04-15 |
KR20040073960A (ko) | 2004-08-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4165401B2 (ja) | マスクパターン補正装置およびマスクパターン補正方法、並びにマスク作製方法および半導体装置の製造方法 | |
KR100750531B1 (ko) | 리소그래피 시뮬레이션용 마스크 배치 데이타를 산출하기 위한 방법 | |
US7480890B2 (en) | Method for correcting and configuring optical mask pattern | |
US7142941B2 (en) | Computer-implemented method and carrier medium configured to generate a set of process parameters and/or a list of potential causes of deviations for a lithography process | |
US20030177467A1 (en) | Opc mask manufacturing method, opc mask, and chip | |
JPH0934095A (ja) | マスクパターン補正方法とそれを用いたマスク、露光方法および半導体装置 | |
US7600213B2 (en) | Pattern data verification method, pattern data creation method, exposure mask manufacturing method, semiconductor device manufacturing method, and computer program product | |
TW200532398A (en) | Design pattern correction method, mask producing method , semiconductor device producing method, mask pattern producing method, design pattern correction system and recording media | |
US20150169820A1 (en) | Weak points auto-correction process for opc tape-out | |
JP2002328459A (ja) | ウエーハ転写検証方法 | |
EP1246010A2 (en) | Photomask manufacturing method, photomask manufactured by said manufacturing method, and semiconductor device method using said photomask | |
JP2000098584A (ja) | マスクパタ―ン補正方法及びマスクパタ―ン補正プログラムを記録した記録媒体 | |
JP3914085B2 (ja) | プロセスパラメータの作成方法、プロセスパラメータの作成システム及び半導体装置の製造方法 | |
JP2010016044A (ja) | 設計レイアウトデータ作成方法および半導体装置の製造方法 | |
JP2007004585A (ja) | マスクパタンデータの検証方法、マスクの製造方法、マスクパタンデータの検証プログラム | |
JP4643302B2 (ja) | マスクパターン作成方法、レイアウト作成方法、フォトマスクの製造方法、フォトマスク、及び半導体装置の製造方法 | |
JP4177722B2 (ja) | パターン補正方法、パターン補正システム、マスク製造方法、半導体装置製造方法、及びパターン補正プログラム | |
JP2000258892A (ja) | マスクパターン設計方法 | |
US7544447B2 (en) | Method of forming a mask pattern for a semiconductor device | |
JP2009042275A (ja) | プロセスモデル作成方法、プロセスモデル作成プログラム及びパターン補正方法 | |
KR20070053625A (ko) | 포토마스크의 판정 방법, 및 반도체 장치의 제조 방법 | |
KR100827474B1 (ko) | 반도체용 마스크의 패턴 배치를 위한 모델링 데이터 생성방법과 장치 | |
JP4580529B2 (ja) | 半導体回路の設計パタンデータ補正方法と、補正された設計パタンデータを用いたフォトマスク、該フォトマスクの検査方法およびフォトマスク検査用パタンデータ作製方法 | |
KR100662961B1 (ko) | 광근접보정 모델링 데이타 추출을 위한 테스트 패턴제작방법 | |
US8146022B2 (en) | Mask pattern data generation method, mask manufacturing method, semiconductor device manufacturing method, and pattern data generation program |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN JP KR US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020037010560 Country of ref document: KR Ref document number: 2003553337 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10468211 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 02806755X Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020037010560 Country of ref document: KR |