Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0008—Arrangements for reducing power consumption
  • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Definitions

• transistors have been made with ever ever smaller geometries. For example, photolithographic and etch techniques have improved to the point where transistors with a gate length of 0.25 microns ((m) may be made. Decreasing the size of transistors is generally perceived to be beneficial because this may allow more transistors to be made within the same amount of area on a semiconductor die.
• the distance between the current carrying electrodes may also be proportionately reduced. Consequently, the amount of semiconductor material between these terminals and beneath the gate of the transistor, often referred to as a channel or body region, may be reduced. As the length of the channel region of a transistor is reduced, the electric field of the drain terminal may have a greater effect upon the flow of current in the channel region. Thus, reductions in channel length, may make it more difficult to control the flow of current across the channel region between the source and drain terminals and lead to an increase in the amount of source-to-drain leakage (e.g., off-state current).
• source-to-drain leakage e.g., off-state current
• FIG. 1 is a schematic representation of two transistors and a circuit in accordance with an embodiment the present invention
• FIG. 2 is a schematic representation illustrating circuits that may be used in accordance with various embodiments of the present invention
• FIG. 3 is a schematic representation of voltage generators in accordance with various embodiments of the present invention.
• FIG. 4 is a schematic representation of a voltage generator in accordance with an alternative embodiment of the present invention.
• Embodiment 100 may comprise a portable device such as a mobile communication device (e.g., cell phone), a portable computer, or the like.
• a mobile communication device e.g., cell phone
• a portable computer e.g., a laptop computer
• the scope of the present invention is in no way limited to these applications.
• Embodiment 100 includes an integrated circuit 10 that may comprise, for example, a microprocessor, a digital signal processor, a microcontroller, a memory array, such as static random access memory (SRAM), or the like.
• Integrated circuit 10 may comprise transistors 20 and 30 fabricated in a substrate 15, such as silicon, although the scope of the present invention is not limited in this respect.
• Transistors 20 and 30 may include a gate electrode 23 and 33 that may be used to modulate a current flow across channel regions 24 and 34, respectively, while transistors 20 and 30 are in operation.
• channel region 24 may include the portion of substrate 15 where current flows between the current carrying electrodes 21-22 of transistor 20. Additionally, channel region 34 may comprise N-type well 35 where current flows between current carrying electrodes 31-32 of transistor 30. Generally stated, channel regions 24 and 34 are the portions of transistors 20 and 30 under gates 23 and 33 between current carrying electrodes 21-22 and 31-32, respectively. Channel regions 24 and 34 may also be referred to as body regions by those skilled in the art.
• transistor 30 may comprise a p-channel transistor formed in an N-well region 35 while transistor 20 may comprise a n-channel transistor formed in a p-type substrate 15.
• CMOS complementary metal-oxide semiconductor
• the scope of the present invention is not limited by the electrical characteristics of transistors 20 and 30 or by the type of material in which transistors 20 and 30 may be formed.
• substrate 15 may comprise a variety of materials such as epitaxial layers, field oxide regions, etc.
• transistors 20 and 30 may be fabricated with twin-wells, or a P-well in an N-type substrate.
• substrate 15 need not comprise silicon as other semiconductor materials may be used, such as semiconductor- on-insulator (SOI), etc.
• Transistors 20 and 30 illustrate one example of how embodiments of the present invention may be used to reduce the leakage current of integrated circuit 10 when all or some of the transistors of integrated circuit 10 are in a non-conducting mode (e.g., at least some of the transistors are in an inactive mode and do not have a substantial voltage potential driven onto their gate terminals). Two transistors are shown in FIG. 1 so as not to obscure the present invention. It should be understood that integrated circuit 10 may comprise any number of transistors or sub-circuits. In the following description, a circuit or sub-circuit generally refers to a plurality of transistors, for example two or more.
• a single transistor may be a circuit or sub-circuit.
• a circuit may refer to the voltage level or logic signal provided by a node of another circuit or bonding pad.
• Vsssup voltage potential 40 Veep voltage potential 41, and Vcc voltage potential 42 may be selectively applied to portions of transistors 20 and 30 to reduce the leakage across channel regions 24 and 34.
• voltage potentials 40-42 may be provided by pads that may be connected to power supplies that are external to integrated circuit 10. However, this is not intended as a limitation of the scope of the present invention as voltage potentials 40-42 may be provided from power supplies located within integrated circuit 10 (e.g. from charge pumps or voltage dividers). Furthermore, in other embodiments, voltage potentials 40-42 may represent the voltage potential provided by the nodes of another circuit (not shown) or from other portions of integrated circuit 10.
• a voltage potential (e.g., Vsssup 40) may be applied to channel region 24 that is lower in magnitude than a voltage potential (e.g., a Vss potential) on the source region 21 of transistor 20.
• a voltage potential e.g., a Vss potential
• a Vss Generator 60 may be used to provide the Vss voltage potential to source region 21 by raising the Vsssup voltage potential 40.
• a Vccsup generator 50 may be used to provide a voltage potential
• Vccsup e.g., Vccsup
• FIG. 2 illustrates two circuits that may be used either individually or in combination to provide Vccsup generator 50.
• a transistor 82 is used as Vccsup generator 50 to provide Veep voltage potential 41 as Vccsup.
• An enable signal, labeled E2 in FIG. 2 may be used to enable and control the operation of transistor 82 so that Vccsup generator 50 may selectively provide a voltage potential, labeled Vccsup.
• the voltage potential provided by Vccsup generator 50 may be substantially equal to the Veep voltage potential 41, although this is not intended a limitation of the scope of the present invention.
• Enable signal E2 may be activated when integrated circuit 10 has entered an inactive or stand-by mode.
• portions of integrated circuit 10 are in a stand-by mode (e.g., logic transistors 20 and 30)
• an n- channel transistor (not shown) may be used in place of transistor 82.
• Vccsup generator 50 may comprise a voltage reference circuit 65 connected to the gate of a transistor 81 (see FIG. 2).
• FIG. 3 is provided to demonstrate an example for implementing voltage reference circuit 65, although the scope of the present invention is not limited to this particular implementation.
• transistors 91, 94, and 99 may operate as a reference resistor element connected to a bootstrapped reference circuit.
• a bootstrapped circuit comprising transistors 92, 93, 95, and 96 may provide an output voltage potential that may be applied to the gate of transistor 81.
• the voltage potential applied to the gate terminal of transistor 81 determines, at least in part, the voltage potential provided by Vccsup generator 50.
• Vccsup generator 50 may also include an enable transistor 80 to selectively connect the voltage potential provided by transistor 81 as the output voltage potential of Vccsup generator 50, namely, the Vccsup voltage potential.
• An enable signal, labeled El may be used to determine when transistor 81 provides the Vccsup voltage potential.
• FIG. 2 may be used to indicate when all or portions of integrated circuit 10 may enter a stand-by or inactive mode, although the scope of the present invention is not limited in this respect. Consequently, enable signal El may be generated by inverting the ACTIVE# signal so that transistor 80 is on when transistor 89 is off. In contrast, when integrated circuit 10 is not in a stand-by or low-leakage mode, enable signals El and E2 may be disabled and the ACTIVE# signal may be enabled so that the Vccsup voltage potential may be driven to Vcc by transistor 89, thus allowing transistors 20 and 30 to operate normally.
• voltage reference circuit 65 may raise the Vccsup voltage potential so that the voltage applied to channel region 34 (see FIG. 1) is greater than the voltage potential on source region 31.
• the Vccsup voltage potential is at least 0.4 volts greater than the Veep voltage potential 42.
• the scope of the present invention is not limited in this respect as the voltage differential may be increased or reduced as desired.
• voltage reference circuit 65 may also include transistors 97 and 98 connected to a RESET#.ACTIVE signal.
• RESET#.ACTIVE signal When the RESET#.ACTIVE signal is activated (e.g., indicating the core transistors 20 and 30 are active), transistors 91 and 98 may pull up the voltage potential on the drain of transistor 96 to reduce the risk that the bootstrapped circuit comprising transistors 92, 93, 95, and 96 does not resolve to the zero- current state solution.
• Vccsup generator 50 may provide a substantially constant voltage potential for Vccsup even if Veep voltage potential 41 should vary.
• transistor 82 may be advantageous because it may be less complex and formed in a smaller surface area than the particular embodiment shown in FIG. 3. Again, it may also be desirable to use both embodiments in the same integrated circuit.
• embodiment 100 may also optionally include a Vss generator 60.
• Vss generator 60 may comprise transistors 83 and 84 that "float-up" Vsssup voltage potential 40.
• Vss generator 60 may also include an enable transistor 85 that may be controlled by an enable signal labeled E4. For example, if integrated circuit 10 is in a low leakage or inactive mode, transistor 85 may be enabled so that transistors 83-84 provide a Vss voltage potential that is greater than Vsssup voltage potential 40.
• the Vss voltage potential may be at least 0.4 volts greater than the Vsssup voltage potential 40.
• the difference in voltage potential between the voltage potential applied to channel region 24 and the corresponding source region 21 may be changed as desired, for example, by sizing transistors 83 and 84 differently.
• the use of transistors 83 an 84 in this particular embodiment may provide a Vss voltage potential that is about two Vt's (threshold voltage potentials) above Vsssup voltage potential 40.
• this is not intended as a limitation of the present invention as in alternative embodiments devices with low threshold voltages may be used.
• the scope of the present invention is not limited to embodiments that use two transistors as a single or a plurality of transistors may be used in alternative embodiments.
• Vss generator 60 may be provided with a feedback circuit 61 (see FIG. 2).
• FIG. 4 is provided as an example of an implementation for a feedback circuit 61 using a differential amplifier 45 connected to a transistor 86 and resistive elements Rl and R2.
• Differential amplifier 45 may be implemented with transistors 102- 106 and resistive elements Rl and R2 may be provided by a series of transistors 100 as shown in FIG. 4.
• the consumption of current by transistors 20 and 30 may result in the Vss voltage potential rising above Vsssup voltage potential 40.
• Feedback circuit 61 may limit how high Vss may rise relative to a reference voltage provided by Rl and R2.
• the output signal of differential amplifier 45 may be used to drive the gate of transistor 86. This, in turn, may source an amount of current sufficient to stabilize the Vss voltage potential if it is driven above the Vsssup voltage potential 40 by transistors 83 and 84. As shown in FIGs. 2 and 4, this embodiment may also include enable transistors 87 and 107 that may be controlled by an enable signal labeled E3. Enable signal E3 in conjunction an ACTIVE signal (see FIG. 2) may be used to determine when the Vss voltage potential is provided by transistor 88 or by transistor 86 in conjunction with transistors 83 and 84.
• transistor 86 may provide additional current to integrated circuit 10 if the Vss potential would otherwise be driven up too high. This may occur, for example, when integrated circuit 10 transitions from an inactive to active state (e.g. the core of integrated circuit 10 is "hot" immediately after high frequency operation and the leakage, and thus the overall current demand, may be high).
• transistors 102-107 in sub-threshold mode.
• a capacitor may be placed between the gate and drain of feedback transistor 86 to provide stability to feedback amplifier 45.
• the present invention provides circuits and methods by which the leakage current of an integrated circuit may be reduced.
• the channel region of a transistor may be reverse biased with respect to its current carrying electrodes to reduce the flow of leakage current. The reverse biasing of the channel or body region relative to the current carrying electrodes may increase the potential barrier created by the channel region. Consequently, this may make it more difficult for electrons to pass between the current carrying electrodes of the transistor.
• a voltage potential may be selectively applied to the channel region of a p-channel device or to the source region of a n-channel device to reduce the amount of leakage current. It should also be understood that a voltage potential may also be selectively applied to other terminals of a transistor. Furthermore, some of the embodiments described above included raising a voltage potential that was provided to the integrated circuit so that the channel region of a transistor may be reversed biased with respect to its source region.

Landscapes

• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Semiconductor Integrated Circuits (AREA)
• Logic Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=24368271

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (3)

Citations (3)

Family Cites Families (11)

• 2001
  • 2001-04-19 TW TW090109435A patent/TW501278B/zh not_active IP Right Cessation
  • 2001-06-01 JP JP2002511471A patent/JP2004503948A/ja active Pending
  • 2001-06-01 KR KR1020027016892A patent/KR100551143B1/ko not_active IP Right Cessation
  • 2001-06-01 CN CNB018140807A patent/CN1236560C/zh not_active Expired - Fee Related
  • 2001-06-01 AU AU2001265321A patent/AU2001265321A1/en not_active Abandoned
  • 2001-06-01 WO PCT/US2001/017839 patent/WO2001097380A1/en active IP Right Grant
• 2009
  • 2009-06-09 JP JP2009137804A patent/JP2009207178A/ja active Pending

Patent Citations (3)

Also Published As

Similar Documents

Legal Events