WO2001038611A1 - Plaquette de silicium pour plaquette epitaxiee, plaquette epitaxiee, et procede de fabrication correspondant - Google Patents
Plaquette de silicium pour plaquette epitaxiee, plaquette epitaxiee, et procede de fabrication correspondant Download PDFInfo
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- WO2001038611A1 WO2001038611A1 PCT/JP2000/008204 JP0008204W WO0138611A1 WO 2001038611 A1 WO2001038611 A1 WO 2001038611A1 JP 0008204 W JP0008204 W JP 0008204W WO 0138611 A1 WO0138611 A1 WO 0138611A1
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- WIPO (PCT)
- Prior art keywords
- wafer
- epitaxy
- void
- epitaxial
- silicon wafer
- Prior art date
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 65
- 239000010703 silicon Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 238000000034 method Methods 0.000 title claims description 17
- 239000012298 atmosphere Substances 0.000 claims abstract description 16
- 230000001590 oxidative effect Effects 0.000 claims abstract description 10
- 238000000407 epitaxy Methods 0.000 claims description 75
- 230000007547 defect Effects 0.000 claims description 67
- 238000010438 heat treatment Methods 0.000 claims description 46
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 45
- 239000011800 void material Substances 0.000 claims description 31
- 229910052757 nitrogen Inorganic materials 0.000 claims description 22
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 11
- 229910052739 hydrogen Inorganic materials 0.000 claims description 11
- 239000011261 inert gas Substances 0.000 claims description 8
- 238000001816 cooling Methods 0.000 claims description 4
- 230000008030 elimination Effects 0.000 claims 1
- 238000003379 elimination reaction Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 137
- 239000013078 crystal Substances 0.000 description 38
- 239000000758 substrate Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 11
- 238000002474 experimental method Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000005247 gettering Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 241000652704 Balta Species 0.000 description 1
- 241000255925 Diptera Species 0.000 description 1
- 241000238413 Octopus Species 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
- C30B15/20—Controlling or regulating
- C30B15/203—Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
- C30B15/20—Controlling or regulating
- C30B15/206—Controlling or regulating the thermal history of growing the ingot
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
Definitions
- the present invention relates to a substrate for an epitaxial wafer, which has less crystal defects in the epitaxial layer than before, an epitaxial wafer, and a method of manufacturing the same.
- epitaxy wafers that have an epitaxy layer with excellent crystallinity (hereinafter sometimes simply referred to as epi layer) is increasing year by year.
- epitaxy wafers have various crystal defects, which adversely affect the device and lower the yield, so it is necessary to reduce them.
- the crystal defects in the polycrystallized epitaxy layer are generated from particles adhering to the surface of the epitaxy growth silicon wafer (hereinafter sometimes simply referred to as a substrate) that forms the epitaxy layer.
- a substrate the epitaxy growth silicon wafer
- epi growth epitaxial growth
- void-type defects exposed on the substrate surface are mainly found in Grown-in defects introduced during silicon single crystal growth.
- Force S which is a vacancy cluster exposed on the wafer surface.Conventionally, this void was thought to be a shallow pit after epi growth, but not a crystal defect.
- SF epi stacking fault
- the present invention has been made in view of such problems, and has as its object to provide a silicon wafer for epitaxy growth and an epitaxy wafer with reduced SF generation, and a method of manufacturing the same. .
- the present invention for solving the above-mentioned problems is directed to a silicon wafer for epitaxy growth, wherein void-type defects are not exposed at least on the surface on which the epitaxy layer is grown. It is a silicon wafer.
- the silicon wafer for epitaxy growth in which at least the void type defect is not exposed on the surface where the epitaxy layer is grown can prevent the generation of SF during the epitaxy growth. It is clear that SF originates from void-type defects, so using such an aepitaxial substrate without such void-type defects would prevent SF generation in the epi layer. Because you can.
- the “surface on which the epitaxial layer is grown” of the present invention substantially means the substrate surface (epitaxial layer and the substrate) immediately after such a hydrogen beta and just before the epitaxial layer is grown. Boundary).
- the void-type defects do not exist at a depth of at least 10 nm from the surface on which the epitaxial layer is grown.
- nitrogen is doped in the epitaxial growth silicon layer 8.
- the present invention also measures the number of void-type defects exposed on the surface of the silicon wafer and / or the number of void-type defects existing at a depth of at least 10 nm from the surface of the silicon wafer. And selecting a silicon wafer in which the number of these void-type defects is equal to or less than a predetermined value, and growing an epitaxy layer on the surface of the selected silicon wafer. ⁇ This is a method for manufacturing an e-wafer.
- the present invention extracts one or more wafers from a wafer in the same manufacturing lot, and counts the number of void defects exposed on the wafer surface and / or at least 10 wafers from the wafer surface.
- the number of void-type defects existing at a depth of up to nm is measured, and the number of these void-type defects is equal to or less than a predetermined value. That is, the specification of the epitaxial wafer required by the user (the upper limit of the number of SFs)
- This method is characterized in that the number of board-type defects allowed from (1) is set in advance, and an epitaxial wafer that satisfies this is selected to grow an epitaxial layer. In this way, defective wafers can be reduced in the production of epitaxial wafers, and silicon single crystal wafers suitable for epitaxy wafers according to the user's specifications can be manufactured under the same conditions. You can provide feedback to
- the present invention provides a method for heat-treating a silicon wafer having a void defect exposed on the surface and a silicon wafer having a void defect at a depth of at least 10 nm from the surface.
- heat treatment heat treatment is performed at a temperature of 110 to 130 ° C. in a non-oxidizing atmosphere, and then the heat treatment is continuously performed without cooling to less than 700 ° C. It is preferable to perform a heat treatment at a temperature of 700 to 130 ° C. in an oxidizing atmosphere.
- the first-stage heat treatment in a non-oxidizing atmosphere can diffuse out the natural oxide film on the wafer surface and the inner wall oxide film on the void near the surface. Therefore, in the subsequent heat treatment in an oxidizing atmosphere, interstitial silicon can be efficiently implanted, and voids near the surface can be eliminated. With respect to the voids exposed on the surface, the opening shape can be made smooth by forming an oxide film, and it can be prevented from becoming a source of SF in the subsequent epitaxial growth.
- the temperature is not lowered to less than 700 ° C. after the first-stage heat treatment, it is possible to prevent the regrowth of the inner wall oxide film which hinders the implantation of interstitial silicon into the void.
- the heat treatment may be performed by introducing an inert gas after the hydrogen baking before the growth of the epitaxy layer in the epitaxy step.
- a nitrogen-doped silicon wafer as the silicon wafer.
- the use of the nitrogen doped wafer can provide a higher gettering effect due to the effect of nitrogen.
- FIG. 1 is a view showing a cross-sectional TEM image, (a) is a microscopic image, and (b) is a diagram schematically showing a defect based on the microscopic image.
- Fig. 2 is an enlarged view showing the results of cross-sectional TEM observation of a wafer not doped with nitrogen.
- (A) is a microscopic observation
- (b) is a schematic diagram of the microscopic observation. is there.
- FIG. 3 is an enlarged view showing another result of cross-sectional TEM observation of a wafer not doped with nitrogen.
- (A) is a microscopic observation
- (b) is a schematic of the microscopic observation.
- FIG. 4 is an enlarged view showing another result of cross-sectional TEM observation of a wafer not doped with nitrogen.
- (A) is a microscopic observation diagram
- (b) is a microscopic observation diagram.
- FIG. 5 is an enlarged view showing the result of cross-sectional TEM observation of a nitrogen-doped wafer.
- FIG. 6 is an enlarged view showing another result of cross-sectional TEM observation of a nitrogen-doped wafer.
- FIG. 7 is an enlarged view showing another result of cross-sectional TEM observation of a nitrogen-doped wafer.
- FIGS. 8 (a) to 8 (d) are explanatory diagrams showing a state in which SF is formed in a nitrogen-doped wafer.
- FIGS. 9 (a) to 9 (d) are explanatory views showing a state in which SF is formed in a wafer which is not doped with nitrogen.
- the present inventors have completed the present invention by performing the following experiments in order to clarify the cause of generation of SF generated in the epitaxial layer.
- FIGS. 1 (a) and 1 (b) cross-sectional TEM (transmission electron microscope) observation was performed on the SF on the surface of these epitaxial layers as shown in FIGS. 1 (a) and 1 (b).
- FIG. 1 (a) is a microscopic observation diagram
- FIG. 1 (b) is a diagram schematically showing a defect based on the microscopic observation diagram
- Fig. 2 (a) (b) to Fig. 4 (a) (b) show the results of enlarging the part enclosed by the ellipse in Fig. ).
- FIGS. 2 (a) to 4 (a) are microscopic observation diagrams
- FIGS. 2 (b) to 4 (b) are schematic diagrams of microscopic observation diagrams. In each case, it can be seen that some crystal defect exists below the SF peak.
- SF on the surface of the epitaxy layer was present in several wafers or about 8 inches.
- 5 to 7 show the results of cross-sectional TEM observation of the three SFs from the 110> direction as in Experiment 1. According to this cross-sectional TEM observation, it is 10 to 40 from the top of SF just below SF as in the case of nitrogen non-doping. It was found that rod-like and plate-like voids peculiar to nitrogen dope wafers were observed at a distance of about nm.
- the mechanism of SF generation from void-type defects is considered as follows.
- the voids are rod-shaped and plate-shaped, and the plate-shaped cut has 20 nm x 1
- the apex of the generated SF is at least 10 nm away from the void-type defects. Therefore, in order to surely prevent the generation of SF, it is preferable that void-type defects do not exist at least to a depth of 10 nm from the surface immediately before the growth of the epitaxial layer. From the above research by the present inventors, it has been clarified that void generation existing near the surface of the epitaxial growth wafer is involved in the generation of SF in the epitaxial layer. Therefore, in order to prevent the generation of SF, it is sufficient that no void-type defect exists near the surface of the epitaxial growth layer.
- the void-type defect is not exposed or "the void-type defect does not exist” means that the void-type defect which is a source of SF during epitaxy is exposed or does not exist.
- the existence of such a void-type defect, which is a source of SF, near the surface of an epitaxial growth wafer manufactured under a specific manufacturing condition is determined by the manufacturing method.
- Epitaxial layers can be grown on other wafers manufactured under the same manufacturing conditions, and the LPD observed on the surface can be determined by observing the substance with an optical microscope or an electron microscope.
- an epitaxial layer is grown on the surface of the wafer.
- a defect-free wafer for example, FZ wafer can be used.
- CZ wafers defect-free wafers can be obtained by controlling the conditions during crystal pulling, and this can be applied.
- Another method is to use a CZ wafer, which is manufactured under normal conditions and has void-type defects on the surface and bulk of the wafer, and heat-treats it. This is a method in which the epitaxial growth is performed after the mosquito or void type defect that eliminates the type defect is made into a form that does not become a SF generation source.
- the present invention has been completed by scrutinizing various conditions based on the above idea.
- an example of an implementation flow of the present invention will be described, but the present invention is not limited to these.
- an epitaxial silicon wafer is required.
- silicon wafers for wafer growth manufacture wafers without void defects throughout the wafer, or wafers with no void defects exposed at least on the surface where the epitaxial layer is grown.
- FZ wafers and VZG (V: pulling speed, G: temperature gradient at the crystal-solid interface) during pulling of CZ crystal are controlled by:
- V pulling speed
- G temperature gradient at the crystal-solid interface
- Such an FZA wafer is mainly used for a discrete device, and has never been used as an epitaxial growth substrate for forming a so-called integrated circuit, which is the subject of the present application. Also, since the defect-free CZ wafer was developed as a substrate that can obtain characteristics comparable to an epitaxial wafer at a low cost, the idea of forming an additional epitaxial layer on this wafer and using the wafer is not considered. It has never been before.
- the shape (size and shape) of the void changes depending on the crystal pulling conditions and the presence or absence of nitrogen doping. Therefore, one or more wafers are manufactured under specific manufacturing conditions. Then, the number of void-type defects exposed on the surface of the wafer and / or the number of void-type defects existing at a depth of at least 1 O nm from the surface of the wafer are measured.
- the number of void-type defects is less than or equal to a predetermined value, that is, the allowable number of void-type defects is set in advance based on the specifications of the epitaxy wafer required by the user (the upper limit of the number of SFs), and this is satisfied In this case, if the wafer manufactured under these manufacturing conditions is used for growing the epitaxial layer, defective wafers can be reduced. In addition, since the relationship between the manufacturing conditions (single crystal pulling conditions) and the SF generated in the epitaxial layer is required, it can be fed back to the silicon single crystal wafer manufacturing conditions suitable for epitaxy. .
- a wafer to be measured is oxidized by etching after forming an oxide film of about 20 nm by thermal oxidation. The measurement may be performed after removing the film.
- wafers produced from CZ single crystals grown at a normal CZ pulling speed are more or less.
- the void can be a void where the void does not exist from its surface at least up to a depth of 10 nm.
- the exposed shape should not be a source of SF.
- the heat treatment conditions can be set by experimentally obtaining the relationship between the shape of the pit and the occurrence of SF.
- the appropriate heat treatment that can eliminate void-type defects not exposed on the wafer surface depends on the shape and size of the voids present in the wafer. Therefore, appropriate heat treatment conditions may be experimentally determined in consideration of the manufacturing conditions (eg, conditions for pulling a single crystal) of AH8 to which heat treatment is applied.
- the heat treatment furnace for performing these heat treatments is not particularly limited, and examples thereof include a heater heating type batch furnace, a lamp heating type RTA (Rapid Thermal Anneal) furnace, and the like. It can also be incorporated into the epitaxy process using an epitaxy growth system.
- the first heat treatment is performed in a non-oxidizing atmosphere, preferably in an atmosphere containing hydrogen.
- a non-oxidizing atmosphere preferably in an atmosphere containing hydrogen.
- the natural oxide film on the surface is removed, and the inner wall oxide film of the void type defect is removed by outward diffusion. If the temperature is less than 110 ° C, removal of the natural oxide film on the surface and outward diffusion of the inner wall oxide film are likely to be insufficient. Since the natural oxide film on the surface can be removed in a short time, immediately switch to a gas such as argon that does not have an etching effect on the substrate and expand the outer oxide film on the inner wall.
- the voids (pits) exposed on the surface are smoothed by the migration of silicon atoms on the surface, and the internal voids are removed from the inner wall oxide film and the interstitial silicon is removed. It will be easier to accept kon.
- heat treatment is performed at a temperature of 700 to 130 ° C. in an oxidizing atmosphere.
- a thermal oxide film is formed on the surface, and the pit shape on the surface becomes smoother.
- the interstitial silicon is efficiently implanted into the void from which the inner wall oxide film has been removed by the first heat treatment, and the void is removed. It is filled. If the temperature is 700 ° C. or more, sufficient interstitial silicon implantation for void annihilation occurs.
- the inner wall oxide film regrows, so the first and second heat treatments do not require cooling to less than 700 ° C. It is preferable to carry out continuously.
- the oxide film on the wafer surface formed by this heat treatment is removed with a hydrofluoric acid aqueous solution and then used for epitaxial growth.
- the atmosphere gas is changed to argon or the like.
- the inner wall oxide film of void-type defects not exposed on the wafer surface is effectively diffused outward, and silicon atoms are reduced.
- the migration can eliminate the voids.
- the atmosphere in which the heat treatment after the hydrogen baking is performed is not required to be replaced with 100% inert gas or the ratio of inert gas to hydrogen is fixed at a constant value.
- the heat treatment may be performed in a state where the inert gas and the hydrogen gas are mixed and the ratio thereof changes with time.
- the ratio of Ar to hydrogen gas is preferably about 3: 1.
- an epitaxy wafer in which generation of SF is extremely suppressed can be manufactured.
- the force to put the nitride in the quartz crucible in advance, the injection of the nitride into the silicon melt By setting the atmosphere gas to an atmosphere containing nitrogen or the like, nitrogen can be doped into the pulled crystal. At this time, the doping amount in the crystal can be controlled by adjusting the amount of the nitride, the concentration of the nitrogen gas, or the introduction time.
- the present invention will be described in detail with reference to Examples of the present invention, but the present invention is not limited thereto.
- a silicon single crystal is grown at a normal pulling rate (about lmm / min) by doping with nitrogen, and a CZ silicon single crystal wafer of 8 inches in diameter (crystal axis orientation ⁇ 100>, p-type, 10-inch) ⁇ cm, oxygen concentration of 15 ppma (JEIDA standard)), nitrogen concentration of 1 ⁇ 10 4 cm 3 were prepared.
- silicon wafers were subjected to a heat treatment at a temperature of 1200 ° C. for 1 hour in an argon atmosphere in a heater-heated batch furnace, and then the wafers were removed from the furnace. Continuously in an oxygen atmosphere without cooling to temperatures below 800 ° C 1 2
- Example 1 As in Example 1, four epitaxy wafers each having an epitaxy layer of about 4 ⁇ m formed on the surface of this epitaxial growth silicon wafer were prepared, and the LPD on the epitaxy surface was observed with an optical microscope. . As a result, no SF was observed on the entire epitaxy of each ewa.
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Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00976394A EP1154048B1 (en) | 1999-11-25 | 2000-11-21 | Method of manufacture of a silicon epitaxial wafer |
DE60045735T DE60045735D1 (de) | 1999-11-25 | 2000-11-21 | Verfahren zur herstellung von silizium epitaktischem wafer |
US09/890,007 US6626994B1 (en) | 1999-11-25 | 2000-11-21 | Silicon wafer for epitaxial wafer, epitaxial wafer, and method of manufacture thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33404099A JP3601383B2 (ja) | 1999-11-25 | 1999-11-25 | エピタキシャル成長用シリコンウエーハ及びエピタキシャルウエーハ並びにその製造方法 |
JP11/334040 | 1999-11-25 |
Publications (1)
Publication Number | Publication Date |
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WO2001038611A1 true WO2001038611A1 (fr) | 2001-05-31 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/008204 WO2001038611A1 (fr) | 1999-11-25 | 2000-11-21 | Plaquette de silicium pour plaquette epitaxiee, plaquette epitaxiee, et procede de fabrication correspondant |
Country Status (7)
Country | Link |
---|---|
US (1) | US6626994B1 (ja) |
EP (1) | EP1154048B1 (ja) |
JP (1) | JP3601383B2 (ja) |
KR (1) | KR100741540B1 (ja) |
DE (1) | DE60045735D1 (ja) |
TW (1) | TW524898B (ja) |
WO (1) | WO2001038611A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1293591A2 (en) * | 2001-09-14 | 2003-03-19 | Wacker Siltronic AG | Silicon semiconductor substrate and method for production thereof |
WO2004007815A1 (ja) * | 2002-07-12 | 2004-01-22 | Shin-Etsu Handotai Co.,Ltd. | エピタキシャル成長用シリコンウエーハ及びエピタキシャルウエーハ並びにその製造方法 |
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DE10066107B4 (de) * | 2000-09-25 | 2008-11-27 | Mitsubishi Materials Silicon Corp. | Verfahren zur Wärmebehandlung eines Siliciumwafers |
TWI303282B (en) * | 2001-12-26 | 2008-11-21 | Sumco Techxiv Corp | Method for eliminating defects from single crystal silicon, and single crystal silicon |
JP4376505B2 (ja) * | 2002-10-30 | 2009-12-02 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
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JP2000203999A (ja) * | 1999-01-08 | 2000-07-25 | Sumitomo Metal Ind Ltd | 半導体シリコンウェ―ハとその製造方法 |
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JP3763630B2 (ja) * | 1997-01-24 | 2006-04-05 | 株式会社Sumco | 薄膜エピタキシャルウェーハおよびその製造方法 |
JP3460551B2 (ja) * | 1997-11-11 | 2003-10-27 | 信越半導体株式会社 | 結晶欠陥の少ないシリコン単結晶ウエーハ及びその製造方法 |
JP3899725B2 (ja) * | 1998-09-30 | 2007-03-28 | 株式会社Sumco | 単結晶体の欠陥除去方法 |
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- 2000-11-21 WO PCT/JP2000/008204 patent/WO2001038611A1/ja active Application Filing
- 2000-11-21 KR KR1020017009292A patent/KR100741540B1/ko not_active IP Right Cessation
- 2000-11-21 DE DE60045735T patent/DE60045735D1/de not_active Expired - Lifetime
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1293591A2 (en) * | 2001-09-14 | 2003-03-19 | Wacker Siltronic AG | Silicon semiconductor substrate and method for production thereof |
EP1293591A3 (en) * | 2001-09-14 | 2003-06-04 | Wacker Siltronic AG | Silicon semiconductor substrate and method for production thereof |
US6767848B2 (en) | 2001-09-14 | 2004-07-27 | Wacker Siltronic Gesellschaft Für Halbleiter Materialien AG | Silicon semiconductor substrate and method for production thereof |
WO2004007815A1 (ja) * | 2002-07-12 | 2004-01-22 | Shin-Etsu Handotai Co.,Ltd. | エピタキシャル成長用シリコンウエーハ及びエピタキシャルウエーハ並びにその製造方法 |
CN1312327C (zh) * | 2002-07-12 | 2007-04-25 | 信越半导体株式会社 | 外延生长用硅晶片及外延晶片及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1154048A1 (en) | 2001-11-14 |
EP1154048B1 (en) | 2011-03-16 |
JP2001151596A (ja) | 2001-06-05 |
US6626994B1 (en) | 2003-09-30 |
EP1154048A4 (en) | 2004-05-12 |
TW524898B (en) | 2003-03-21 |
KR100741540B1 (ko) | 2007-07-20 |
KR20010101656A (ko) | 2001-11-14 |
DE60045735D1 (de) | 2011-04-28 |
JP3601383B2 (ja) | 2004-12-15 |
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