Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
  • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
  • H01L2221/1068—Formation and after-treatment of conductors
  • H01L2221/1073—Barrier, adhesion or liner layers
  • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
  • H01L2221/1089—Stacks of seed layers

Definitions

• the present invention pertains to the field of electroplating metals or alloys for filling high aspect ratio openings, such as trenches and vias, for semiconductor metallization interconnects, thin film heads, or micromachined Microelectromechanical Systems (MEMS) devices.
• embodiments of the present invention provide improved seed layers for electroplating copper or silver interconnects in semiconductor devices, and methods and apparatus for fabricating such improved seed layers.
• the improved seed layers facilitate reliable, void-free filling of small openings with high aspect ratios for so called "Damascene” and “Dual Damascene” copper and/or silver interconnects.
• filling trenches and/or vias formed on a wafer by electroplating copper metal to form semiconductor device interconnects requires that a metallization layer (often referred to in the art as a seed layer or a base layer) be formed over the wafer surface.
• the seed layer is required: (a) to provide a low-resistance electrical path (to enables uniform electroplating over the wafer surface); (b) to adhere well to the wafer surface (usually to an oxide-containing a dielectric film such as SiO , SiO ⁇ , or SiO ⁇ N ⁇ ); and (c) to be compatible with subsequent electroplating copper thereon.
• a low-resistance electrical path to be comprised of an adequately thick, low-resistivity material.
• the requirement of adhering well to the wafer surface is typically fulfilled by disposing an intermediary barrier (or adhesion) metallic layer having a strong affinity for oxygen atoms under the seed layer.
• the barrier metallic layer is formed prior to the seed layer to provide good adhesion: (a) to the oxide surface underneath it (the barrier layer provides good adhesion to the oxide surface by sharing oxygen atoms) and (b) to the seed layer above it (the barrier metallic layer provides good adhesion to the seed layer by metal to metal bonds).
• the barrier layer is often also referred to as an "adhesion layer" or a "liner".
• the barrier layer also serves to mitigate copper out-diffusion directly into the device, or indirectly (through an insulating or a dielectric layer) into the device.
• the barrier layer is usually chosen from the refractory metals or their alloys, such as for example, Ta, TaNx, Cr, CrNx, Ti,
• the requirement of being compatible with electroplating copper is fulfilled by choosing a seed layer that does not react spontaneously (i.e., by displacement) with copper electrolyte used during the electroplating. This is satisfied by requiring that the seed layer does not comprise a metal or alloy that is less noble than copper.
• a seed layer comprises a copper layer that is deposited by a "dry” technique, such as by physical vapor deposition (“PVD”), including but not limited to sputtering, ion plating, or evaporation, or by chemical vapor deposition (“CVD”).
• PVD physical vapor deposition
• CVD chemical vapor deposition
• the seed layer may also be deposited by a "wet” electroless plating process.
• the copper seed layer thickness is typically in a range of about 300 A to about 2,000 A on the field (i.e., the top surface of the wafer outside trenches and via openings).
• the barrier layer is typically deposited to a thickness of about 50A to about 50 ⁇ A (on the field) by either a PVD or a CVD technique.
• the PVD techniques include, for example and without limitation, techniques such as evaporation, ion plating, and various sputtering techniques, such as DC and/or RF plasma sputtering, bias sputtering, magnetron sputtering, or Ionized Metal Plasma (IMP) sputtering.
• sputtering techniques such as DC and/or RF plasma sputtering, bias sputtering, magnetron sputtering, or Ionized Metal Plasma (IMP) sputtering.
• IMP Ionized Metal Plasma
• MOCVD Metal Organic Chemical Vapor Deposition
• CupraselectTM which precursor is sold by Schumacher, Inc.
• Cu(II) hexafluoroacetylacetonate is another precursor used for CVD Cu.
• the latter can be reacted with hydrogen gas to obtain high purity copper.
• the CVD and the electroless techniques produce conformal deposition, with substantially uniform thickness over the entire surface, including over the field and the bottom and sidewall surfaces of the openings.
• AR Aspect ratio
• D depth
• W width, or diameter
• commercial copper electrolytes contain additives that adsorb and locally inhibit (or suppress) growth outside the openings (i.e., on the field). Further, growth inhibition inside the openings is decreased from that achieved outside the openings due to slow replenishment of the additives inside the openings as compared with replenishment of the additives on the field. As a result, the deposition rate inside the openings is faster than outside, thereby facilitating void-free copper fill.
• Other well known reasons for voids in copper electrofill include discontinuous (or incomplete coverage of) seed layers inside the openings, and pinching-off of opening walls (for example, by overhangs of the top corners) prior to plating.
• the openings may consist of vias, trenches, or patterned photoresist.
• an insulating or a dielectric layer is pattern-etched to form openings therein.
• a barrier (or an adhesion) metallic layer and a seed layer are deposited over the insulating layer to metallize its field (the surface surrounding openings), as well as the sidewalls and bottom surfaces of the openings.
• copper electroplating is performed over the entire metallized surface, including the top surface (the field) surrounding the openings, and inside the patterned openings.
• the seed layer inside the openings must completely cover the bottom and the sidewall surfaces inside the openings without discontinuities, or else there will be voids in the copper electrofill.
• the seed layer must not be so thick on the sidewalls that it pinches-off the very narrow openings and should not overhang the top corners of the openings so that it pinches-off the very small openings.
• the barrier layer must also be continuous inside the openings.
• the seed layer must be sufficiently thick on the top surface (the field) to provide a low-resistive electrical path that facilitates uniform plating across the surface of the wafer. That is, the seed layer must be sufficiently thick (for example, a Cu seed layer should preferably be at least about 1,000 A) on the field to avoid radial non-uniformity across the wafer caused by a voltage (or IR) drop between a contact at the edge of the wafer to the center of the wafer. Any voltage drop (and resulting non-uniformity therefrom) becomes more severe as the resistance of the seed layer increases due to high resistivity and/or insufficient thickness.
• a copper seed layer to a thickness of about 1,000 A to about 2,000A on the top surface (field) by a PVD technique.
• the typical thickness of about 300A to about 1,000A (on the field), deposited by the CVD techniques may not be sufficient.
• the non-conformal PVD techniques while providing adequate thickness on the field, fail to provide continuous and complete step coverage inside very narrow openings with large AR. They also result in substantial overhangs at the top corners of the openings.
• the conformal CVD or electroless techniques while providing continuous and complete step coverage of the seed layer inside very narrow openings, pinch-off the small openings when used at thicknesses required on the field for a low-resistance electrical path. As a result, typical conformal CVD or electroless seed layers are too thin on the field and too thick inside the very narrow openings.
• Embodiments of the present invention advantageously satisfy the above- identified need in the art and provide a method and apparatus to produce seed layers used to produce void-free copper or silver electrochemical filling of small openings having high aspect ratios.
• One embodiment of the present invention is a method for making metallic interconnects comprising: (a) forming a patterned insulating layer on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening; (b) depositing a barrier layer over the field and inside surfaces of the at least one opening; (c) depositing a first seed layer over the barrier layer using a first deposition technique; (d) depositing a second seed layer over the first seed layer using a second deposition technique, the first and second deposition techniques being different; and (e) electroplating a metallic layer over the second seed layer, the electroplated metallic layer comprising a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
• a substantially conformal and a substantially non-conformal seed layers are deposited in a single tool, without breaking vacuum, or without exposing the wafer to the atmosphere between the deposition of the two seed layers.
• the single deposition tool may comprise two or more chambers, at least one chamber for the deposition of the conformal seed layer and at least another chamber for the deposition of the non-conformal seed layer.
• a single deposition tool comprises a single chamber in which both the conformal and the non-conformal seed layers are deposited utilizing either: (a) two or more distinct steps, wherein the deposition conditions (or parameters) during the first step are suitable for the deposition of a substantially conformal (or a non-conformal) seed layer and the deposition conditions during the second step are suitable for the deposition of a substantially non-conformal (or a conformal) seed layer, or (b) wherein the deposition conditions are varied continuously or gradually, thereby changing the nature of the seed layer from substantially conformal to substantially non-conformal, or vice versa, or (c) a combination of at least one distinct step and at least one gradual variation of the deposition conditions.
• FIG. 1 shows a cross-sectional view of an inventive structure formed in accordance with a preferred embodiment of the present invention wherein a first, conformal seed layer is deposited over a barrier layer, followed by a second, non- conformal seed layer deposited over the first, conformal seed layer;
• FIG. 2 shows a cross-sectional view of the inventive structure of FIG. 1 after removing excess plated copper or silver overlying an opening and the field, as well as removing the seed layers and barrier layer overlying the field surrounding the opening;
• FIG. 3 shows a cross-sectional view of an inventive structure formed in accordance with an alternative embodiment of the present invention wherein a first, non-conformal seed layer is deposited over a barrier layer, followed by a second, conformal seed layer deposited over the first, non-conformal seed layer;
• FIG. 4 shows a cross-sectional view of the inventive structure of FIG. 3 after removing excess plated copper or silver overlying an opening and the field, as well as removing the seed layers and barrier layer overlying the field surrounding the opening;
• FIG. 5 shows a scanning electron microscope ("SEM") photograph of a cleaved cross-section (with a tilt angle of 30°) of a trench (the trench is -O.lO ⁇ m wide, ⁇ 1.4 ⁇ m deep, and has an aspect ratio of -14:1) having seed layers formed in accordance with one embodiment of the present invention;
• FIG. 6 shows an SEM photograph of the trench shown in FIG. 5 without a tilt, and with a larger enlargement
• FIG. 7 shows a schematic (not to scale) top view of a cluster tool apparatus, and a frontal view of its controller (e.g. computer), in accordance with a preferred embodiment of the invention.
• FIG. 1 shows a cross-sectional view of an inventive structure formed in accordance with a preferred embodiment of the present invention wherein a first, conformal seed layer is deposited over a barrier layer, followed by a second, non- conformal seed layer deposited over the first, conformal seed layer.
• the conformal seed layer provides continuous and complete step coverage inside the openings, while the non-conformal seed layer provides a low resistance electrical path over the top surface (field) surrounding the openings to enable uniform plating across the substrate (or wafer).
• the thickness of the combined seed layers be at least about 1,000A on the field.
• barrier layer 18 is deposited over the entire surface of wafer 10, including over patterned insulating layer 12 (having had opening 16 patterned therein in accordance with any one of a number of methods that are well known to those of ordinary skill in the art), using a conformal Chemical Vapor Deposition ("CVD") technique.
• CVD Chemical Vapor Deposition
• barrier layer includes examples wherein: (a) the barrier layer acts both as an adhesion layer and as a barrier layer; (b) a barrier layer separate from an adhesion layer is used; and (c) a multiplicity of layers is used, some acting as adhesion layers, some acting as barrier layers, or some acting as both.
• wafer is used, this also includes the term substrate as it is used in the art. Still further, although the present invention is described in the context of opening 16, in practice, a multiplicity of openings are patterned and filled in accordance with the present invention.
• barrier layer 18 ensures substantially complete and continuous coverage of the bottom and sidewall surfaces inside opening 16.
• barrier layer 18 may also be deposited using a Physical Vapor Deposition ("PVD") technique that provides continuous bottom and sidewall coverage.
• PVD Physical Vapor Deposition
• barrier layer 18 may comprise, for example and without limitation, a material selected from Ta, TaNx, Cr, CrNx, Ti, TiN ⁇ ; W, WNx, and other alloys containing one or more of these materials. Further, the thickness of barrier layer 18 can be in a range of about
• barrier layer 18 occupies a certain fraction of interconnects formed in accordance with the present invention, and since barrier layer 18 has a relatively large resistivity, its thickness should be minimized. However, the thickness of barrier layer 18 should be sufficiently large to mitigate copper out-diffusion and to provide complete bottom and sidewall coverage inside opening 16. Many CVD techniques and PVD techniques are well known to those of ordinary skill in the art for forming barrier layer 18.
• conformal seed layer 20 is deposited over barrier layer 18.
• Conformal seed layer 20 can be preferably deposited by using a CVD technique, but it can also be deposited by using an electroless technique or any other substantially conformal deposition technique. Many CVD techniques and electroless techniques are well known to those of ordinary skill in the art for forming conformal seed layer 20.
• the thickness of conformal seed layer 20 can be in a range of about 5 ⁇ A to about 500 A, and more preferably in a range of about 100 A to about 300 A.
• non- conformal seed layer 22 is deposited over conformal seed layer 20.
• Non-conformal seed layer 22 can be preferably obtained using a PVD technique. Many PVD techniques are well known to those of ordinary skill in the art for forming non- conformal seed layer 22.
• the thickness of non-conformal seed layer 22 can be in a range of about lOOA to about 3,000A, and more preferably in a range of about 500A to about 1 ,800A (in the field).
• the conformal and non- conformal seed layers may comprise the same material, or they may comprise different materials.
• copper is commonly used as a seed layer, a highly conductive silver (Ag) layer can also be used.
• Ag has lower resistivity than that of Cu and, therefore, can be formed with a smaller thickness than that required when using Cu.
• conformal seed layer 20 and non-conformal seed layer 22 may comprise, for example, a material selected from Cu, Ag, or alloys comprising one or more of these metals.
• the thickness of the CVD layers is substantially uniform over the entire surface (i.e., conformal), including over field 14, and over bottom and sidewall surfaces inside opening 16.
• the best conformal CVD layers are thicker over the field than inside the openings.
• CVD Cu seed layers inside openings it is quite common for CVD Cu seed layers inside openings to have a thickness of about 80% of that over the field.
• the thickness of a CVD barrier layer inside the openings is typically only about 50% of that over the field. Thus, even the best CVD layers exhibit some overhang at the top corners of the openings.
• one deposits, by a CVD technique, a barrier layer comprised of about 200A of TaNx or WNx, then one deposits, by a CVD technique, a conformal seed layer comprised of about 300 A of Cu, finally one deposits, by a PVD technique, a non- conformal seed layer comprised of about 900 A of Cu (as measured on the field).
• the inventive "two-step" seed layer deposition ensures a continuous seed layer having excellent step coverage, and a low-resistance electrical path on the field to ensure uniform copper plating across the wafer.
• the thickness of the "two-step” seed layer inside the openings is adequate for copper plating therein.
• the thickness of the "two-step” seed layer inside the openings can be further decreased (to a range from about 100A to about 200A) to enable void-free copper filling of even smaller openings (for example, below 0.10 - 0.13 ⁇ m).
• the combined thicknesses of the barrier and seed layers at the sidewalls of the openings is about 400A on each side, thus occupying about 800 A of the 1,800 A opening. This leaves enough room (-1,000 A) to facilitate electroplating inside the opening without sealing or pinching-off of the top corners.
• substrate 10 is placed in a copper electroplating bath, and electroplating is carried out in accordance with any one of a number of methods that are well known to those of ordinary skill in the art to deposit a thickness of copper sufficient to fill patterned opening 16, with some excess, and to cover field 14 surrounding opening 16.
• excess plated copper overlying opening 16 and overlying field 14, as well as seed layers 20 and 22 and barrier layer 18 overlying field 14, are removed using any one of a number of techniques that are well known to those of ordinary skill in the art, for example, using a mechanical polishing or a chemical mechanical polishing (CMP) technique.
• CMP chemical mechanical polishing
• removal techniques such as wet or dry etching techniques may also be used to remove excess plated copper overlying opening 16 and field 14, and to remove seed layers 20 and 22 and barrier metallic layer 18 overlying field 14. It should be clear to those of ordinary skill in the art that removal may also be accomplished using a combination of techniques, including those identified above.
• electrofill opening 16 with any low resistivity material, such as a material selected from Cu, Ag, or an alloy comprising one or more of these metals.
• silver (Ag) has lower resistivity than that of Cu, and may be attractive for further reducing the dimensions of the interconnects.
• FIG. 2 shows a cross-sectional view of the inventive structure of FIG. 1 after removing excess plated copper (or silver) 24 overlying opening 16 and field 14, and removing seed layers 20 and 22 and barrier layer 18 overlying field 14 surrounding opening 16.
• FIG. 2 illustrates the filling of openings (trenches and vias) with electroplated copper (or silver) 24, as well as the lining of the bottom and sidewall surfaces of opening 16 by barrier layer 18 and seed layers 20 and 22.
• all metallic layers were removed from field 14 of insulating layer 12 which surrounds embedded electroplated copper (or silver) interconnect 24.
• FIG. 1 shows a cross-sectional view of the inventive structure of FIG. 1 after removing excess plated copper (or silver) 24 overlying opening 16 and field 14, and removing seed layers 20 and 22 and barrier layer 18 overlying field 14 surrounding opening 16.
• FIG. 2 illustrates the filling of openings (trenches and vias) with electroplated copper (or silver) 24, as well as the lining of the bottom and sidewall surfaces of opening 16
• FIG. 3 shows a cross-sectional view of an inventive structure formed in accordance with an alternative embodiment of the present invention wherein a first, non-conformal seed layer is deposited over a barrier layer, followed by a second, conformal seed layer deposited over the first, non-conformal seed layer.
• the non- conformal seed layer provides a low resistance electrical path over the top surface (field) surrounding the openings to enable uniform plating across the substrate (or wafer), while the conformal seed layer provides continuous and complete step coverage inside the openings.
• barrier layer 118 is deposited over the entire surface of wafer 110, including over patterned insulating layer 112 (having had opening 116 patterned therein in accordance with any one of a number of methods that are well known to those of ordinary skill in the art), using a conformal Chemical Vapor Deposition ("CVD”) technique.
• CVD Chemical Vapor Deposition
• barrier layer includes examples wherein: (a) the barrier layer acts both as an adhesion layer and as a barrier layer; (b) a barrier layer separate from an adhesion layer is used; and (c) a multiplicity of layers is used, some acting as adhesion layers, some acting as barrier layers, or some acting as both.
• wafer is used, this also includes the term substrate as it is used in the art.
• present invention is described in the context of opening 116, in practice, a multiplicity of openings are patterned and filled in accordance with the present invention.
• barrier layer 118 ensures complete and continuous coverage of the bottom and sidewall surfaces inside opening 116.
• barrier layer 118 may also be deposited using a
• barrier layer 118 may comprise, for example and without limitation, a material selected from Ta, TaNx, Cr, CrNx, Ti, TiNx, W, WNx, and other alloys containing one or more of these materials. Further, the thickness of barrier layer 118 can be in a range of about 3 ⁇ A to about
• barrier layer 118 occupies a certain fraction of interconnects formed in accordance with the present invention, and since barrier layer 118 has a relatively large resistivity, its thickness should be minimized. However, the thickness of barrier layer 118 should be sufficiently large to mitigate copper out-diffusion and to provide complete bottom and sidewall coverage inside opening 116. Many CVD techniques and PVD techniques are well known to those of ordinary skill in the art for forming barrier layer 118.
• non-conformal seed layer 126 is deposited over barrier layer 118.
• Non-conformal seed layer 126 can be preferably obtained using a PVD technique. Many PVD techniques are well known to those of ordinary skill in the art for forming non-conformal seed layer 126.
• the thickness of non-conformal seed layer 126 can be in a range of about 100 A to about 3, 000 A, and more preferably in a range of about 500A to about l,80 ⁇ A (on the field).
• conformal seed layer 128 is deposited over non-conformal seed layer 126.
• Conformal seed layer 128 can be preferably obtained using a CVD or electroless technique or any other substantially conformal deposition technique.
• conformal seed layer 128 can be in a range of about 50 A to about 500 A, and more preferably in a range of about lOOA to about 30 ⁇ A.
• the conformal and non- conformal seed layers may comprise the same material, or they may comprise different materials.
• copper is commonly used as a seed layer, a highly conductive silver (Ag) layer can also be used.
• Non-conformal seed layer 126 and conformal seed layer 128 may comprise, for example, a material selected from Cu, Ag, or alloys comprising one or more of these metals.
• substrate 110 is placed in a copper electroplating bath, and electroplating is carried out in accordance with any one of a number of methods that are well known to those of ordinary skill in the art to deposit a thickness of copper sufficient to fill patterned opening 116, with some excess, and to cover field 114 surrounding opening 116.
• excess plated copper overlying opening 116 and field 114 of insulating layer 112, as well as seed layers 126 and 128 and barrier layer 118 overlying field 114 are removed using any one of a number of techniques that are well known to those of ordinary skill in the art, for example, using a mechanical polishing or a chemical mechanical polishing (CMP) technique.
• CMP chemical mechanical polishing
• removal techniques such as wet or dry etching techniques may also be used to remove excess plated copper overlying opening 116 and field 114, and to remove seed layers 126 and 128 and barrier layer 118 overlying field 114. It should be clear to those of ordinary skill in the art that removal may also be accomplished using a combination of techniques, including those identified above.
• FIG. 4 shows a cross-sectional view of the inventive structure of FIG. 3 after removing excess electroplated copper (or silver) 130 overlying opening 116 and field 114, and removing seed layers 126 and 128 and barrier layer 118 overlying field 114 surrounding opening 116.
• FIG. 4 shows a cross-sectional view of the inventive structure of FIG. 3 after removing excess electroplated copper (or silver) 130 overlying opening 116 and field 114, and removing seed layers 126 and 128 and barrier layer 118 overlying field 114 surrounding opening 116.
• FIG. 4 illustrates the filling of openings (trenches and vias) with electroplated copper (or silver) 130, as well as the lining of the bottom and sidewall surfaces of opening 116 by barrier layer 118 and seed layers 126 and 128. As shown in FIG. 4, all metallic layers were removed from field 114 of insulating layer 112 which surrounds embedded electroplated copper (or silver) interconnect 130.
• Example 2
• FIGs. 5 and 6 show scanning electron microscope ("SEM") photographs of a cross-section of a 0.10 ⁇ m wide trench having a Cu seed layer prepared in accordance with a preferred embodiment of the invention.
• SEM scanning electron microscope
• a pattern of trenches was formed in a SiO insulating layer.
• the trenches were about 0.10 ⁇ m wide and about 1.4 ⁇ m deep (thereby having an aspect ratio of about 14:1).
• a barrier layer (WNx) was deposited using a CVD technique.
• a relatively thin, conformal Cu seed layer was deposited using a CVD technique.
• the barrier layer and thin, conformal Cu seed layer is seen at 501 in FIG. 6.
• the combined thickness of the barrier and the CVD Cu seed layer was about 500 A on the field, and about 400-500 A on the sidewalls and bottom of the trenches.
• a non-conformal PVD Cu seed layer having a thickness of about 1,400 A (on the field) was deposited by sputtering.
• the non conformal PVD Cu seed layer was applied in two steps and is seen at 510 in FIG. 6. The end result, as shown in FIGs. 5 and 6, was a combined thickness (including the barrier and the Cu seed layers) of only about 400-500A on the sidewalls and bottom of the trench (with excellent continuity and uniformity there), and about 1,900A on the field, without pinching-off of the trench.
• FIG. 5 shows the cross-section with a tilt of about 30° and an enlargement of 20,000X (thus providing also a partial view of the top surface)
• FIG. 6 shows the same cross-section with an enlargement of 40,000X and without a tilt.
• trenches -0.10 ⁇ m wide and -1.4 ⁇ m deep were formed in a SiO insulating layer.
• a barrier layer (WNx) was deposited using a CVD technique.
• a relatively thin, conformal Cu seed layer was deposited using a CVD technique.
• the combined thickness of the barrier layer and the CVD Cu layer was -500 A on the field, and -400- 500 A on the sidewalls and bottom of the trenches.
• a non-conformal PVD Cu seed layer having a thickness of -500 A (on the field) was deposited by sputtering.
• a relatively thin (“Flash”) PVD seed layer can be deposited first, followed by a conformal CVD or electroless seed layer, and finally followed by a (relatively thick) PVD seed layer to produce three separately deposited seed layers.
• Adhesion of a metallo-organic CVD (MOCVD) deposited Cu seed layer to underlying barrier layer is rather poor, and may not be adequate for use in devices when chemical mechanical polishing (CMP) processing follows Cu plating.
• CMP chemical mechanical polishing
• MOCVD Cu layer is deposited directly over a barrier layer containing a refractory metal, further problems arise. In particular, the morphology, uniformity, and electrical resistivity of the MOCVD Cu layer may not be adequate for use in devices. It is believed that these problems are due to the high affinity of the refractory metal in the barrier layer to oxygen and/or carbon atoms.
• the refractory metal of the barrier layer spontaneously reacts with carbon or oxygen containing species (from the organic part of the metallo-organic compound) to form an oxide, carbide, or a mixed oxide- carbide interfacial layer between itself and the depositing Cu.
• carbon or oxygen containing species from the organic part of the metallo-organic compound
• Such an intermediate layer adversely impairs the adhesion of the MOCVD Cu layer.
• Cu (as well as other noble metals) does not adhere well to oxide or carbide layers, and requires a clean metal -to-metal bond in order to adhere well to another metal.
• the oxide, carbide, and/or oxide-carbide interfacial layer impairs proper nucleation of the
• MOCVD Cu on the refractory metal barrier layer. This adversely affects the morphology, uniformity, and resistivity of the deposited MOCVD Cu seed layer.
• At least an initial stage of CVD Cu deposition is carried out utilizing high purity, inorganic Cu compounds (precursors), such as, for example and without limitation, chlorides or fluorides, which do not contain oxygen or carbon atoms.
• precursors such as, for example and without limitation, chlorides or fluorides, which do not contain oxygen or carbon atoms.
• the resulting clean metal-to- metal interface between a barrier layer containing a refractory metal and the depositing copper ensures good adhesion, morphology, uniformity, and low electrical resistivity of the CVD Cu layer.
• the entire CVD Cu layer can be deposited using the inorganic precursors.
• only the initial stage of the CVD Cu is carried out using inorganic precursors, switching later to an MOCVD Cu deposition process, to form the rest of the CVD Cu layer.
• a first, relatively thin, "Flash” PVD seed layer is deposited to enhance adhesion to the barrier layer and/or to improve grain morphology and uniformity of a subsequently deposited CVD seed layer.
• conformal and non-conformal seed layers are deposited in an apparatus where the conformal and non-conformal seed layer deposition steps can be carried out without breaking vacuum, or without exposing the wafer to the atmosphere between the deposition steps.
• the apparatus may comprise two or more chambers, at least one chamber for deposition of the conformal seed layer, and at least another chamber for deposition of the non-conformal seed layer.
• the apparatus further comprises a chamber for deposition of the barrier layer, preferably by a CVD technique.
• the barrier layer may be deposited in a separate chamber or it may be deposited in one of the chambers used to deposit either the conformal, or the non-conformal, seed layers.
• FIG. 7 shows apparatus 7000 that is fabricated in accordance with a preferred embodiment of the invention.
• apparatus 7000 comprises cluster tool 70 which operates in accordance with input from controller 80 in a manner that is well known to those of ordinary skill in the art.
• cluster tool 70 includes input loadlock 71 and output loadlock 72.
• loadlocks 71 and 72 enable wafers to be inserted into and removed from cluster tool 70, respectively.
• FIG. 7 shows separate input and output loadlocks, it is also within the spirit and scope of the present invention to use a single loadlock for both input and output of wafers.
• cluster tool 70 comprises CVD barrier layer deposition chamber 76, PVD Cu seed layer deposition chamber 77, and CVD Cu seed layer deposition chamber 78.
• FIG. 7 shows several other processing, for example, processing chambers 75 and 79, which can be used for other processing steps that are well known to those of ordinary skill in the art, such as pre-cleaning, cooling, or as extra deposition chambers.
• FIG. 7 shows separate CVD chambers for depositing a barrier layer and Cu seed layers, it is also within the scope of the invention to deposit both types of layers in the same CVD chamber.
• Controller 80 is apparatus which is well known to those of ordinary skill in the art that is used to control the operation of cluster tool 70. As such, controller 80 determines the sequence and duration of movements and stays of wafer 74: (a) to and from loadlocks 71 and 72; and (b) to and from the various processing chambers 75-79.
• controller 80 controls the specific process sequence and process parameters for operation of the various ones of processing chambers 75-79, sometimes referred to in the art as "recipes.”
• controller 80 controls the duration of the sputter deposition, the background pressure, the sputtering gas (such as Argon) pressure and flow rate, the cathodic voltage and power, and/or bias voltage applied to the wafer.
• controller 80 performs these functions in accordance with specific recipes which are data structures that dictate the operation of controller 80 software.
• the data structures are typically stored on computer readable media that are input to controller 80 under the control of operation software, which operation software itself is typically stored on a computer readable medium.
• recipes are input to controller 80 to cause it to control cluster tool 70 to process wafers in the manner described above to deposit a Cu barrier layer and Cu seed layers without breaking vacuum or exposing a wafer to the atmosphere.
• the apparatus comprises a chamber in which both conformal and non-conformal seed layers are deposited utilizing: (a) two or more distinct steps, wherein the deposition variables (or conditions or parameters) during the first step are suitable for the deposition of a substantially conformal (or a non-conformal) seed layer, and the deposition conditions during the second step are suitable for the deposition of a substantially non-conformal (or a conformal) seed layer; (b) wherein at least one of the deposition variables is varied (or ramped) continuously or gradually, thereby changing the nature of the seed layer from substantially conformal to substantially non-conformal, or vice versa; or (c) a combination of at least one distinct step of depositing a substantially conformal (or a non-conformal) seed layer and at least one gradual variation (or ramping) of at least one deposition variable towards a substantially non-conformal (or a conformal) seed layer, and vice versa.
• the nature of certain deposition techniques can be made more conformal, or less conformal, by varying the deposition parameters (or variables, or conditions). For example, increasing the (partial) pressure during ion plating and other PVD techniques, tends to increase scattering of the depositing atoms (or ions), thereby making the deposition more isotropic and conformal.
• biasing the substrate has a effect on the nature of the deposit. For example, in ionized metal plasma (IMP) and ion plating, increasing the (negative) bias voltage further accelerates positive ions (of the depositing metal) towards the substrate, thereby improving the filling of small openings.
• the higher (negative) bias also increases the removal rate (or back-sputtering) from the top corners of the openings and the field, thereby rendering the deposition to be more conformal.
• the nature of certain CVD techniques can be made less conformal, or more conformal, by changing the deposition variables. For example, increasing the substrate temperature tends to shift the deposition from a surface-reaction, rate-controlled deposition at low temperature, to a transport, rate-controlled deposition at higher temperature. As a result, increasing the substrate temperature tends to render the deposition to be less conformal. Conversely, decreasing the temperature, tends to render the deposition to be more conformal. Similarly, increasing the precursor and/or the reacting gas partial pressure (or flow rate) tends to shift the deposition to be a more surface-reaction, rate- controlled deposition, thereby tending to render the deposition to be more conformal.
• PECVD plasma variables in PECVD, such as the power density, may also have significant effects on the nature of the deposition.
• cluster tool 70 comprises the following chambers: a CVD deposition chamber for depositing a barrier layer (for example, Ta, TaN x , W, or WN X ); a PVD deposition chamber for depositing a PVD Cu seed layer; and a CVD deposition chamber for depositing a CVD Cu seed layer.
• a barrier layer for example, Ta, TaN x , W, or WN X
• PVD deposition chamber for depositing a PVD Cu seed layer
• CVD deposition chamber for depositing a CVD Cu seed layer.
• Single wafers are transferred in-situ in cluster tool 70, from one chamber to another, without exposing the wafers to the atmosphere prior to the deposition of the top Cu seed layer.
• the CVD barrier and the CVD Cu seed layers can be deposited in the same CVD chamber by using different gases and chemistries for the respective layers.
• cluster tool controller 80 would cause a deposition process such as the following to be carried out in accordance with a recipe specified, for example in the form of a data structure or software or program code: (a) (in accordance with a first portion of the data structure or a first portion of the software or computer code) introducing wafer 74 into CVD barrier layer deposition chamber 76 and depositing on wafer 74 a CVD barrier layer (about 200-400A thick) comprising TaN x or WN X ; (b) (in accordance with a second portion of the data structure or a first portion of software or computer code) transferring wafer 74 through transfer chamber 73, without exposing wafer 74 to the atmosphere, to PVD Cu seed layer deposition chamber 77 and depositing on wafer 74 a relatively thin (about 100-500 A) "Flash" PVD Cu layer;
• a three-step combination may include a first deposited CVD seed layer, followed by a relatively thick PVD seed layer, and finally followed by a second deposited CVD seed layer.
• Other combinations may comprise even more steps in the deposition of the seed layer.
• the three (or more) separately deposited seed layers may comprise the same metal or alloy or they may comprise, for example and without limitation, different materials chosen from Cu, Ag, or alloys comprising one or more of these metals.

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