WO2000045261A1 - Procede et dispositif de commande d'acces - Google Patents
Procede et dispositif de commande d'acces Download PDFInfo
- Publication number
- WO2000045261A1 WO2000045261A1 PCT/JP2000/000265 JP0000265W WO0045261A1 WO 2000045261 A1 WO2000045261 A1 WO 2000045261A1 JP 0000265 W JP0000265 W JP 0000265W WO 0045261 A1 WO0045261 A1 WO 0045261A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- access
- address
- management unit
- dram
- information
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
Definitions
- FIG. 5 is a block diagram partially showing the configuration of a conventional information processing apparatus, which is used for accessing a DRAM (Dynamic Random Access Memory) 120 from the CPU 160 or the first and second processing circuits 500 and 510. The related configuration is shown.
- DRAM Dynamic Random Access Memory
- the DRAM byte address designation register 141 is a register for writing the address of the DRAM that the CPU 160 wants to access.
- the DRAM read / write register 142 holds the data of the address written in the DRAM pipeline address designation register 141 or the data written in the address written in the DRAM byte address designation register 141.
- the access mode designation register 143 designates a method of accessing the DRAM 120.
- the DRAM end address variable designation bit 144 specifies 1 or 0 as to whether or not to continuously change the address written in the DRAM byte address designation register 141.
- the DRAM address increase Z decrease designation bit 145 designates, by 1 or 0, the force for continuously increasing or decreasing the address written in the DRAM byte address designation register 141.
- the access control device is further characterized in that, when another task or interrupt processing is activated when all of the plurality of access ports are used, the activated another task Alternatively, a save area for saving information stored in any one access port so that information regarding an access request for interrupt processing can be stored in any one access port, and any one of the above-mentioned one access port And evacuation / return means for evacuation of the information written in the evacuation area and restoring the evacuation information in the evacuation area to the access port.
- FIG. 4 is a flowchart schematically showing the operation of the access method according to the present embodiment. An access method according to the present embodiment will be described with reference to FIGS. 1 and 4.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Multi Processors (AREA)
- Storage Device Security (AREA)
- Memory System (AREA)
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/647,196 US6742089B1 (en) | 1999-01-27 | 2000-01-20 | Access controller and access method for controlling access from a CPU to a memory based on use states of plural access ports |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01887899A JP3525070B2 (ja) | 1999-01-27 | 1999-01-27 | アクセス制御装置及びアクセス方法 |
JP11/18878 | 1999-01-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000045261A1 true WO2000045261A1 (fr) | 2000-08-03 |
Family
ID=11983822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/000265 WO2000045261A1 (fr) | 1999-01-27 | 2000-01-20 | Procede et dispositif de commande d'acces |
Country Status (7)
Country | Link |
---|---|
US (1) | US6742089B1 (ja) |
JP (1) | JP3525070B2 (ja) |
KR (1) | KR100419682B1 (ja) |
CN (1) | CN1145101C (ja) |
ID (1) | ID27388A (ja) |
TW (1) | TW463130B (ja) |
WO (1) | WO2000045261A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003029967A (ja) * | 2001-07-17 | 2003-01-31 | Fujitsu Ltd | マイクロプロセッサ |
US20040128418A1 (en) * | 2002-12-30 | 2004-07-01 | Darren Abramson | Mechanism and apparatus for SMI generation |
JP4827469B2 (ja) * | 2005-09-08 | 2011-11-30 | パナソニック株式会社 | キャッシュメモリ解析方法、プロセッサおよび模擬情報処理装置 |
JP4699858B2 (ja) * | 2005-10-13 | 2011-06-15 | シャープ株式会社 | メモリ装置およびメモリ制御方法 |
JP4825810B2 (ja) * | 2005-10-26 | 2011-11-30 | パイオニア株式会社 | 情報記録装置、情報記録方法、情報記録プログラムおよび記録媒体 |
US8850103B2 (en) | 2009-08-28 | 2014-09-30 | Microsoft Corporation | Interruptible NAND flash memory |
EP2618552A1 (en) * | 2010-09-17 | 2013-07-24 | Konica Minolta Holdings, Inc. | Image forming device |
CN102789439B (zh) * | 2012-06-16 | 2016-02-10 | 北京忆恒创源科技有限公司 | 控制数据传输过程中的中断的方法与存储设备 |
FR3072233B1 (fr) * | 2017-10-10 | 2020-11-27 | Bull Sas | Procede de generation de requetes pour la segmentation de la surveillance d'un reseau d'interconnexion et materiel associe |
JP7240118B2 (ja) * | 2018-09-14 | 2023-03-15 | キヤノン株式会社 | 情報処理装置、その制御方法およびプログラム |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6220042A (ja) * | 1985-07-19 | 1987-01-28 | Fujitsu Ltd | メモリアクセスポ−ト管理装置 |
JPH02163834A (ja) * | 1988-12-16 | 1990-06-25 | Mitsubishi Electric Corp | マルチ・タスク処理方式 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61250749A (ja) * | 1985-04-30 | 1986-11-07 | Fujitsu Ltd | 主記憶アクセス制御方式 |
JP2574821B2 (ja) * | 1987-12-02 | 1997-01-22 | 株式会社日立製作所 | ダイレクトメモリアクセス・コントローラ |
KR940002595Y1 (ko) * | 1988-12-30 | 1994-04-21 | 주식회사 금성사 | Cpu보드상의 이중 포트 기억장치 회로 |
JP2553698B2 (ja) | 1989-03-28 | 1996-11-13 | 松下電器産業株式会社 | 時分割マルチタスク実行装置 |
US5371887A (en) * | 1989-09-05 | 1994-12-06 | Matsushita Electric Industrial Co., Ltd. | Time-shared multitask execution device |
JPH0415730A (ja) * | 1990-04-29 | 1992-01-21 | Fujitsu Ltd | シーケンスコントローラ |
US5875470A (en) * | 1995-09-28 | 1999-02-23 | International Business Machines Corporation | Multi-port multiple-simultaneous-access DRAM chip |
EP0768609B1 (en) * | 1995-10-16 | 2003-06-25 | Hitachi, Ltd. | Multimedia data transferring method |
US6314499B1 (en) * | 1997-11-14 | 2001-11-06 | Lucent Technologies Inc. | Non-preemptive memory locking mechanism in a shared resource system |
US6401176B1 (en) * | 1997-11-14 | 2002-06-04 | Agere Systems Guardian Corp. | Multiple agent use of a multi-ported shared memory |
-
1999
- 1999-01-27 JP JP01887899A patent/JP3525070B2/ja not_active Expired - Fee Related
-
2000
- 2000-01-20 US US09/647,196 patent/US6742089B1/en not_active Expired - Fee Related
- 2000-01-20 CN CNB008000786A patent/CN1145101C/zh not_active Expired - Fee Related
- 2000-01-20 WO PCT/JP2000/000265 patent/WO2000045261A1/ja active IP Right Grant
- 2000-01-20 ID IDW20002178A patent/ID27388A/id unknown
- 2000-01-20 KR KR10-2000-7010638A patent/KR100419682B1/ko not_active IP Right Cessation
- 2000-01-21 TW TW089101000A patent/TW463130B/zh not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6220042A (ja) * | 1985-07-19 | 1987-01-28 | Fujitsu Ltd | メモリアクセスポ−ト管理装置 |
JPH02163834A (ja) * | 1988-12-16 | 1990-06-25 | Mitsubishi Electric Corp | マルチ・タスク処理方式 |
Also Published As
Publication number | Publication date |
---|---|
JP2000222226A (ja) | 2000-08-11 |
KR20010024958A (ko) | 2001-03-26 |
TW463130B (en) | 2001-11-11 |
CN1145101C (zh) | 2004-04-07 |
CN1293778A (zh) | 2001-05-02 |
JP3525070B2 (ja) | 2004-05-10 |
ID27388A (id) | 2001-04-05 |
US6742089B1 (en) | 2004-05-25 |
KR100419682B1 (ko) | 2004-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2000045261A1 (fr) | Procede et dispositif de commande d'acces | |
JP2724078B2 (ja) | 二重化メモリの保守方法 | |
JPH0518143B2 (ja) | ||
JP3882461B2 (ja) | 記憶装置システム及びそのバックアップ取得方法 | |
JP2001290704A (ja) | マルチプロセス制御装置及びマルチプロセス制御方法 | |
JP3827068B2 (ja) | コントローラ | |
JP3772003B2 (ja) | メモリ管理システムおよびデータ管理方法 | |
WO2023226107A1 (zh) | 一种存储装置的数据备份方法、系统、电子设备及介质 | |
JP2701739B2 (ja) | プロセッサの系切替え方式 | |
JPS5924428B2 (ja) | 表示装置 | |
JPH053611B2 (ja) | ||
JP3463696B2 (ja) | オンラインガーベッジコレクション処理方法 | |
JP3364751B2 (ja) | データ転送システム | |
JP2001084179A (ja) | 自動バックアップシステム及び自動バックアッププログラムを記録した記録媒体 | |
JPH09319598A (ja) | 低コストシグナルマスク制御方式 | |
JP4009401B2 (ja) | ディスク制御装置及びプログラムを記録した記録媒体 | |
JPH08123725A (ja) | ライトバック式キャッシュシステム | |
JPH04296954A (ja) | メモリシステム | |
JP2001236241A (ja) | メモリ二重化制御方式 | |
JP2000003307A (ja) | メモリ制御装置及び制御方法 | |
JPH04285789A (ja) | 情報記憶装置及びそのリフレッシュ制御方法 | |
JPH0481934A (ja) | 情報処理装置 | |
JPH0476142B2 (ja) | ||
JP2000047943A (ja) | メモリ保護システム | |
JPH041376B2 (ja) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 00800078.6 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN ID KR SG US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020007010638 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 09647196 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 1020007010638 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1020007010638 Country of ref document: KR |