ID27388A - Pengatur pemasukan dan metoda pemasukan - Google Patents

Pengatur pemasukan dan metoda pemasukan

Info

Publication number
ID27388A
ID27388A IDW20002178A ID20002178A ID27388A ID 27388 A ID27388 A ID 27388A ID W20002178 A IDW20002178 A ID W20002178A ID 20002178 A ID20002178 A ID 20002178A ID 27388 A ID27388 A ID 27388A
Authority
ID
Indonesia
Prior art keywords
entry management
entering
methods
entering methods
entry
Prior art date
Application number
IDW20002178A
Other languages
English (en)
Inventor
Takao Inoue
Yasushi Imamura
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of ID27388A publication Critical patent/ID27388A/id

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Storage Device Security (AREA)
  • Memory System (AREA)
IDW20002178A 1999-01-27 2000-01-20 Pengatur pemasukan dan metoda pemasukan ID27388A (id)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01887899A JP3525070B2 (ja) 1999-01-27 1999-01-27 アクセス制御装置及びアクセス方法

Publications (1)

Publication Number Publication Date
ID27388A true ID27388A (id) 2001-04-05

Family

ID=11983822

Family Applications (1)

Application Number Title Priority Date Filing Date
IDW20002178A ID27388A (id) 1999-01-27 2000-01-20 Pengatur pemasukan dan metoda pemasukan

Country Status (7)

Country Link
US (1) US6742089B1 (id)
JP (1) JP3525070B2 (id)
KR (1) KR100419682B1 (id)
CN (1) CN1145101C (id)
ID (1) ID27388A (id)
TW (1) TW463130B (id)
WO (1) WO2000045261A1 (id)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003029967A (ja) * 2001-07-17 2003-01-31 Fujitsu Ltd マイクロプロセッサ
US20040128418A1 (en) * 2002-12-30 2004-07-01 Darren Abramson Mechanism and apparatus for SMI generation
JP4827469B2 (ja) * 2005-09-08 2011-11-30 パナソニック株式会社 キャッシュメモリ解析方法、プロセッサおよび模擬情報処理装置
JP4699858B2 (ja) * 2005-10-13 2011-06-15 シャープ株式会社 メモリ装置およびメモリ制御方法
WO2007049482A1 (ja) * 2005-10-26 2007-05-03 Pioneer Corporation 情報記録装置、情報記録方法、情報記録プログラムおよび記録媒体
US8850103B2 (en) 2009-08-28 2014-09-30 Microsoft Corporation Interruptible NAND flash memory
US8854647B2 (en) * 2010-09-17 2014-10-07 Konica Minolta Holdings, Inc. Image forming apparatus with time-divisional function execution
CN102789439B (zh) * 2012-06-16 2016-02-10 北京忆恒创源科技有限公司 控制数据传输过程中的中断的方法与存储设备
FR3072233B1 (fr) * 2017-10-10 2020-11-27 Bull Sas Procede de generation de requetes pour la segmentation de la surveillance d'un reseau d'interconnexion et materiel associe
JP7240118B2 (ja) * 2018-09-14 2023-03-15 キヤノン株式会社 情報処理装置、その制御方法およびプログラム

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61250749A (ja) * 1985-04-30 1986-11-07 Fujitsu Ltd 主記憶アクセス制御方式
JPS6220042A (ja) * 1985-07-19 1987-01-28 Fujitsu Ltd メモリアクセスポ−ト管理装置
JP2574821B2 (ja) * 1987-12-02 1997-01-22 株式会社日立製作所 ダイレクトメモリアクセス・コントローラ
JPH02163834A (ja) * 1988-12-16 1990-06-25 Mitsubishi Electric Corp マルチ・タスク処理方式
KR940002595Y1 (ko) * 1988-12-30 1994-04-21 주식회사 금성사 Cpu보드상의 이중 포트 기억장치 회로
JP2553698B2 (ja) * 1989-03-28 1996-11-13 松下電器産業株式会社 時分割マルチタスク実行装置
US5371887A (en) * 1989-09-05 1994-12-06 Matsushita Electric Industrial Co., Ltd. Time-shared multitask execution device
JPH0415730A (ja) * 1990-04-29 1992-01-21 Fujitsu Ltd シーケンスコントローラ
US5875470A (en) * 1995-09-28 1999-02-23 International Business Machines Corporation Multi-port multiple-simultaneous-access DRAM chip
EP0768609B1 (en) * 1995-10-16 2003-06-25 Hitachi, Ltd. Multimedia data transferring method
US6314499B1 (en) * 1997-11-14 2001-11-06 Lucent Technologies Inc. Non-preemptive memory locking mechanism in a shared resource system
US6401176B1 (en) * 1997-11-14 2002-06-04 Agere Systems Guardian Corp. Multiple agent use of a multi-ported shared memory

Also Published As

Publication number Publication date
WO2000045261A1 (fr) 2000-08-03
KR100419682B1 (ko) 2004-02-21
JP3525070B2 (ja) 2004-05-10
KR20010024958A (ko) 2001-03-26
JP2000222226A (ja) 2000-08-11
CN1145101C (zh) 2004-04-07
CN1293778A (zh) 2001-05-02
TW463130B (en) 2001-11-11
US6742089B1 (en) 2004-05-25

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