Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/01—Manufacture or treatment
  • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09G—POLISHING COMPOSITIONS; SKI WAXES
  • C09G1/00—Polishing compositions
  • C09G1/02—Polishing compositions containing abrasives or grinding agents
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
  • C09K3/00—Materials not provided for elsewhere
  • C09K3/14—Anti-slip materials; Abrasives
  • C09K3/1454—Abrasive powders, suspensions and pastes for polishing
  • C09K3/1463—Aqueous liquid suspensions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
  • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/32115—Planarisation
  • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/692—Electrodes
• • H10P52/403—
• • H10P95/062—
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
  • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
  • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/692—Electrodes
  • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer

Definitions

• the present invention relates to a chemical mechanical polishing (CMP) method and composition having applicability to the manufacture of ferroelectric random access memory capacitors, in which a stop layer is employed over the capacitor recess dielectric material to achieve the required planarization of the microelectronic device structure. It is also applicable to the fabrication of other integrated circuit structures, such as capacitor, resistor and inductor structures, which in utilizing multilayer geometries benefit from the inherently planarizing character of CMP.
• CMP chemical mechanical polishing
• FeRAMs FeRAMs. It is well known that these materials require electrodes made from noble metals or noble metal alloys such as Pt, Ir, Ir ⁇ 2, Pt-Ru, etc., and sub-micron patterning of both the noble metals or noble metal alloys such as Pt, Ir, Ir ⁇ 2, Pt-Ru, etc., and sub-micron patterning of both the noble metals or noble metal alloys such as Pt, Ir, Ir ⁇ 2, Pt-Ru, etc., and sub-micron patterning of both the noble metals.
• capacitor over plug is also known as a stack capacitor configuration.
• a barrier layer is needed to prevent oxidation of the plug and diffusion of the plug material (p-Si or W) through the noble metal bottom electrode.
• a trench capacitor which utilizes an enhanced surface area capacitor on the walls of a trench that is etched directly into doped silicon.
• the bottom electrode contact is not to a conductive plug (p-Si or W) but to the conductive substrate itself, though the requirements for the barrier are similar to the stack configuration.
• the memory cell's transistors are formed on the surface of wafer adjacent to the top of the trench capacitor.
• Ferroelectric capacitors planarized using chemical mechanical polishing are also more versatile for monolithic integration of ferroelectric memory or dynamic random access memory (DRAM) with logic IC ("embedded memory").
• DRAM dynamic random access memory
• logic IC embedded memory
• the 4-6 levels of metal needed for logic ICs place additional demands on the planarity of the underlying structures.
• Surface flatness is required in high resolution microlithography in order to stay within the aligner's specified depth of focus.
• a variety of semiconductor integrated circuits utilize passive (and in some cases active) filtering techniques that use resistors, capacitors, inductors. There is an accelerating trend toward the incorporation of multiple circuit functions in a single IC, whereas in the past different ICs were fabricated and connected externally on a circuit board, or by another packaging scheme.
• the polishing pad is pre-soaked and re-wet continuously with a slurry consisting of various particles suspended in a solution.
• the polishing particles range in size from 10 to 1000 nanometers.
• the suspension solution generally comprises a diluted base or acid for polishing oxide and metals, respectively.
• the wafers go through a post-CMP clean process in which the residual slurry, ground oxide/metal particles, and other potential contaminants are removed.
• DI de-ionized
• the two most common uses of CMP are oxide and metal (tungsten) plug planarization.
• the two most essential components of the CMP process are the slurry and the polishing pad.
• the polishing pad generally a polyurethane-based material, performs two primary functions.
• the polymeric foam cell walls of the pad aid in removal of the reaction products at the wafer surface and the pores within the pad assist in supplying the slurry to the pad/wafer interface.
• the conditioner was composed of a base material (metal), a diamond grit (for cutting), and a grit-bonding material (Ni plating). The plating bonded the diamond grit to the base material. The conditioner then effectively removed the top layer of the pad until excess, non-desired particles were removed and the nominal surface characteristics of the pad were restored. Although this approach allowed the same pads to be used for an extended period of time, it also resulted in other complications. Specifically, the physical bonding of the diamonds and base material ruptured relatively easily during the conditioning process. New methods of bonding as well as enhanced post-conditioning cleaning were pursued. When the diamonds were chemically bonded to the base material, the additional strength made grit detachment less prominent. The new bonding method allowed a factor of ten more wafers to be polished with the same conditioning pads as compared to the number that were able to be polished with the physically grit-bonded pads.
• Pad conditioning plays a larger role in planarization of oxide than in planarization of metals since metals tend to have a higher degree of hardness relative to the pad material.
• CMP critical dimensions, CD
• CMP tends to polish small, individual features faster than larger, more densely packed features.
• the oxide removal rate over features 15 microns in width is 60-80% greater than the oxide removal rate over features 60 microns in width.
• Denser or larger features tend to distribute applied load pressure over a larger area than smaller features. Since the removal rate and pressure are directly related in the direct contact mode, the removal rate decreases since the effective, local pressure decreases. The same principles apply when adjacent layers have a larger height contrast. "Taller" features will be planarized quicker, depending on other dimensions and the proximity to other devices.
• the purpose of the slurry is simple, yet understanding and modeling all the mechanical and chemical reactions involved is extremely difficult. Essentially, the surface of the material being polished is chemically altered to a softer composition, which is then mechanically removed by the pad and slurry abrasives. Thus, the slurry provides both chemical and mechanical forces in the CMP process. Oxide slurries are relatively new and largely experimental, yet the most common are ferric nitrate with an alumina abrasive and low pH. Some polysilicon and polyimide slurries exist, but are still in the prototype and developmental stages.
• Typical slurries incorporate an oxidizer or naturally dissolved oxygen additives to adjust pH levels, and either alumina or colloidal silica abrasives.
• the oxidizer changes the oxidation state of the metal and consequently produces metal ions.
• the top oxidized metal layer is more brittle and easily removed with the embedded abrasive particles. If the oxidation potential is too aggressive or the resulting metal compound too soluble, metal corrosion can occur as a result of wet etching. Alloys, galvanic actions, and precise oxidation states (oxidizers) are employed to slow down wet etching and limit the metal corrosion.
• oxide slurries can introduce various contaminants to the wafer surface.
• KOH-based slurries introduce a larger quantity of 200 nanometer particles than do the NH 4 OH slurries. That difference translates into a higher probability of scratches (e.g., up to 7 times greater, according to some studies) on the wafer surface when using the KOH slurries.
• NH 4 OH slurries also produce a lower concentration of mobile ions than KOH-based slurries, and leave residual films that are easier to remove than the residue from KOH slurries.
• KOH-based slurries afford advantages over NH 4 OH slurries.
• No ammonia smell exists when using KOH slurries KOH slurries are less prone to settle in cleaning tanks and CMP machines, and KOH slurries are more stabile in terms of pH, and less temperature dependent than NH 4 OH slurries.
• CMP has revolutionized global planarization technology, some significant problems exist.
• One of the major difficulties is in-situ measuring of the amount of material removed from the wafer surface. Due to inaccurate models, many results of CMP machines are difficult to reproduce and the machines themselves do not exhibit the ability for precise process control. This also leads to difficulty in analyzing feedback, or using in-situ measurements, to make adequate and appropriate process alterations to alleviate process complications.
• Some CMP slurry analyzers have been designed to measure and detect particle sizes in order to ascertain the abrasive characteristics of slurries more accurately.
• a few endpoint detection devices like a stylus profiler, have been developed to monitor removal rates as well. Such efforts will aid in more precisely controlling the entire CMP process, but the analysis techniques and instruments have not been developed to a state of high commercial precision.
• commercial CMP is the focus of substantial development effort, but in essence it continues to comprise the simple unit operations of:
• reaction of an exposed layer of material e.g., an insulating inorganic metal oxide and/or noble metal
• an exposed layer of material e.g., an insulating inorganic metal oxide and/or noble metal
• Illustrative CMP slurry compositions for insulating inorganic metal oxides include the compositions set out below:
• the art has directed improvements to alkali-containing solutions via aqueous or alcohol solutions of fluorinated silicon oxide particles, specifically the use of H 2 SiF 6 .
• the abrasive composition comprises Al 2 O 3 and/or SiO 2 aqueous solution.
• the abrasive composition comprises Al 2 O 3 and/or SiO 2 aqueous solution.
• the abrasive composition comprises Al 2 O 3 and/or SiO 2 aqueous solution.
• the slurry comprises a non-aqueous halogenated or pseudohalogenated reactant, and preferably includes a liquid organic ligand precursor (e.g., cyclic, acyclic, polycyclic, or aromatic compounds) which upon reaction with the halogenated or pseudohalogenated material form a metal-organic coordination complex which is heterocyclic.
• a liquid organic ligand precursor e.g., cyclic, acyclic, polycyclic, or aromatic compounds
• TE/FE/BE capacitor in a typical FeRAM are on the order of 100 nm.
• the maximum abrasive particle size should be much less than the minimum feature size in the device.
• Obstacles facing the commercial use of CMP for ferroelectric-based capacitors with noble metal electrodes include the relatively low chemical reactivity of many noble metals of interest, and the high degree of hardness of various of those metals, especially Ir and Rh. A large degree of mechanical removal of the noble metals and oxide films is necessary to achieve high removal rates, and the CMP process may result in physical or chemical damage to the capacitor layers. Physical damage includes disruption of the microstructure and long range order of the polycrystalline oxide lattice, which is principally responsible for the unique properties of the ferroelectric and high ⁇ oxides.
• Chemical damage, especially in the ferroelectric layer, may involve removal of specific cations, interdiffusion, de-oxygenation, or introduction of metallic contamination from the polishing media.
• capacitor structures entails CMP definition of the edge of the ferroelectric or high ⁇ layer, where relatively high E-fields are realized in these capacitor applications. Damage to the ferroelectric or metal layers will therefore have large effects on the functionality of the capacitor.
• the invention facilitates fabrication of microelectronic device capacitor structures in geometries that are only limited by the resolution of the lithography and the conformality of thin film deposition processes. Therefore, the polishing of 0.18 or even
• Trench capacitors of this type possess the advantage of having significant contribution of sidewall area, without the need for separate patterning steps for the top and bottom electrode, thus the method of the invention has large economic advantages. Additionally, the approach of the present invention has inherent advantages to protect the plug-barrier-bottom electrode interface from exposure to oxidation.
• the present invention relates to a method of forming a microelectronic device structure.
• Such method includes the steps of forming a capacitor recess dielectric material, depositing a bottom electrode layer, a ferroelectric layer, and a top electrode layer, to form a capacitor precursor structure.
• This capacitor precursor structure then is planarized by chemical mechanical polishing to yield the ferroelectric capacitor structure, e.g., a stack capacitor or a trench capacitor.
• One improvement of the invention involves forming the capacitor recess dielectric material to contain a stop layer at the planarization depth, wherein the stop layer has a substantially lower CMP removal rate than the dielectric insulating material and device structure materials under CMP conditions. In this manner, the removal of the dielectric insulating material and device structure materials by CMP under CMP conditions is terminated at the planarization depth by the stop layer.
• the method of the invention may comprise chemical mechanical polishing of a microelectronic device structure for planarization thereof, wherein:
• examples include perovskite nanocrystalline particles, such as those of barium strontium titanate; tantalum oxide, niobium oxide, or other donor dopants compensatory for O vacancies or acceptor impurity defects in the thin film capacitor material when inco ⁇ orated therein; refractory nitrides and carbides including cations that are beneficial to dielectric and/or ferroelectric properties of thin film capacitor material when inco ⁇ orated therein, such as tantalum nitride, tantalum carbide, niobium nitride, and niobium carbide; components that have hardness exceeding hardness of chemical byproducts existing at surface of the film being planarized; and reactant components that react with the material at the surface of the film being planarized, such as acids, bases and components that are effective to oxidize the material at the surface of the film being planarized);
• metal (electrode material) or dielectric (ferroelectric or high dielectric constant) material is removed either during or after the CMP planarization to create a local recess in the substrate, optionally followed by deposition of an insulating layer thereover, to thereby reduce the susceptibility of the device structure to short-circuiting or high leakage current behavior in use, with such metal removal comprising at least one of the steps of:
• an interlayer dielectric material e.g., Pb diffusion barrier layer for PZT device structures, Bi diffusion barrier layer for SBT device structures, and SiO 2 diffusion barrier layer for BST device structures
• isotropic dry etching of the device structure e.g., Pb diffusion barrier layer for PZT device structures, Bi diffusion barrier layer for SBT device structures, and SiO 2 diffusion barrier layer for BST device structures
• thermal annealing of the device structure after CMP planarization e.g., by conventional oven processing, or by rapid thermal annealing (RTA), preferably conducting such thermal annealing in the presence of oxygen to facilitate correction of oxygen stoichiometry in the thin film capacitor material and/or other device structure oxide layers;
• noble metal electrode material is removed by a CMP composition
• a CMP composition comprising component(s) selected from the group consisting of:
• silica silica, alumina, titania, silicon carbide, diamond, ceria, perovskite nanocrystalline particles, dopant materials of the above-described types, and mixtures of the foregoing;
• reactive components reactive with the noble metal electrode material to form solid and/or ionic products having a lower hardness than the noble metal electrode material itself (e.g., nitrides, sulfides, halides, oxides, hydrated oxides, etc. of the noble metal), such reactive components including species such as H 2 O 2 , K 3 Fe(CN) 6 , K 3 Fe(C 2 O 4 ) 3 , Fe(C 2 H 3 O 2 ) 3 , Fe(NO 3 ) 3 , Fe 2 (SO 4 ) 3 , Fe(OH) 3 , (NH 4 ) 3 Fe(CN) 6 , (NH 4 ) 3 Fe(C 2 O 4 ) 3 , KC1, KBr, KI, FeCl 3 , FeBr 3 , Fel 3 , FeCl 2 , FeBr 2 , and Fel 2 .
• reactive components including species such as H 2 O 2 , K 3 Fe(CN) 6 , K 3 Fe(C 2 O 4 ) 3 ,
• a high selectivity between metal polishing and oxide polishing is achieved by conducting the CMP operation in accordance with the relationship:
• pressure x platen speed 300 psi ⁇ m wherein the pressure is measured in pounds per square inch, and the platen speed of the CMP polishing pad is measured in revolutions per minute.
• Still another aspect of the invention relates to a method of fabricating an integrated circuit structure including conductive transmission lines, comprising:
• the transmission-enhancement material depositing the transmission-enhancement material over the conductive transmission lines of the conductor material, to encapsulate the conductive transmission lines in the transmission-enhancement material, whereby the transmission-enhancement material enhances the inductance and/or capacitance of the conductive transmission lines, relative to a corresponding integrated circuit structure lacking such transmission-enhancement material.
• a still further aspect of the invention relates to an integrated circuit structure including conductive transmission lines encapsulated in a transmission-enhancement material selected from the group consisting of high magnetic permeability materials (e.g., MgMn ferrites and/or MgMnAl ferrites) and high permittivity materials (e.g., barium strontium titanate, lead zirconium titanate, titanium oxide, tantalum oxide, etc.).
• a transmission-enhancement material selected from the group consisting of high magnetic permeability materials (e.g., MgMn ferrites and/or MgMnAl ferrites) and high permittivity materials (e.g., barium strontium titanate, lead zirconium titanate, titanium oxide, tantalum oxide, etc.).
• Figures 1A through 1H show a schematic process flow for patterning sub-micron ferroelectric capacitors in a stack capacitor configuration using CMP in accordance with the present invention, with CVD of the ferroelectric, electrode and barrier layers being desirable for feature sizes below 1 micron.
• Figures 2A-2B show a schematic representation of a top edge region of the capacitor structure of Figure IE, showing the details of the structure.
• Figures 3A-3D show a schematic process flow for patterning sub-micron transmission lines using CMP in accordance with the present invention.
• the method of the present invention permits the formation of a microelectronic device structure including forming a capacitor recess dielectric material and device structure materials on a substrate, in which the device structure materials are removed during processing to a planarization depth therein by chemical mechanical polishing (CMP).
• CMP chemical mechanical polishing
• the capacitor recess dielectric material is formed to contain a stop layer at the desired planarization depth in the dielectric insulating material.
• the stop layer has a substantially lower CMP removal rate than the dielectric insulating material under CMP conditions, so that the removal of the device structure materials and dielectric insulating layer material by CMP under CMP conditions is terminated at the planarization depth by the stop layer.
• the capacitor recess dielectric in such method may include a material species such as Al 2 O 3 , Ta 2 O 5 , ZrO 2 , TiO 2 , SiO 2 , Si 3 N 4 , TiAlO 4 , boron-doped SiO 2 , or phosphorus-doped SiO 2 , mixtures of those materials, etc.
• a material species such as Al 2 O 3 , Ta 2 O 5 , ZrO 2 , TiO 2 , SiO 2 , Si 3 N 4 , TiAlO 4 , boron-doped SiO 2 , or phosphorus-doped SiO 2 , mixtures of those materials, etc.
• the device structure materials may include one or more materials such as multicomponent oxide capacitive materials, ferroelectric materials, noble metals, noble metal alloys, polysilicon, tungsten, titanium nitride, titanium silicon nitride, titanium aluminum nitride, silicon carbide, and/or multicomponent oxide magnetoresistive materials.
• the device structure may comprise a ferroelectric material such as lead zirconium titanate, strontium bismuth tantalate, bismuth titanate, etc.
• the device structure alternatively may include a multicomponent oxide capacitive material such as barium titanate, barium strontium titanate, etc., or a multicomponent oxide magnetoresistive material such as lanthanum calcium manganate.
• a multicomponent oxide capacitive material such as barium titanate, barium strontium titanate, etc.
• a multicomponent oxide magnetoresistive material such as lanthanum calcium manganate.
• the stop layer may be formed of a material such as Al 2 O 3 , Si 3 N 4 , TiN, TiSiN, TiAIN, I1 2, SiC or combinations thereof.
• the dielectric such as Al 2 O 3 , Si 3 N 4 , TiN, TiSiN, TiAIN, I1 2, SiC or combinations thereof.
• the insulating material comprises SiO 2 and the stop layer is formed of Si 3 N 4 .
• the electrode materials comprise Ir
• the ferroelectric material is lead zirconate titanate
• the conductive barrier layer is TiAIN.
• the conductive barrier layer may serve as a stop layer for the CMP process.
• the ratio of the stop layer CMP removal rate to the dielectric insulating material CMP removal rate under said CMP conditions is suitably less than 0.20, and more preferably is less than 0.01.
• the microelectronic device structure that is fabricated in the practice of the invention may be of any suitable type, and may for example comprise a ferroelectric capacitor structure formed by sequentially depositing a bottom electrode layer, a ferroelectric layer and a top electrode layer on a base structure including the substrate and the capacitor recess dielectric material, to form a capacitor precursor structure, and planarizing the capacitor precursor structure by CMP to yield said ferroelectric capacitor structure.
• the capacitor structure may comprise a stack capacitor or alternatively a trench capacitor.
• the ferroelectric capacitor device fabrication method of the present invention is preferably carried out without dry etching of the electrode layers or dry etching of the ferroelectric layer, and is applicable to fabrication of ferroelectric capacitors having a
• the device structure material may form a capacitor structure including a top electrode, a ferroelectric layer, and a bottom electrode, with the stop layer underlying the bottom electrode as a conductive barrier layer for the capacitor structure.
• the CMP conditions applicable to the practice of the invention may include any suitable slurry compositions, pressure and temperature conditions, as will be readily determinable within the skill of the art and without undue experimentation.
• the CMP conditions may for example comprise mechanical polishing with a slurry including an oxide abrasive material, e.g., alumina and/or ceria, and chemical additives for removal of the top electrode layer, ferroelectric layer and bottom electrode layer in the case of a ferroelectric capacitor structure.
• the CMP operation may be carried out with polishing media containing elements that are used as dopants and/or modifiers in the film being removed, so that these components of the CMP composition become inco ⁇ orated in the film left at the conclusion of CMP processing, and beneficially affect the residual film on the substrate, relative to the use of a CMP composition lacking such components therein.
• the polishing media may be formulated to contain perovskite nanocrystalline particles similar in composition to the film being removed, or including constituents that would have a positive effect on the dielectric material layer if the cations of the perovskite material were inco ⁇ orated in the dielectric film material, either as dopants or modifiers.
• perovskite nanocrystalline particles similar in composition to the film being removed, or including constituents that would have a positive effect on the dielectric material layer if the cations of the perovskite material were inco ⁇ orated in the dielectric film material, either as dopants or modifiers.
• Such compounds may for example include BaSrTiO 3 , and related materials, which contain species that are known to be beneficial to the properties of the many other perovskites when inco ⁇ orated therein in small concentrations.
• Polishing media may be employed in the CMP operation, which are comprised of oxides such as Ta 2 O 5 or Nb 2 O 5 . Inco ⁇ oration of those metal elements improve the properties of many perovskite oxides, especially those in the PZT family, which are prone to O vacancies, which in turn result in degraded electrical properties. Donor dopants may be employed to compensate for O vacancies as well as defects due to acceptor impurities, so that the dopant species are inco ⁇ orated in the film being subjected to CMP processing.
• Refractory nitrides or carbides likewise may be employed in the CMP medium, which contain cations as described above. Examples include Ta nitride, Ta carbide, Nb nitride and Nb carbide.
• the CMP medium may be formulated to have hardness exceeding the hardness of the chemical byproducts at the film surface of the material undergoing CMP, yet which will also "stop" at polish stop layers such as binary or ternary nitride-carbide barriers, as described in copending U.S. patent application no. 09/141,971 filed August 28, 1998 in the names of Peter C. Van Buskirk and Michael W. Russell for "Ternary Nitride-Carbide Barrier Layers," the disclosure of which hereby is inco ⁇ orated herein by reference in its entirety.
• CMP media with conventional slurries, including liquid media that are typically used to react at the thin film surface, as for example acids, bases and oxidizers, may be usefully employed in CMP compositions according to the present invention.
• metal or dielectric (ferroelectric or high ⁇ ) layer may be carried out, either during or after the CMP step, to create a local recess.
• This approach removes the damaged area, or makes the presence of a damaged region irrelevant. In this case the possibility of electrical shorts or high leakage current in the areas affected will be reduced.
• Such an approach may be accomplished in a several ways.
• inert ion bombardment may be carried out after CMP is complete and before deposition of the interlayer dielectric (e.g., a Pb or Bi diffusion barrier for PZT and SBT; SiO 2 for BST). Bombardment will preferentially remove lighter elements such as Zr and Ti compared to Ir or Pt, for example, and residual Pb may be removed as PbO at elevated temperatures such as > 600°C.
• the inert ions for such bombardment technique may be of any suitable type, which are non-reactive to the material being removed. Examples include argon, helium, xenon, etc.
• isotropic dry etching may be carried out, as more fully described in co-pending U.S. patent application no. U.S. Patent Application No. 09/093,291 filed June 8, 1998 in the names of
• the present invention also contemplates the formulation of CMP slurry media to achieve significant removal rates of noble metals via chemical mechanical polishing.
• Suitable CMP slurry media for the polishing of iridium and other noble metals are more fully described in co-pending U.S. patent application no. U.S. Patent Application No.
• Polishing media for noble metals may contain conventional abrasive particles such as silica, alumina, titania, silicon carbide, diamond, or ceria; perovskite nanocrystalline particles, or dopant metal particles of the type as described earlier hereinabove, or mixtures of two or more of the foregoing.
• the slurry chemicals react with the metal surface and form either solid and/or ionic products.
• Enhanced removal rate of the metal film is accomplished in instances where this surface layer is more easily removed by abrasion than the original metal surface.
• the surface layer may be a nitride, sulfide, halide, or combination thereof, but is most likely an oxide or hydrated oxide layer that is softer than the underlying noble metal film.
• Native oxide and hydroxide films may form in exposure to various CMP slurries depending upon the solution pH, electrochemical potential of the metal in the slurry environment, and the kinetics of the various reactions that are thermodynamically favorable for a given set of CMP processing conditions. Control of the solution pH and electrochemical potential via the use of buffering agents may be desirable in order to facilitate a balance between chemical etching and material removal by mechanical abrasion.
• high selectivity between metal and oxide polishing may be achieved by conducting the CMP operation under conditions at which the parameter (pressure x platen speed) has a value of less than 300 psi rpm, wherein pressure of the CMP polishing pad is measured in psi, and the platen speed of the polishing pad is measured in ⁇ m units.
• a substrate 10 (typically formed of silicon, although other substrate materials of construction, such as GaAs, are possible) is provided with transistors and other circuitry (not shown) already fabricated below the wafer surface 12, according to conventional fabrication techniques.
• the silicon circuitry is covered with an insulating layer (isolation dielectric) 14 such as Ti ⁇ 2, Si ⁇ 2, Si3N4, boron- or
• Vias 16 to the Si circuitry are opened using photolithography and dry-etching, a plug 18 of suitable material, such as p-Si or W, is formed in the vias using CVD, and the surface 20 is planarized using dry etching or CMP.
• suitable material such as p-Si or W
• Si3N4 boron- or phosphorus-doped Si ⁇ 2, etc., is formed over the surface of the plugs
• isolation dielectric 14 using CVD, sputtering or wet deposition methods.
• the isolation layer and the capacitor recess dielectric may be fabricated from the same material.
• capacitor recesses 24 are formed in the surface of the insulating layer 22 using photolithography and dry-etching.
• the top surface of the conductive plug 26 may then be sputter etched or heat treated to ensure a clean surface prior to conductive barrier deposition in step D.
• the conducting and insulating layers that will comprise the capacitor layers are deposited in step D ( Figure ID).
• the layers include (in the sequence they would be deposited in): a conductive barrier layer 28, the bottom electrode 30 (BE), the ferroelectric layer 32 (FE), the top electrode 34 (TE), and the dielectric insulating layer 35.
• the conductive barrier layer may be TiN, TiSiN, TiAIN, Ir ⁇ 2, SiC or some other
• the conductive barrier layer may also be comprised of a Ti layer that is first deposited to improve contact of the barrier to the plug.
• the BE and TE layers are typically noble metals such as Pt or Ir, or alloys of similar materials. In some instances, TE need not be a noble metal, since it does not need to withstand the highly oxidizing deposition environment.
• the FE layer material is typically PZT or SBT, but it may be bismuth titanate or some other ferroelectric thin film composition. Alternatively it may be a similar multicomponent oxide such as BST for high capacitance, or LaCaMnO ⁇ for
• the barrier must cover the sidewall in order to make good adhesion between the BE and the capacitor recess dielectric, because excellent mechanical robustness is needed for the polishing in step E.
• the BE must cover the sidewall to achieve adequate thickness for electrical continuity if the sidewall part of the structure is to be used for the chosen application.
• Another constraint is that both the conductive barrier and the BE will together serve as a Pb or Bi diffusion barrier when PbZrTiO 3 or SrBi 2 Ta 2 O 9 are the dielectrics, and that function also requires adequate sidewall coverage of those layers.
• step E the film stack is planarized using CMP which forms the 3 dimensional capacitors in the capacitor recesses.
• the CMP process is comprised of mechanical polishing with a slurry that typically contains an oxide abrasive harder than the materials being removed, such as alumina, ceria, etc., with chemical additives present to promote selective removal of the dielectric insulating layer, TE, FE, BE and barrier, relative to the capacitor recess dielectric.
• a preferred embodiment is to utilize a CMP process having a high selectivity between the electrode metal and the barrier layer, thereby using the barrier layer 28 as an intrinsic stop layer for the CMP process.
• a third alternative is to fabricate the entire capacitor recess dielectric of a suitable CMP stop layer material, and in that way there will be thickness of the stop layer even in cases where the selectivity of the CMP process is low with respect to the stop layer removal rate.
• Ir may require a different CMP process than PZT, for example.
• Ir removal rates between 20-50 nm/min. have been demonstrated.
• Most CMP processes utilize a second stage polish that removes microscratches and/or corrosion product(s) that are present on the wafer surface.
• a post-CMP anneal in an oxidizing or inert environment may be carried out if required to remove physical or chemical damage to the ferroelectric film that was subjected to mechanical and chemical agitation during its partial removal by CMP.
• Passive endpoint detection utilization of high selectivity interfaces is easily integratable and is preferred over the use of expensive metrology equipment.
• Step F involves sequentially depositing an insulating passivation layer 36 and an inter-level dielectric (ILD) 38 over the capacitors that were formed in the previous step.
• This barrier is deposited using CVD, sputtering or wet deposition methods, and its pu ⁇ ose is to prevent undesirable chemical reactions and interdiffusion between the top edge of the ferroelectric film or electrodes and the overlying ILD layer that typically contains Si or Si ⁇ 2- PZT and SBT in particular contain the highly
• the passivation layer may be Ti ⁇ 2, Z1 2, a2 ⁇ 5, Si3N4 or other similar dielectric materials that
• a diffusion barrier 42 of a material such as TiN, TiAIN, WN or other suitable material is deposited using CVD or sputtering, and metallization 44 is deposited over that barrier, in order to conformally fill the via.
• the metallization may be either CVD-applied W or Al that is sputtered at high temperatures or reflowed, or Cu, or Al-Cu alloys, or other conductive materials.
• the metallization is then patterned using photolithography and dry-etching.
• a substrate is utilized that may for example be formed of silicon, although other materials such as GaAs are potentially usefully employed, with transistors and other circuitry fabricated in the wafer surface.
• the substrate may be p-type, with no transistors fabricated in it at the time of capacitor formation.
• an insulating passivation layer and an inter-level dielectric (ILD) layer are sequentially deposited over the capacitors formed in the previous step. Vias then are opened in the barrier comprising the insulating passivation layer and ILD layer using photolithography and dry-etching.
• a diffusion barrier layer of a material such as TiN, TiAIN, WN or another suitable material is deposited using CVD or sputtering
• the barrier layer deposited previously is patterned using dry etching or CMP.
• Vias are opened to doped regions formed previously and p-Si or other suitable conductor is deposited and patterned to form part of the circuitry for the memory cell.
• Dielectric isolation material is then formed over the patterned p-Si word lines and plate, vias are opened to the transfer transistor (doped Si regions) and the bit line is formed by deposition and patterning of Al with suitable barrier layers at the Si interface.
• Figure 2 A shows a magnified view of the device structure of Figure IE after CMP has been carried out.
• the CMP operation may result in the recessing of electrode layer edges forming the recess gaps 36 in relation to the otherwise planarized surface.
• an insulating layer 39 may be deposited over the device structure, as shown in Figure 2B.
• An insulating layer such as TiO 2 or Ta 2 O 5 may be used in the case of PZT or SBT dielectrics, respectively, to afford resistance to Pb or Bi diffusion. Standard interlayer dielectric processing and metallization can follow. Recess of the damaged dielectric is an alternative resultant condition of the CMP operation, and can be correspondingly dealt with, by forming an insulative layer over the dielectric material.
• chemical mechanical polishing is used to pattern conductive lines.
• the self-inductance of the lines may be increased by embedding them in a high magnetic permeability material.
• permeability is quantitatively complex; the real part ⁇ ' is dispersive (resulting in a phase
• Ferrites are quaternary (or higher oxidative state) metal oxide compounds which exhibit
• ferrites with low ⁇ " in the microwave region examples include MgMn ferrites
• Mg x Mn,. x Fe 2 O 4 MgMnAl ferrites
• the magnetic and electrical resistance properties of thin films of these materials may be further engineered by modifying grain size, Fe content, etc.
• parasitic capacitance may be increased by embedding the transmission line in a material with high permittivity, ⁇ .
• Candidates for the high ⁇ film include BaSrTiO 3 , paraelectric
• FIG. 3 A shows a substrate 10, with a conductive via 18, which is connected to transistors and other buried circuitry (not shown) already fabricated below the wafer surface.
• Recesses 24 are opened in the recess dielectric by wet or dry etching. Dry etching is preferred for feature sizes below about 1 micron.
• the layout of these recesses correspond to the pathways intended for the conductors, and vertical holes may be fabricated in an adjacent lithography-etch step, in order to make contact to conductors or other subsurface structures in the substrate.
• the recesses are filled sequentially by a high permeability layer 46, followed by a conductor 48, using conventional methods for deposition of those layers, such as for example, sputtering, evaporation, CVD, laser ablation, etc.
• layer 46 may also comprise a barrier layer (not shown) in order to prevent chemical interactions or diffusional interactions with the recess dielectric.
• subsequent metal layers may be formed with or without the inductance-enhancing high ⁇ layers, by using the same fabrication method described herein.
• Resistors may be correspondingly formed, by a damascene process utilizing suitable materials, e.g., Ta or TaN, which have fairly low temperature coefficients of resistance. In general it will be advantageous to form inductors, capacitors and resistors together in an integrated circuit using these techniques.

Landscapes

• Engineering & Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Organic Chemistry (AREA)
• Manufacturing & Machinery (AREA)
• Materials Engineering (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Nanotechnology (AREA)
• Mathematical Physics (AREA)
• Theoretical Computer Science (AREA)
• Crystallography & Structural Chemistry (AREA)
• Semiconductor Memories (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Mechanical Treatment Of Semiconductor (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=22741982

Family Applications (1)

Country Status (5)

Cited By (10)

Families Citing this family (108)

Citations (3)

Family Cites Families (7)

• 1998
  • 1998-11-25 US US09/200,499 patent/US6346741B1/en not_active Expired - Lifetime
• 1999
  • 1999-11-23 EP EP99962839A patent/EP1133792A4/en not_active Withdrawn
  • 1999-11-23 JP JP2000584527A patent/JP5128731B2/ja not_active Expired - Lifetime
  • 1999-11-23 WO PCT/US1999/027754 patent/WO2000031794A1/en not_active Ceased
  • 1999-11-23 KR KR1020017006595A patent/KR20010089510A/ko not_active Withdrawn

Patent Citations (3)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events