WO1997035341A1 - Dispositif de stockage a semi-conducteur et sa production - Google Patents

Dispositif de stockage a semi-conducteur et sa production Download PDF

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Publication number
WO1997035341A1
WO1997035341A1 PCT/JP1996/000685 JP9600685W WO9735341A1 WO 1997035341 A1 WO1997035341 A1 WO 1997035341A1 JP 9600685 W JP9600685 W JP 9600685W WO 9735341 A1 WO9735341 A1 WO 9735341A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
electrode
capacitor
upper electrode
etching
Prior art date
Application number
PCT/JP1996/000685
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English (en)
Japanese (ja)
Inventor
Takao Kumihashi
Yasushi Goto
Toru Kaga
Kenichi Shoji
Masahiro Moniwa
Natsuki Yokoyama
Tokuo Kure
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/000685 priority Critical patent/WO1997035341A1/fr
Priority to JP53333997A priority patent/JP3666877B2/ja
Priority to TW085115005A priority patent/TW312832B/zh
Publication of WO1997035341A1 publication Critical patent/WO1997035341A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Definitions

  • the present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) or a domain-inverted nonvolatile memory suitable for a large-scale integrated memory.
  • DRAM dynamic random access memory
  • a high-dielectric insulating film such as Ta 2 0 5 and BST as a capacitor insulating film.
  • a ferroelectric insulating film such as PZT is used as a capacitor insulating film, a nonvolatile memory using spontaneous polarization can be obtained. Since ferroelectric substances have extremely large relative dielectric constants of hundreds to thousands, they are also effective as a capacitor insulating film of Dynamitsu Random Access Memory ⁇ High dielectric insulating film / ferroelectric insulating film
  • the selection of the electrode material becomes important. This is because if the electrode material is oxidized during the formation of the insulating film to form an insulator having a low dielectric constant, the capacity of the capacitor is reduced.
  • Japanese Patent Application Laid-Open No. 5-89662 discloses a technique of performing etching while suppressing Pt re-adhesion using a Ti mask.
  • Japanese Patent Laid-Open No. 4-159679 discloses a technique for changing the area of the upper electrode and the lower electrode, or processing the end of the strong dielectric insulating film obliquely to eliminate the distortion of the film thickness change due to the polarization reversal. It is disclosed in the official gazette.
  • the side wall adhesion film 113 mainly composed of the electrode material adheres to the side walls of the mask 112, the upper metal electrode 111, the capacitor insulating film 109, and the lower metal electrode. This is remarkable when Pt or the like which is hardly oxidized is used as the electrode material.
  • the fact that it is difficult to oxidize means that it is difficult to change to a volatile substance by a chemical reaction, and the electrode material is mainly etched by physical sputtering. This sputtered electrode material adheres to the side walls. Oxide becomes conductor
  • the etching reaction product has low volatility, so that the sidewall adhesion film 113 is also formed.
  • This side wall adhesion film 113 must be removed because it causes a short circuit of the capacitor.
  • wet cleaning using an acid or the like has a problem that the capacitor insulating film is deteriorated.
  • the proposed technology uses the fact that the etch rate in dry etching varies depending on the incident angle of ions, and removes side wall deposits on the electrode material by self-cleaning during dry etching. That is.
  • the principle of this self-cleaning is shown in FIG.
  • the etch speed depends on angle 0.
  • the deposition rate is aR (0).
  • the etch rate of the deposited film on the side wall is R (0).
  • the etch rate R ( ⁇ ) on the side wall needs to be higher than the vertical thickness aR (O) / cos0 of the deposited film.
  • Figure 31 shows an improved capacitor structure based on the above findings.
  • the semiconductor memory device S shown in FIG. 31 is a cross-sectional view of a main part at the stage when a capacitor of a semiconductor memory is formed.
  • an element isolation region 102 is first formed on a semiconductor substrate 101.
  • an M0S transistor including the gate electrode 104 and the diffusion layer 105 is formed.
  • a plug 106 is formed in the through hole of the interlayer insulating layer 105 by using CVD and dry etching.
  • a barrier layer 107, a lower metal electrode 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed by dry etching using a mask and a mask 112 of each electrode.
  • the mask 112 is previously formed into a taper shape having a taper angle of 75 degrees or less, and the taper angle of the capacitor can be formed to 75 degrees or less by dry etching based on Ar physical sputtering. In this way, a capacitor having no sidewall adhesion film can be formed.
  • the completed capacitor has a tapered shape, and depending on the thickness of each layer of the capacitor, there is a limit to the degree of integration due to an increase in the bottom area of the capacitor. However, there is no problem in practical use.
  • Semiconductor memory such as DRAM The major challenge is to reduce the cell area as the capacity increases and to improve the degree of integration.
  • a typical object of the present invention is to overcome the above-mentioned problems, and to provide a highly integrated and highly reliable semiconductor memory device.
  • Another representative object of the present invention is to provide a manufacturing method capable of realizing the above-described semiconductor memory device by a relatively simple process. Disclosure of the invention
  • a stacked capacitor including a lower electrode, an insulating film, and an upper electrode is provided on a main surface of a semiconductor substrate, and charges are stored in the capacitor.
  • a side wall of the capacitor has a side wall spacer, and the upper electrode is provided with the upper electrode. It is located inside the doorspacer. This ensures that the side of the lower electrode and the side of the upper electrode are electrically separated, so that there is no short between the two electrodes, and the semiconductor memory device is particularly suitable for high integration.
  • a method of manufacturing a semiconductor memory device having a multilayer capacitor according to a typical embodiment of the present invention, after performing dry etching of an upper electrode, forming a sidewall spacer prior to dry etching of a lower electrode. It is characterized by: As a result, the tapered portion of the side wall spacer does not adhere to the side wall due to self-cleaning during dry etching, so that processing without a short shot becomes possible, and high reliability and high integration are achieved. Thus, a semiconductor memory device is obtained.
  • FIG. 1 is a sectional view of a main part of a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 2 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention.
  • FIG. 3 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 2;
  • FIG. 4 is a fragmentary cross-sectional view following FIG. 3 showing the manufacturing steps of the semiconductor memory device S of the first embodiment of the present invention.
  • FIG. 5 is a fragmentary cross-sectional view following FIG. 4, showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention
  • FIG. 6 is a fragmentary sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 5;
  • FIG. 7 is an essential part cross sectional view showing the manufacturing process of the semiconductor memory device of the first embodiment of the present invention, following FIG. 6;
  • FIG. 8 is a cross-sectional view of the essential part showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG.
  • FIG. 9 is a fragmentary cross-sectional view following FIG. 8, showing the manufacturing steps of the semiconductor memory device of the first embodiment of the present invention.
  • FIG. 10 is an essential part cross sectional view showing the manufacturing step of the semiconductor memory device of the first embodiment of the present invention, following FIG. 9;
  • FIG. 11 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 10;
  • FIG. 12 shows a semiconductor according to the first embodiment of the present invention
  • FIG. 14 is a cross-sectional view of a main part showing a manufacturing step of the storage device.
  • FIG. 13 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 12;
  • FIG. 14 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 13;
  • FIG. 15 is a fragmentary cross-sectional view showing a semiconductor memory device according to a second embodiment of the present invention.
  • FIG. 16 is a sectional view showing a main part of a semiconductor memory device according to a third embodiment of the present invention.
  • FIG. 17 is a sectional view showing a main part of a semiconductor memory device according to a fourth embodiment of the present invention.
  • FIG. 18 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the fifth embodiment of the present invention.
  • FIG. 19 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device of the fifth embodiment of the present invention, following FIG. 18;
  • FIG. 20 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the sixth embodiment of the present invention, following FIG. 19;
  • FIG. 21 is a plan view showing a sixth embodiment, in particular, a memory cell layout to which the first embodiment is applied.
  • FIG. 22 is a sectional view taken along the line AA of FIG. 21.
  • FIG. 23 is a plan view showing a seventh embodiment, in particular, another memory cell layout to which the first embodiment is applied.
  • FIG. 24 is a plan view showing an eighth embodiment, in particular, another memory cell layout to which the first embodiment is applied.
  • FIG. 25 is a sectional view taken along the line AA ′ shown in FIG. 24.
  • FIG. 26 is a cross-sectional view of a main part of a conventionally known memory cell.
  • FIG. 27 is a cross-sectional view of main parts of another conventionally known memory cell.
  • FIG. 28 is a fragmentary cross-sectional view for explaining problems in the method of manufacturing the memory cell shown in FIG. 27;
  • FIG. 29 is an explanatory diagram of a method of obtaining a clean side wall condition, which is a means of the present invention.
  • FIG. 30 is a graph showing a range of clean side wall conditions, which is a means of the present invention.
  • Fig. 31 is a cross-sectional view of the main part of the capacitor proposed earlier.
  • FIG. 1 is a cross-sectional view of a main part of a semiconductor pathological device (hereinafter referred to as a semiconductor memory) at a stage where a capacitor is formed.
  • a semiconductor memory a semiconductor pathological device
  • an element isolation region 102 is formed on a substrate 101.
  • a MISFET absolute gate field effect transistor
  • the gate electrode 104 and the semiconductor region (diffusion layer) 103 is formed.
  • a plug 106 is formed using CVD and dry etching.
  • a barrier layer 107, a lower metal electrode 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed by dry etching using the same mask as the deposition of each layer.
  • a barrier species 107, a lower metal cladding 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed by dry etching using the same mask as the deposition of each layer,
  • a side wall spacer 114 is formed, and then the lower metal electrode 108 and the barrier layer 107 are etched to form a capacitor. Since a taper angle ( ⁇ ) is formed at the portion of the wall spacer 114, the deposited electrode material is removed by self-cleaning at this portion, so that a capacitor having no side wall deposition film can be formed.
  • the completed multilayer capacitor has the side wall of the upper electrode U1 covered with the side wall base 114. That is, the upper electrode 111 is located inside the side wall spacer 114.
  • an element isolation region 102 is formed in a semiconductor substrate (for example, a P-type Si substrate or a P-type well region) 101.
  • the element isolation region 102 is formed of an oxide film selectively formed on the main surface of the semiconductor substrate 101 by LOCOS (Local Oxidation of Silicon) technology.
  • LOCOS Local Oxidation of Silicon
  • a MISFET is formed by the gate electrode 104 and the diffusion layer 103.
  • the gate oxide film below the gate electrode 104 is formed to a predetermined thickness prior to the formation of the gate electrode.
  • an interlayer insulating film for example, a SOG (Spin On Glass) film 105 is covered and flattened by a reflow process, a through hole is provided in the interlayer insulating film 105.
  • the W (tungsten) plug 106 is formed so as to fill the through hole provided in the interlayer insulating film 105 by using a CVD technique and an etch pack by dry etching.
  • a capacitor is formed on the plug 106. That is, the barrier layer 107, the lower metal layer 115, the insulating film layer 116, the upper metal layer 117, the hard mask layer 118 and a resist mask 119 are sequentially formed.
  • the Nono Domasuku layer 118 may be an insulating material such as Si0 2 or Si 2 N 3 or A1 2 0 3, it may be used a metal such as A1 or Cu. Further, as the barrier layer 107, TiN is preferable.
  • the electrode material This is effective when the side wall is formed by etching.
  • a hard mask 120 is formed.
  • the hard mask 120 is processed so as to have a taper angle of 75 degrees or less.
  • taper processing method when a metal is used as a hard mask, tapering can be performed by processing under conditions that allow side etching by dry etching, or processing may be performed by wet etching. If an insulator is used as a hard mask, it can be processed by either time modulation dry etching, in which deposition and dry etching are alternately performed, or wet etching.
  • the temperature of the substrate is etched near room temperature by dry etching using SF 6 plasma
  • taper processing by side etching is possible.
  • the taper angle can be controlled by controlling the side etching amount and controlling the ion energy by the bias.
  • the resist mask on the hard mask 120 is removed by an ashing step.
  • the upper metal S (117) is dry-etched to form an upper metal electrode 111.
  • Pt is used as the upper metal layer
  • Ar gas is When sputter etching is performed under the conditions of a pressure of 10 mTorr and RF of 500 W, etching can be performed at an etching speed of 20 nm / min. When using the same as the hard mask 120, 3 is obtained as the mask selectivity under this condition.
  • Dry etching may be performed by physical sputtering using a rare gas plasma such as Ar or Ar, or dry etching using a halogen-based gas containing F, C 1, or Br. Even in dry etching by physical sputtering using Ar gas plasma with Pt, if the hard mask 120 has a taper angle of 75 degrees or less, there is no side wall adhesion on the side wall of the hard mask 120 due to self-cleaning during dry etching. Dry etching is possible.
  • the capacitor insulating film 109 is processed by etching. If sputtering by Ar plasma or the like is used for this etching, since the selectivity with the lower metal layer 115 is low, the base metal layer 115 is shaved at the end of the etching, and the side wall adhesion film is formed on the side of the capacitor insulating film 109. There is a drawback that it may be formed on the wall, but there is no practical problem if the in-plane distribution of the etching rate is controlled uniformly.
  • the process may proceed to the next step before the etching of the capacitor insulating film 109 is completed.
  • PZT is used as the insulating film of the capacitor, for example, using a mixed gas of Ar and CF 4 gas as an etching gas, the PZT etch is performed at RF 500 W and a pressure of 10 mTorr in a parallel plate type etching apparatus.
  • Etching can be performed at a speed of 40 nm / min. W as hard mask 120 In this case, a mask selectivity of 4 is obtained under these conditions.
  • Pt is used as the lower metal layer, a selectivity of 3 against the lower metal under this etching condition is obtained.
  • an insulating film layer 121 is deposited by a CVD method. Specifically, absolute ⁇ layer 121 is Si0 2 film. Then, as shown in FIG. 8, a reseal wall spacer 114 is formed by etching back. The material of the insulation ⁇ layer 121, S ⁇ in addition to Si0 2, such as A1 2 0 3, Ti0 2, Ta 2 0 6, those capable of deposition by CVD is selected. Next, as shown in FIG. 9, the lower metal layer (115) is etched to form a lower metal electrode.
  • the sidewall attachment film 113 adheres to the pattern vertical portion, but the sidewall of the hard mask 120 and the sidewall spacer 114 has a taper angle, so that the sidewall attachment film does not adhere.
  • the sidewall attachment film 113 adheres to the pattern vertical portion, but the sidewall of the hard mask 120 and the sidewall spacer 114 has a taper angle, so that the sidewall attachment film does not adhere.
  • the sputtering by Ar gas plasma since Pt / Si0 2 etch rate ratio is about 1, Sa I Douorusu in the lower Pt etching
  • the spacer 114 is also etched. If the side spacers 114 are etched by the height of the hard mask 120 during the lower Pt etching, as shown in FIG.
  • the side wall spacers U4 are located beside the upper metal electrode 111 and the capacitor insulating film 109. Processing that can be formed only can be performed. Such processing involves controlling the height of the hard mask at the time of forming the sidewall spacer in FIG. 8 (this can be controlled by the deposited film thickness of the hard mask layer), and the Pt / Si0 2 can be formed by controlling the etch rate ratio.
  • the conditions and film thickness for this addition differ depending on the material of the lower electrode, the material of the sidewall spacer, the etching gas and the etching equipment, but it is necessary to control the thickness of the hard mask layer and control the etch rate ratio. Changes Absent.
  • the sidewall adhesion film 113 does not need to be removed because there is no short-circuit problem because of the presence of the sidewall spacer 114, but it does not need to be removed, but it increases the reliability of the process and suppresses variations in product characteristics. Therefore, it is desirable to remove them. Therefore, in this embodiment, as shown in FIG. 10, the side wall adhesion film was removed by wet treatment.
  • aqua regia is effective in the case of Pt deposits, and in the case of other substances, a solution treatment appropriate for the type may be performed. It is also effective depending on the type of the lower metal material, such as a downflow plasma treatment and a paper treatment.
  • an insulating film layer 122 is deposited.
  • a flat surface required for the following wiring process can be formed at this point.
  • a flat surface can be created by using etch pack technology or CMP (chemical mechanical polishing) technology, etc., and a sputter insulating film or a CVD insulating film may be used.
  • the insulating film layer 122 is processed by etching or CMP until the upper metal electrode 111 is exposed.
  • a plate electrode 123 is formed. This plate electrode 123 is subjected to wiring processing as necessary. Further, by performing necessary wiring processing, a DRAM device is formed.
  • a side wall spacer 114 is formed immediately after the etching of the upper metal electrode 111, and thereafter, the etching of the capacitor insulating film 109 and the lower metal electrode 108 is performed.
  • the side wall adhesion film 113 since the capacitor insulating film 109 is in contact with the side wall adhering film 1, if the wet process is performed to remove the side wall adhering film 113, the electrical characteristics of the capacitor insulating film 109 may be deteriorated.
  • a memory cell is formed with the sidewall adhesion film 1 13 left. If the sidewall adhesion film 113 can be removed without deteriorating the electrical characteristics, the treatment may be performed.
  • the size of the capacitor insulating film 109 and the lower metal electrode 108 are substantially the same, and the length of the lower side of the upper metal electrode 111 is longer than the length of the upper side of the insulating film 109. It is characterized by being short. In other words, in FIG. 15, the condition is that Le ⁇ Li.
  • a sidewall spacer 114 is formed.
  • the base metal film is shaved at the end of the etching of the capacitor insulating film 109, and the upper metal electrode is formed before forming the sidewall spacer.
  • the lower metal layer may be short-circuited by the sidewall adhesion film.
  • the length of the upper side of the insulating film 109 is shorter than the length of the lower side of the insulator 109. That is, in FIG. 16, there is a relationship of L bi> L ui.
  • FIG. 17 shows a structure formed by a method in which the step of removing the sidewall adhesion film 113 is omitted from the method described in the first embodiment. If the sidewall adhesion film 113 is made of a stable material such as Pt, it does not need to be removed, so that it can be manufactured at low cost by omitting the steps.
  • a fifth embodiment of the present invention will be described with reference to FIGS. This embodiment is obtained by omitting some steps from the method of the first embodiment.
  • the omitted step is the step of forming the capacitor by etching and then flattening it with a reflow film or CMP.
  • the semiconductor memory shown in FIG. 18 is formed by the following steps.
  • An element isolation region 102 is formed on a semiconductor substrate 101, and a gate electrode (omitted in this drawing) and a diffusion layer 103 are formed. Thereafter, an interlayer insulating film 105 and a plug 106 are formed, and then an upper metal electrode 111, a capacitor insulating film 109, a side spacer 114, and a lower metal electrode 108 are formed using a film deposition and etching process. After performing the sidewall adhesion film removing step, the barrier layer 107 is etched to form a capacitor. Up to this point, the method is the same as that described in the first embodiment.
  • a CVD insulating film layer 121 is deposited. As shown in the figure, the deposited film thickness should be more than 1/2 of the distance between adjacent capacitors. As the material of the insulating film layer, the material described in Embodiment 3 may be used.
  • the capacitor isolation portion 124 is formed by etching-packing the CVD insulating layer. By etching back the CVD insulating layer deposited more than half of the capacitor interval, the step between the capacitors is reduced.
  • a plate electrode 123 is formed. Since the steps are alleviated by the capacitor separating portion 124, the plate electrode 123 can be formed as a highly reliable plate electrode which does not break even when the sputtering method is used.
  • the thickness of the CVD insulating film layer it is sufficient to increase the thickness of the CVD insulating film layer.
  • the thickness is increased, there is a problem that the processing time of the deposition and etching steps becomes longer and the throughput is reduced, but there is no problem in practical use.
  • the CVD insulating film layer is thinner than 1/2, the effect of alleviating the step is reduced.
  • the capacitor separating portion 124 is formed by the side wall of the capacitor. This is effective because the vertical steps are inclined.
  • the present embodiment is particularly effective when a fine and highly integrated memory is to be manufactured, when the height of the capacitors is almost equal to the interval between the capacitors and the step between the capacitors is steep. Even in such a case, since the processing can be performed without using a time-consuming process such as reflow or CMP, the throughput can be increased.
  • FIG. 21 shows an embodiment of a planar layout of a memory cell according to the present invention.
  • This layout uses a two-intersection cell and a COB (Capacitor Over Bitline) structure that forms a capacitor on a bit line.
  • the transistors (not explicitly shown) of each memory cell are connected to peripheral circuits (not shown) via bit lines 208.
  • the connection between the transistor and bit line 208 is part of the active area 218 This is the portion of the formed bit line plug 207.
  • the operation of the transistor is controlled by a word line (gate electrode) 203.
  • This word line (gate electrode) 203 is connected to a peripheral circuit (not shown).
  • the connection from the transistor to the capacitor section 220 is made via a capacitor plug 211.
  • the capacitor section 220 is connected to a peripheral circuit (not shown) via a plate electrode 216.
  • the first feature of this planar layout is that one plate electrode 216 is wired for two word lines 203.
  • the capacity of the plate electrode 216 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 216 can be easily controlled by a peripheral circuit. Therefore, the operation of the nonvolatile memory using ferroelectricity becomes easy.
  • the number of plate electrodes may be one plate electrode for one word line.
  • one plate may be used for three or more lead wires.
  • the number of plate electrodes increases, it becomes difficult to increase the degree of integration. If the number of plate electrodes decreases, the capacitance of the plate electrode increases, making control by peripheral circuits difficult.
  • the optimal number of plate electrodes varies depending on the memory application.
  • the second feature of this planar layout is that the blade electrode 216 is wired in the same direction as the lead wire (gate electrode) 203. Therefore, when the potential of the plate compressing electrode 216 is controlled by the peripheral circuit, the potential can be controlled in synchronization with the potential of the lead wire 203.
  • FIG. 22 shows a cross-sectional structure (cross-section A-A ′) of FIG. 21. This cross-sectional structure will be described below.
  • An S i 02 202 for element isolation is formed on an S i substrate 201.
  • a MISFET consisting of a gate oxide film (not shown), word lines (gate electrodes) 203 and diffusion layers 204 is formed.
  • Wa lead wire 203 is used Si02 222 Yes and re processed by the dry etching as a mask, and the insulating protective film as it leaves the word lines Si0 2 222.
  • the Si0 2 222 need not to leave it, to delete the structure and to Re when removing step of the present embodiment, also acts as a protective film at the time of forming the gate electrode spacer 221.
  • doped poly Si which is often used as a normal gate electrode, or a silicide such as WSi, oSi, or CoSi may be used.
  • a metal material such as W or TiN, or a film thereof may be used.
  • the word line (gate electrode) 203 has a gate electrode spacer 221 formed thereon. Although this gate electrode spacer is not essential, it has the effect of alleviating steps and the effect of preventing electrical shorts, so that a highly reliable C0B structure can be formed.
  • a word line insulating protective film 205 is formed on the word line (gate electrode) 203.
  • this protective film is not always necessary, it has an effect of preventing an electrical short-circuit when performing dry etching for forming the bit line plug 207 and the capacitor plug 211. If the material is changed (for example, Si 3 N, and Si 0 2 ) between the plug portion and the word line step flattening insulating film 206, the above-described plug portion can be self-aligned using high selective dry etching between insulating films. There is an effect that dry etching can also be performed.
  • the step formed by forming the word line (gate electrode) 203 is flattened by the word line step flattening insulating film 206.
  • a material for the insulating film a fluid insulating film (such as BPSG) or a CVD insulating film may be used. Planarization methods include reflow of the fluid insulating film and dry etching. W
  • the BPSG reflow film is polished by CMP to form the word line step flattening insulating film 206. Since this film is easily removed by dry etching, in this embodiment, an insulating protective film 223 for a planarizing insulating film is formed. If this film is formed by a CVD-sputter deposition method, a denser film can be formed than a reflow film. As the material of the film may be those used in the S i 0 2 and S 3 N ⁇ as any conventional S i LS I process.
  • bit line plug 207 is formed.
  • the bit line plug 207 is formed by forming a hole pattern by dry etching and then forming n + polySi by using a CVD method.
  • the bit line plug 207 may be made of a material such as T i N in addition to 11 + poly S i.
  • the bit line 208 shown in FIG. 21 is also formed.
  • a material such as n + polySi, silicide, or a laminated film thereof may be used.
  • the insulating protection film 209 for the bit line is formed.
  • This film is not essential, but has the same effect as the word line insulating protective film 205.
  • a bit line step flattening insulating film 210 is formed thereon. The formation method and material of this film may be considered in the same manner as the word line step flattening insulating film 206.
  • an insulating protective film 224 for flattening insulating film is formed in this embodiment. Although this protective film is not essential, it has the same effect as the above-described green protective film 223 for a planarizing insulating film.
  • the child of the film becomes the base film in the dry etching of the capacitor, when an insulating film containing A1 atoms such as A1 2 0 3, allows a high selective dry etching in the dry etching of the capacitor.
  • an insulating film containing A1 atoms such as A1 2 0 3
  • dry etching using an Ar or C1-based gas can be processed to a shape that is more vertical.
  • etching resistance can be high because high selective dry etching.
  • Pt dry etching with a high selectivity between the mask and the underlayer can be performed.
  • the capacitor plug 211 is formed.
  • a conductive material is embedded in the hole pattern.
  • n + poly Si used in the conventional Si LSI process may be used, or a material such as TiN, W, Ta, or Ti may be embedded by CVD.
  • the strong ⁇ of absolute ⁇ and good compatibility with Pt, Ru, Ir, Pd, Rh, 0s, Hf, Zr and those are electrically conductive and their oxides (for example Ru0 2, Ir0 2) even by using a Good.
  • a stacked film thereof may be used.
  • Ru0 be formed using a CVD process, such as 2 or Ir0 2, etc. are M0CVD method, can be formed without disconnection of the hole pattern, when the laminated and Ru or ⁇ r thereon, Ru Since materials such as Ir and Ir act as a barrier layer against oxygen, the oxidation resistance in subsequent steps can be improved.
  • the capacitor upper electrode 214, the capacitor insulating film 213, the side electrode spacer 217, the capacitor lower electrode 212, and the barrier metal 219 are formed by the process described in the third embodiment. It is formed.
  • the Pt etching may be performed by Ar sputtering, and the PZT etching may be performed by CF 4 + Ar gas collective dry etching using a W hard mask as described in the third embodiment.
  • an insulating material comprising A 1 atoms as I Douorusu spacers 217 e.g., A 1 2 0 3) dry etching Pt may be Doraietsuchin grayed by F-based gas.
  • the lower electrode of the capacitor other than PI, Ru, Ir, Pd, Rh, Os, Hf, or an oxide thereof and having conductivity may be used.
  • ferroelectric insulators other than PZT insulating films containing Bi, insulating films containing La or Y, insulating films containing Ba or Sr, insulating films containing Cu
  • W or A1 which can be used as a hard mask, TiN, Ta, Cu, Ag, Au, or the like may be used. It may be used, or a stacked film thereof may be used.
  • an insulating protective film 215 for a capacitor is formed in this embodiment.
  • this film is flattened by a combination of a reflow film and CMP.
  • complete flattening is not essential, it is desirable to flatten as much as possible to improve the reliability of the wiring thereafter.
  • the flattening method and material may be the same as the formation of the bit line step flattening insulating film and the formation of the word line step flattening insulating film.
  • an oxide film such as Ti, Zr, or Pb, which is compatible with the material of the capacitor part, is formed using a CVD method as a protective insulating film of the capacitor part, and then a reflow insulating film is formed to form a laminated film. Good.
  • the ferroelectric insulating film tends to deteriorate its characteristics in a reducing atmosphere or an atmosphere in which H atoms are generated.
  • CVD-S i 0 2 film it may be used an organic insulating material such as PI Q (Poryimi de I Seo India Loki mystery dione).
  • the plate electrode 216 is formed in this embodiment.
  • Such materials include 11+ pol y Si and W What is necessary is just to use a material conventionally used in the Si LSI process.
  • a conductive material deposited by sputtering may be used as the electrode material, and in the case of a stepped structure as shown in FIG. May be used to deposit a conductive material.
  • a structure shown in FIG. 22 can be formed.
  • FIG. 22 shows a cross-sectional view of the memory cell section up to the formation of the plate electrode. Needless to say, in actual memory, it is necessary to form two or more eyebrows to connect the memory cell part and peripheral circuits, and also to perform packaging.
  • FIG. 23 shows another embodiment of the planar layout of the memory cell according to the present invention.
  • This layout uses a two-intersection cell and a COB (Capacitor Over Bit Line) structure that forms a capacitor on a bit line.
  • the transistors (not explicitly shown) of each memory cell are connected to peripheral circuits (not shown) via bit lines 208.
  • the connection between the transistor and the bit line 208 is a bit line plug 207 formed in a part of the active region 218.
  • the operation of the transistor is controlled by a word line (gate / pole) 203.
  • This word line (gate gate) 203 is connected to peripheral circuits (not shown).
  • the transistor is connected to the capacitor section 220 via the capacitor plug 211.
  • the capacitor section 220 is connected to a peripheral circuit (not shown) via a plate electrode 216.
  • the first feature of this planar layout is that one plate electrode 216 is wired for one bit line 208.
  • the capacity of the plate electrode 216 is smaller than that of a normal DRAM. This makes it easier to control the potential of the plate electrode 216 by a peripheral circuit. Therefore, the operation of the nonvolatile memory using ferroelectricity becomes easy.
  • the number of plate electrodes is set to one plate electrode for two or more bit lines. Is also good. However, as the number of plate electrodes decreases, the capacitance of the plate electrode increases, making control by peripheral circuits difficult. The optimal number of plate electrodes depends on the application of the memory.
  • the second feature of this planar layout is that the plate electrode 216 is wired in the same direction as the bit line 208. Therefore, when the potential of the plate electrode 216 is controlled by the peripheral circuit, the potential can be controlled in synchronization with the potential of the bit line 208.
  • FIG. 24 shows another embodiment of the planar layout of the memory cell according to the present invention.
  • This layout uses a two-intersection cell and a COB (Capacitor Over Bitline) structure that forms a capacitor on a bit line.
  • the transistor (not explicitly shown) of each memory cell is connected to a peripheral circuit (not shown) via a bit line 208.
  • the connection between the transistor and the bit line 208 is a bit line plug 207 formed in a part of the active region 218.
  • the operation of the transistor is controlled by a word line (gate electrode) 203.
  • This word line (gate electrode) 203 is connected to a peripheral circuit (not shown).
  • the transistor is connected to the capacitor section 220 via the capacitor plug 211.
  • the capacitor section 220 is connected to a peripheral circuit (not shown) via a plate electrode 216.
  • the first feature of this planar layout is that the DRAM operation is considered That is, the capacitor is controlled by the plate electrode 216.
  • FIG. 25 shows a cross-sectional structure (cross-section AA ′) in FIG. This cross-sectional structure is basically the same as FIG. 202 described in Embodiment 8 except for the plate electrode 216.
  • the processing of the plate electrode 216 may be performed to a required size as in the eighth embodiment.
  • a problem occurs when a capacitor is processed in only one lithography step. It is possible to prevent a short circuit between the poles. As a result, a margin for mask alignment is not required, and a highly integrated semiconductor memory using a fine capacitor can be added.
  • the present invention is useful as a highly reliable and highly integrated capacitor, and is suitable for use in large-capacity DRAMs of 1 gigabit or more.

Abstract

Des courts-circuits se produisent souvent entre des électrodes à condensateur supérieure et inférieure du fait des particules déposées sur les bords latéraux d'un condensateur multicouches très petit pendant son attaque à sec dans un procédé lithographique. Ce problème est résolu par l'utilisation d'un matériau d'électrodes (par exemple Pt) dont les produits de réaction provoqués par l'attaque présentent une faible volatilité. Une fois l'électrode métallique supérieure (111) attaquée à sec, un élément d'espacement (114) de parois latérales est formé avant que ne débute l'attaque à sec de l'électrode métallique inférieure (108). Etant donné que rien n'est déposé sur la partie conique de l'élément d'espacement (114) du fait d'une action auto-nettoyante se produisant pendant l'attaque à sec, aucun court-circuit ne se produit entre les électrodes (111 et 108).
PCT/JP1996/000685 1996-03-15 1996-03-15 Dispositif de stockage a semi-conducteur et sa production WO1997035341A1 (fr)

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PCT/JP1996/000685 WO1997035341A1 (fr) 1996-03-15 1996-03-15 Dispositif de stockage a semi-conducteur et sa production
JP53333997A JP3666877B2 (ja) 1996-03-15 1996-03-15 半導体記憶装置およびその製造方法
TW085115005A TW312832B (en) 1996-03-15 1996-12-05 Semiconductor memory device and manufacturing method thereof

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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10057444A1 (de) * 2000-11-20 2002-05-29 Infineon Technologies Ag Verfahren zum Herstellen einer Kondensatoranordnung
WO2002082549A1 (fr) * 2001-04-05 2002-10-17 Renesas Technology Corp. Dispositif de circuit integre a semi-conducteur et son procede de production
JP2002353414A (ja) * 2001-05-22 2002-12-06 Oki Electric Ind Co Ltd 誘電体キャパシタおよびその製造方法
US6586790B2 (en) 1998-07-24 2003-07-01 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6611014B1 (en) 1999-05-14 2003-08-26 Kabushiki Kaisha Toshiba Semiconductor device having ferroelectric capacitor and hydrogen barrier film and manufacturing method thereof
JP2006185991A (ja) * 2004-12-27 2006-07-13 Fujitsu Ltd 半導体装置
JP2006303188A (ja) * 2005-04-20 2006-11-02 Oki Electric Ind Co Ltd 強誘電体キャパシタ及びその製造方法
JP2007019276A (ja) * 2005-07-07 2007-01-25 Oki Electric Ind Co Ltd 強誘電体素子の製造方法
JP2007335897A (ja) * 2007-08-29 2007-12-27 Fujitsu Ltd 半導体装置の製造方法
WO2008111199A1 (fr) * 2007-03-14 2008-09-18 Fujitsu Microelectronics Limited Dispositif semiconducteur et son procédé de fabrication
US10522467B2 (en) 2016-07-06 2019-12-31 Tokyo Electron Limited Ruthenium wiring and manufacturing method thereof
KR20210135914A (ko) * 2020-05-05 2021-11-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 비휘발성 메모리 디바이스 및 제조 기술
EP4156313A1 (fr) * 2021-09-24 2023-03-29 INTEL Corporation Condensateur multicouche avec isolateur périphérique

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132482A (ja) * 1992-10-19 1994-05-13 Sharp Corp 半導体記憶装置
JPH0794600A (ja) * 1993-06-29 1995-04-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH088348A (ja) * 1994-06-20 1996-01-12 Hitachi Ltd 半導体集積回路装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132482A (ja) * 1992-10-19 1994-05-13 Sharp Corp 半導体記憶装置
JPH0794600A (ja) * 1993-06-29 1995-04-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH088348A (ja) * 1994-06-20 1996-01-12 Hitachi Ltd 半導体集積回路装置およびその製造方法

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586790B2 (en) 1998-07-24 2003-07-01 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6982444B2 (en) 1998-07-24 2006-01-03 Kabushiki Kaisha Toshiba Ferroelectric memory device having a hydrogen barrier film
US6611014B1 (en) 1999-05-14 2003-08-26 Kabushiki Kaisha Toshiba Semiconductor device having ferroelectric capacitor and hydrogen barrier film and manufacturing method thereof
US6982453B2 (en) 1999-05-14 2006-01-03 Kabushiki Kaisha Toshiba Semicondutor device having ferroelectric capacitor and hydrogen barrier film and manufacturing method thereof
DE10057444A1 (de) * 2000-11-20 2002-05-29 Infineon Technologies Ag Verfahren zum Herstellen einer Kondensatoranordnung
US6649483B2 (en) 2000-11-20 2003-11-18 Infineon Technologies Ag Method for fabricating a capacitor configuration
WO2002082549A1 (fr) * 2001-04-05 2002-10-17 Renesas Technology Corp. Dispositif de circuit integre a semi-conducteur et son procede de production
JP2002353414A (ja) * 2001-05-22 2002-12-06 Oki Electric Ind Co Ltd 誘電体キャパシタおよびその製造方法
JP2006185991A (ja) * 2004-12-27 2006-07-13 Fujitsu Ltd 半導体装置
JP2006303188A (ja) * 2005-04-20 2006-11-02 Oki Electric Ind Co Ltd 強誘電体キャパシタ及びその製造方法
JP2007019276A (ja) * 2005-07-07 2007-01-25 Oki Electric Ind Co Ltd 強誘電体素子の製造方法
JP4621081B2 (ja) * 2005-07-07 2011-01-26 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
WO2008111199A1 (fr) * 2007-03-14 2008-09-18 Fujitsu Microelectronics Limited Dispositif semiconducteur et son procédé de fabrication
JP5212358B2 (ja) * 2007-03-14 2013-06-19 富士通セミコンダクター株式会社 半導体装置の製造方法
US8956881B2 (en) 2007-03-14 2015-02-17 Fujitsu Semiconductor Limited Method of manufacturing a FeRAM device
JP2007335897A (ja) * 2007-08-29 2007-12-27 Fujitsu Ltd 半導体装置の製造方法
JP4515492B2 (ja) * 2007-08-29 2010-07-28 富士通セミコンダクター株式会社 半導体装置の製造方法
US10522467B2 (en) 2016-07-06 2019-12-31 Tokyo Electron Limited Ruthenium wiring and manufacturing method thereof
KR20210135914A (ko) * 2020-05-05 2021-11-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 비휘발성 메모리 디바이스 및 제조 기술
KR102518679B1 (ko) 2020-05-05 2023-04-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 비휘발성 메모리 디바이스 및 제조 기술
EP4156313A1 (fr) * 2021-09-24 2023-03-29 INTEL Corporation Condensateur multicouche avec isolateur périphérique

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