Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance

Definitions

• the invention relates to a separable connecting bridge and a connectable line break, and to a method for producing and activating a separable connecting bridge and a connectable line break.
• Fuse arrangements are used in integrated circuits in order to separate (“fuse”) or to re-establish electrically conductive connections (“anti-fuse”) after the actual manufacturing process.
• the uses of such fuse arrangements are very diverse. Fuses are used for trimming, for example of analog circuits. Fuses are also used to activate redundant circuit parts and to switch off faulty ones.
• PLA programmable logic arrays
• the logic operations are programmed using fuses.
• fuses prevent unauthorized persons from accessing the test modes of the circuit.
• fuse or anti-fuse arrangements are service life and reliability, ie how safe and over what period of time a fuse or anti-fuse preserves the two states off / on, regardless of current density and temperature. Another criterion is the effort to activate fuse or. Anti-fuse arrangements, for example when testing a fuse. For security-critical applications, security against reprogramming and external contacting is still essential. So far, fuse assemblies have essentially been made from metal, from polysilicon, or from a dielectric.
• the poly fuses to be assigned to a further class are designed in the same way as metal fuses as laser fuses or electrical fuses.
• the conductive material poly-silicon has disadvantages compared to metal, since the thermal destruction and thus the activation of the fuse is more difficult due to the relatively good thermal coupling to the substrate and the better migration resistance.
• the third-class anti-fuses with a dielectric for example made of the material SiN, see MT Takagi, I. Yoshii, N. Ikeda, H. Yasuda, K. Hama, Pros. IEDM 1993, pages 31 to 34
• a high-resistance semiconductor for example made of amorphous silicon, see KE Gordon, R. J. Wong, Proc. IEDM 1993, pages 27 to 30
• a destructible isolator are typically used in programmable logic arrays. They are activated by sufficiently high voltages. Protection against manipulation is improved compared to metal and polyfuses. Nevertheless, due to the locally high current densities in the programmed (conductive) anti-fuses, there is a risk of the insulation healing again.
• Another major disadvantage of such anti-fuses is the higher process outlay for the additional insulator and electrode layers.
• an anti-fuse arrangement with a P + -doped diffusion region formed within an N-well and an aluminum conductor track assigned to the diffusion region has also become known.
• This anti-fuse arrangement is activated by applying a sufficiently large current to the conductor track so that aluminum migrates downward from the conductor track into the diffusion region, and an irreversible process by destroying the pn junction of the diffusion region Line is caused.
• This anti-fuse arrangement initially only represents a one-sided anti-fuse arrangement, ie it can only be operated in one current direction, ie it acts as a reverse-connected diode.
• the object of the invention is to provide a fuse and / or anti-fuse arrangement which is simple to manufacture and to activate and which can be used in safety-relevant integrated circuits.
• This object is achieved by a separable connecting bridge (fuse) according to claim 1, a connectable line interruption (anti-fuse) according to claim 8, and by a method for producing and activating a fuse or anti-fuse according to claims 16 and 17 .
• the invention provides for the formation of a new class or a new type of fuse and anti-fuse arrangement in which, instead of a metal sheet applied to the substrate and therefore easily recognizable, a metal track formed inside the surface of the semiconductor substrate and not recognizable from the outside Conductive diffusion path is formed, which is separated or produced for activation.
• the semiconductor material of the substrate represents a first conduction type, while the material of the diffusion connection is of a second conduction type, which has the opposite sign of the first conduction type.
• the first line type may be referred to as p and the second line type as n, although it is within the scope of the invention to interchange the two line types.
• the fuse and anti-fuse arrangements according to the invention cannot be found from the outside, external contacting is extremely complicated, and reprogramming is impossible, so that the fuse and anti-fuse arrangements according to the invention are outstandingly suitable for safety circuits.
• the fuse and anti-fuse arrangements according to the invention have an inherently high reliability, since the diffusion process to be carried out to activate the fuse or anti-fuse is thermodynamically irreversible, so that once a fuse or anti-fuse is activated, it is not in principle can heal again.
• a laser beam can advantageously be used for locally heating an activation section, as a result of which irreversible mutual diffusion of the n- and p-dopants from the diffusion regions takes place.
• heating by means of a current flow through the diffusion path is also possible in principle.
• Other heating variants are also conceivable, for example in the form of a resistive heater by means of resistance meanders, preferably made of polysilicon, which can be integrated on the semiconductor substrate in the immediate vicinity of the activation section.
• the separable connecting bridge (fuse) has an electrically conductive diffusion or conductor track of a second conductor type opposite to the first conductor type, which is formed in a substrate consisting of semiconductor material of a first conductivity type and is continuous in the longitudinal direction and has a predetermined width transversely to the longitudinal dimension.
• the semiconductor material of the first conduction type has such a concentration with respect to the material of the conduction path that, at a predetermined activation temperature which is greater than the operating temperature of the connecting bridge, there is an interruption over the entire width of the conduction path due to diffusion of the semiconductor material of the first conduction type and / or the material of the conductor track of the second conductivity type.
• the conductor track is assigned a diffusion region formed in the substrate consisting of semiconductor material, which is formed by doping with a dopant of the first conductivity type.
• the Diffusion region of the first conduction type formed with the dopant is formed on both sides of the conduction path of the second conduction type which has a smaller width than the dimensions of the diffusion region. It is advantageously provided here that the conduction path of the second conduction type is formed by doping with a doping element whose doping concentration is smaller in magnitude than the doping concentration of the dopant of the diffusion region of the first conduction type.
• the connectable line interruption (anti-fuse) has an electrically conductive diffusion or conductor track formed in a substrate made of semiconductor material and formed by doping with a dopant, with longitudinally extending line sections of a first line forming a gap with a predetermined distance ⁇ type and a at least filling the area of the gap of the conduction path, diffusion area of a second, from the first conduction type opposite conduction type, wherein the dopant of the conduction path pieces with a given diffusion constant with respect to the semiconductor material of the substrate has such a doping concentration that at a predetermined activation temperature, which is greater than the operating temperature of the line interruption, a diffusion of the dopant of the conductor track pieces takes place over the entire distance of the gap in the conductor track.
• the diffusion region of the second conductivity type is formed by doping with a doping element whose doping concentration is smaller in magnitude than the doping concentration of the dopant of the conductor track pieces of the first conductivity type.
• the line interruption (anti-fuse) according to the invention is characterized in that an activation section with an at least two sections is provided by the line sections and the diffusion area filling the gap in the line sections. times pn junction is formed.
• the anti-fuse according to the invention thus represents a two-sided, true anti-fuse in both current directions.
• at least the activation section consisting of a part of the conductor track and the semiconductor material and / or the diffusion region has an electrically insulating, formed on the main surface of the substrate, transparent or at least translucent for radiation of a predetermined wavelength for local heating of the activation section Cover layer is covered.
• Typical fuse lasers for example neodymium YAG lasers penetrate this transparent or at least translucent covering layer, for example made of oxide or Si 3 N 4, largely unhindered and deposit the radiation energy predominantly in silicon, that is to say in the material of the diffusion sheet or the like Substrates.
• the invention even makes it possible to provide an arrangement of fuse or anti-fuse buried within the semiconductor substrate, so that finding from the outside and external contacting is even more difficult. It is provided here that the diffusion or conduction path is arranged or formed completely within the substrate consisting of semiconductor material at a predetermined depth starting from the main surface of the substrate.
• this embodiment of the invention further enables a vertical and therefore space-saving arrangement of the fuse and anti-fuse. It is provided here that the formed within the substrate The length of the conduit extends transversely to the main surface of the substrate.
• the method according to the invention for producing and activating a separable connecting bridge (fuse) comprises the following steps:
• an activation section comprising the conductor track and at least part of the semiconductor material of the substrate up to a predetermined activation temperature which is greater than the operating temperature of the connecting bridge, for irreversible interruption over the entire width of the conductor track by diffusion of the Semiconductor material of the first conductivity type and / or the material of the
• the method according to the invention for producing and activating a connectable line interruption (anti-fuse) comprises the following steps:
• an activation section comprising the gap of the conductor track pieces up to a predetermined activation temperature, which is greater than the operating temperature of the line interruption, for the irreversible diffusion of the dopant of the conductor track pieces over the entire gap of the conductor track.
• radiation with a predetermined wavelength is used for local heating of the activation section.
• the radiation from a laser light source can advantageously be used for local heating of the activation section.
• the activation section by applying a heating current to the conductor track, which is formed by a suitable doping as a resistance track.
• a heating element which is in thermal contact with the conductor track to heat the activation section.
• FIG. 1 shows a schematic view of a separable connecting bridge (fuse) according to an exemplary embodiment of the invention
• FIG. 2 shows a schematic top view of the fuse arrangement according to the exemplary embodiment according to FIG. 1, *
• FIG. 3 shows a schematic view of a separable connecting bridge (fuse) according to a further exemplary embodiment of the invention
• FIG. 4 shows a schematic top view of the fuse arrangement according to a further exemplary embodiment according to FIG. 1;
• FIG. 5 shows a schematic view of a vertical diffusion fuse arrangement according to a further exemplary embodiment of the invention
• Figure 6 is a schematic representation of a diffusion anti-fuse arrangement according to an embodiment of the invention
• Figure 7 is a schematic plan view of the anti-fuse arrangement according to the embodiment of Figure 6;
• FIG. 8 shows a schematic illustration of a vertical diffusion anti-fuse arrangement according to a further exemplary embodiment of the invention.
• FIG. 9 shows a schematic plan view of a wiring field with diffusion anti-fuse arrangements according to a further exemplary embodiment of the invention.
• FIGS. 10A and 10B are circuit diagrams of a programmable NAND gate and NOR gate with diffusion anti-fuse arrangements according to a further exemplary embodiment of the invention.
• FIGS. 10A and 10B show a schematic top view of a layout example of the exemplary embodiment according to FIGS. 10A and 10B.
• FIGS. 1 and 2 show the basic structure of a lateral diffusion fuse arrangement according to an exemplary embodiment of the invention with a low n-doped, narrow flat diffusion path with a width m of approximately 0.5 to 1 ⁇ m, which is of a large, p-doped region 2 is surrounded.
• the area 2 the substrate may represent a wafer with the silicon base material, which is already pre-doped by basic doping with spielnem boron in a concentration of from about 3 • 10 cm ".
• the diffusion sheet is by implant tation of arsenic with an energy of 120 KeV and a dose of about 5.0 ⁇ 10 14 cm “2 .
• the main surface 31 of the substrate is included in a manner known per se coated with a photoresist with an exemplary thickness of about 1.5 ⁇ m, exposed using a suitable mask and developed.
• the photoresist is removed, for example, in an oxygen-containing plasma environment.
• the implantation of the diffusion path is followed by a healing step at a temperature of about 900 Celsius and a duration of 20 minutes. on.
• a covering layer 4 which is transparent or at least translucent for radiation of a predetermined wavelength can be deposited on the main surface 31.
• an activation section 30 indicated by dashed lines is locally heated, for example by brief exposure to laser light of a suitable wavelength, so that in the area of the activation section 6 there is an interdiffusion of n-
• Dopand from the diffusion path and p-dopand from the p-doped region 2 takes place. If the concentration of the p-doping of the region 2 is sufficiently high, the region of the activation section 6 becomes high-resistance or redoped, which leads to the interruption of the n-doped diffusion path.
• FIGS. 3 and 4 show a fuse arrangement in accordance with a further exemplary embodiment of the invention.
• the reference numerals 1 and 3 to 6 designate the same components as in the exemplary embodiment according to FIGS. 1 and 2.
• the diffusion path is assigned on both sides in the p + -doped diffusion regions 7, 8 formed in the substrate consisting of semiconductor material such as silicon , which are formed by implantation of, for example, boron at an energy of 20 KeV and a dose of about 5.0 “10 cm ” and, based on the main surface 31 of the substrate, larger dimensions compared to the width m of the diffusion path
• the two diffusion areas 7 and 8 are arranged at a distance r from one another.
• the diffusion regions 7, 8 are formed in a p-well 9 in the silicon substrate, which follows Structuring with conventional photolithography process steps by means of a mask 10 and subsequent implantation with boron at an energy of approximately 230 KeV and a dose of approximately 1.0 “10 cm ” can be formed.
• FIG. 5 shows a further exemplary embodiment of a fuse arrangement 5 according to the invention, with two connecting bridges 12 and 13 with n-doped diffusion tracks 14, which are juxtaposed within the substrate or an n-well 11 and vertically formed with respect to the main surface 31.
• Hier ⁇ bei two n-doped regions 15 and 16 are connected to one another by means of thin, vertically running n-doped channels 17 and 18.
• two n * -doped and thus low-resistance contact areas 19 and 20 are provided, which are produced by a suitable photolithography process step and a suitable implantation step.
• Another p + -doped contact area 21 formed in the main surface 31 allows the p + -doped diffusion area 22 to be completely contacted within the substrate or the n-well 11 to activate the vertically arranged connecting bridges 12 and 13 are suitable for the heating methods already described for the lateral diffusion fuse arrangements.
• FIGS. 6 and 7 show schematic views of the basic structure of a lateral diffusion anti-fuse arrangement according to a further exemplary embodiment of the invention.
• the substrate has silicon as the basic material with a p-type basic doping with boron of, for example, 3 ⁇ 10 cm " .
• the n-well 28 formed here can be formed after structuring with conventional photolithography process steps and subsequent implantation with phosphorus at an energy of approximately 460 KeV and a dose of approximately 6.0 »10 cm " , an optional anti-punch implantation being used with arsenic at an energy of 320 KeV and a dose of about 8.0 ⁇ 10 11 cm " can be connected.
• the conductor track pieces 24 and 25 formed within the n-well 28 are exposed and developed using a suitable mask, via a subsequent implantation made with boron at an energy of about 20 KeV and a dose of about 5.0 ⁇ 10 1 cm '2 .
• the photoresist mask has been removed by stripping in an oxygen-containing plasma environment, the conductor track pieces 24 and 25 are healed at a temperature of approximately 900 ⁇ Celsius and a duration of approximately 20 minutes.
• the dimensions and doping concentrations of the conductor track pieces 24, 25, the gap 26, and the surrounding diffusion region 27 are selected so that at a sufficiently high activation temperature, which is greater than the normal operating temperature of the line interruption or of the other integrated circuits formed on the substrate, a thermodynamically irreversible diffusion of the doping substances of the conductor track sections 24, 25, 32, 33 takes place over the entire distance of the gap 26 of the conductor track sections 24 and 25.
• Local heating of the activation section 30 to the predetermined activation temperature for example by means of a laser beam directed onto the activation section 30, thus results in a mutual diffusion of the n- and p-dopants.
• the activation section 30 and thus the gap 26 is p-doped, which leads to a permanent electrical connection of the two p + -doped track sections 24 and 25.
• this process is irreversible; the anti-fuse arrangement is also difficult to contact.
• direct heating by electrical current flow is not possible, but indirect heating methods can be used, for example resistive heating by means of adjacent resistance meanders made of polysilicon (not shown in the figures).
• FIG. 8 shows a further exemplary embodiment of the invention with a vertically arranged diffusion anti-fuse arrangement 31 with two highly p * -doped layers 32 and 33, which are isolated from one another by a thin n-doped layer 34 .
• the p * -doped layers 32 and 33 forming the two conductor track pieces of the anti-fuse arrangement 31 with the n-doped layer 34 arranged in between, which represent the gap 26 between the conductor track pieces, can be produced with implantation steps or epitaxial steps.
• FIG. 9 shows, by way of example for the multiple applications of the fuse or anti-fuse arrangements according to the invention, a wiring field with a large number of integrated circuit groups 35 which can be connected by means of the diffusion anti-fuses 36, which are only shown schematically by double arrows.
• Two possible wiring paths 37 and 38 are shown in exemplary form.
• FIGS. 10A and 10B show a further preferred application example in the form of a programmable NAND gate 39 and a programmable NOR gate 40 with diffusion anti-fuse arrangements a, b, c, d, e shown schematically by broken lines , and f.
• This exemplary embodiment is particularly suitable for subsequent test circuit modifications in which, by activating the anti-fuse arrangements a, b, c or d, e, f and correspondingly connecting the MOS transistors T or coupling them to a supply voltage V DD and a ground V ss a NAND or
• FIG. 11A shows a schematic plan view of the layout of such programmable NAND-NOR gates 39 and 40, the symbols of the individual layers being explained in FIG. 11B.

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• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)
• Fuses (AREA)
• Lining Or Joining Of Plastics Or The Like (AREA)

Priority Applications (6)

Applications Claiming Priority (2)

Publications (2)

Family

ID=7784979

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Cited By (3)

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• 1996
  • 1996-02-09 DE DE19604776A patent/DE19604776A1/de not_active Withdrawn
  • 1996-04-25 ES ES96914128T patent/ES2158310T3/es not_active Expired - Lifetime
• 1997
  • 1997-02-06 ES ES97914128T patent/ES2198559T3/es not_active Expired - Lifetime
  • 1997-02-06 UA UA98084340A patent/UA50755C2/uk unknown
  • 1997-02-06 WO PCT/DE1997/000235 patent/WO1997029515A2/de not_active Ceased
  • 1997-02-06 AT AT97914128T patent/ATE239302T1/de not_active IP Right Cessation
  • 1997-02-06 DE DE59709973T patent/DE59709973D1/de not_active Expired - Lifetime
  • 1997-02-06 JP JP52805297A patent/JP3288385B2/ja not_active Expired - Fee Related
  • 1997-02-06 EP EP97914128A patent/EP0879479B1/de not_active Expired - Lifetime
  • 1997-02-06 KR KR10-1998-0706091A patent/KR100414239B1/ko not_active Expired - Fee Related
  • 1997-02-06 CN CNB971921598A patent/CN1211856C/zh not_active Expired - Lifetime
  • 1997-02-10 IN IN229CA1997 patent/IN191121B/en unknown

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