GB2100057A - Method of forming conductive tracks in a semi-conductor body by annealing - Google Patents
Method of forming conductive tracks in a semi-conductor body by annealing Download PDFInfo
- Publication number
- GB2100057A GB2100057A GB8116157A GB8116157A GB2100057A GB 2100057 A GB2100057 A GB 2100057A GB 8116157 A GB8116157 A GB 8116157A GB 8116157 A GB8116157 A GB 8116157A GB 2100057 A GB2100057 A GB 2100057A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- tracks
- compound semiconductor
- layers
- localised
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000000137 annealing Methods 0.000 title description 3
- 150000001875 compounds Chemical class 0.000 claims abstract description 40
- 150000002500 ions Chemical class 0.000 claims abstract description 21
- 238000010894 electron beam technology Methods 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 238000010849 ion bombardment Methods 0.000 claims description 3
- 239000000615 nonconductor Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- -1 hydrogen ions Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229940036051 sojourn Drugs 0.000 description 2
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 1
- 239000005952 Aluminium phosphide Substances 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- LVQULNGDVIKLPK-UHFFFAOYSA-N aluminium antimonide Chemical compound [Sb]#[Al] LVQULNGDVIKLPK-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- PPNXXZIBFHTHDM-UHFFFAOYSA-N aluminium phosphide Chemical compound P#[Al] PPNXXZIBFHTHDM-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002772 conduction electron Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Physical Vapour Deposition (AREA)
Abstract
A method of forming conductive tracks (4) in a semiconductor device comprises providing a compound semiconductor body, bombarding the compound semiconductor region with ions to form at least one layer (1, 2) having a lower electrical conductivity, and selectively heating localised tracks (4) in the bombarded layer of the compound semiconductor region using a focused energy beam e.g. an electron beam (3) to anneal the localised tracks and thereby restore their electrical conductivity to provide conducting tracks (4) in the electrically insulating bombarded layer (1, 2). The method can produce tracks in each of two layers (1, 2) with either interconnections or insulated cross-overs. <IMAGE>
Description
SPECIFICATION
Forming conductive tracks in semiconductor devices
The electrical resistance of compound semiconductors increases sharply when the compound semiconductor is bombarded with ions.
The smallest ion is a hydrogen ion or simple proton. The bombardment of a compound semiconductor by ions leads to the conduction electrons in the compound semiconductor being more tightly bound and this decreases the electrical conductivity of the semiconductor.
When light ions such as protons are used to bombard the compound semiconductor this effect can be thought of as simply increasing the number of protons associated with the ions of the compound semiconductor which therefore provides an excess of protons which bind the available electrons more tightly. Using heavier ions such as oxygen for bombardment not only has this effect but also damages the crystal structure of the compound semiconductor and this, in turn, leads to a further incease in the electrical resistance of the semiconductor. Typical compound semiconductors that exhibit this effect are dual compound semiconductors such as gallium arsenide, gallium phosphide, gallium antimonide, indium phosphide, indium antimonide, aluminium phosphide, aluminium antimonide and cadmium telluride, and other ternary alloys such as gallium aluminium arsenide.
It is known that the electrical properties of the bombarded compound semiconductor are restored when the compound semiconductor is heated and annealed. The degree of bombardment governs the change in electrical resistance that is created so that the greater the dose of ions used to bombard the compound semiconductor the greater the decrease in electrical conductivity that is created.
Equally, the degree of reduction in conductivity is also related to the mass of the ions used to bombard the compound semiconductor.
The heavier the ion, the greater the damage and hence the greater the conductivity reduction induced for a given dose.
It has also been found that the greater the degree of bombardment that is given to the compound semiconductor and consequently the greater the electrical resistance of the compound semiconductor, the greater the temperature to which the compound semiconductor has to be raised to restore the electrical properties and increase its conductivity.
According to this invention, a method of forming conductive tracks in a semiconductor device comprises providing a compound semiconductor region, bombarding the compound semiconductor region with ions to form a layer having a lower electrical conductivity, and selectively heating localised tracks in the bombarded layer of the compound semiconductor region using a focused energy beam to anneal the localised tracks and thereby restore their electrical conductivity to provide conducting tracks in the bombarded layer.
Thus, by selectively annealing tracks in the bombarded layer of the compound semiconductor conductive paths can be provided through the electrically insulated bombarded compound semiconductor layer and these conductive paths can be used as a wiring in a semiconductor device.
According to a second aspect of this invention a method of forming conductive tracks in a semiconductor device comprises providing a compound semiconductor region bombarding the compound semiconductor region with a dose of ions having a first energy to form a first layer having a low electrical conductivity, bombarding the compound semiconductor region with a dose of ions having a second energy which is lower than the first energy to form a second layer having a low electrical conductivity, the first layer thus being deeper than the second layer and the degree of bombardment received by the first layer being less than that received by the second layer, selectively heating localised tracks in the first layer to a first temperature using a first energy beam, the first temperature being sufficient to anneal the first layer to restore its electrical conductivity and provide conductive tracks in the first layer without substantially affecting the second layer, and selectively heating localised tracks in the second layer to a second temperature using a focused energy beam, the second temperature being sufficient to anneal the second layer to restore its electrical conductivity and provide conducting tracks in the second layer.
The selective heating of the localised tracks in the second layer to the second temperature using the focused energy beam may be arranged so that it heats both the first and second layer to the second temperature thereby forming a conductive path extending between both the first and second layers and any conductive paths in the first and second layers or, alternatively, the selective heating of localised tracks in the second layer to the second temperature may be arranged to restore the electrical conductivity of the second layer without substantially affecting the first layer. In this latter case criss-crossing but not connecting conductive paths can be provided in the first and second layers and this obviously provides great flexibility in the arrangement and interconnections of the conductive paths in the first and second layers.By using the former technique, electrical connections can be made between conductive paths in the first and second layers, for example, at their crossing points.
The focused energy beam may be formed by a focused laser beam but preferably it is formed by an electron beam. One way of arranging the electron beam to heat localised tracks in the bombarded layers is to have a pulsed electron beam and to move the focusing spot of the electron beam along predetermined path between pulses of the electron beam. In this way a series of overlapping pulses are provided by the electron beam which, taken together, describe a path along the bombarded layers. In this case, the duration of the pulses will be relatively longer and the energy of the electron beam lower when it is only required to heat the first layer to a first temperature whereas the duration of the pulses will be shorter and the energy of the electron beam higher when it is required to only heat the second layer to the second temperature without substantially affecting the first layer.Where it is required to interconnect conductive tracks in the first and second layers the pulses will have a longer duration and a higher energy thereby heating both the first and second layers to the second temperature.
Another way of arranging this is to have a continuously operating energy beam and then moving this over the bombarded layer to "draw" the conductive tracks in the first and second layers.
This invention has particular application to semiconductor devices having their substrate formed by a compound semiconductor but it is also possible to provide a top layer of a compound semiconductor by, for example, epitaxial deposition. Preferably the ion bombardment of the compound semiconductor region is sufficient to turn the compound semiconductor region into an electrical insulator.
Thus, it is preferred that the bombardment is sufficient to cause the conductivity of the compound semiconductor region to be less than 10-6mhos per sq. cm. When the compound semiconductor is bombarded to form two different layers the degree of bombardment of the second layer may be increased by using heavier ions for the bombardment, for example hydrogen ions or protons may be used to create the first layer and oxygen ions used to create the second layer with the dose used for both layers similar or, alternatively, a higher dose of the same ion that is used to make the first layer may be used to create the second layer and in this case the dose should probably be an order of magnitude greater.
The different depths of ion bombardment to form the first and second layers could theoretically be achieved by changing the crystal orientation so that the first layer may be created by directing ions along an open direction of the crystal lattice by ion beam channelling and thereafter the second, shallower layer could be formed by directing ions from a different direction but with the same energy.
Naturally, a greater dose would be required to form the second layer. This method, whilst possible, seems unlikely to be used since it requires the use of sophisticated alignment apparatus.
It is possible to create more than two layers and, thereafter, create conductive tracks in each of the layers provided that there is sufficient difference in the degree of bombardment in each of the layers to enable each of the layers to be annealed independently. However, in practice, two layers are usually sufficient.
The accompanying drawings which are all partial sectional elevations through semiconductor wafers illustrate the formation of conductive tracks in accordance with this invention.
Figure 1 shows a semiconductor wafer after bombardment with first, high energy ions to produce a first layer 1 and then with a higher dose of low energy ions to produce a second layer 2. When such a wafer is subjected to an electron beam 3 having a relatively low energy this heats both the layer 2 and the layer 1 to a temperature which is sufficient to anneal the layer 1 and form conductive tracks in the first layer 1 as shown by the crosshatched region 4, but to anneal the layer 2 as shown in Fig. 2. If the electron beam has a greater energy so that the temperature it induces is greater but, for example, if the sojourn time of the beam is less, the second layer 2 adjacent the surface of the wafer is heated to a sufficient extent to anneal the second layer 2 to form a conducting track 5 in the second layer 2 as shown in Fig. 3. One way of achieving this is to pulse the electron beam 3. Finally, if a high energy electron beam 3 is used and a greater sojourn time is used then a conductive track 6 is formed by annealing areas of both the second 2, and first 1 layers of the wafer to provide a conducting region that connects paths in the first layer 1 with paths in the second layer 2 or to enable contacts to be made with the conductive paths in the first layer 1. This is shown in
Fig. 4
Claims (9)
1. A method of forming conductive tracks in a semiconductor device comprising providing a compound semiconductor region, bombarding the compound semiconductor region with ions to form a layer having a lower electrical conductivity, and selectively heating localised tracks in the bombarded layer of the compound semiconductor region using a focused energy beam to anneal the localised tracks and thereby restore their electrical conductivity to provide conducting tracks in the bombarded layer.
2. A method of forming conductive tracks in a semiconductor device comprising providing a compound semiconductor region, bombarding the compound semiconductor region with a dose of ions having a first energy to form a first layer having a low electrical con ductivity, the first layer thus being deeper than the second layer and the degreee of bombardment received by the first layer being less than that received by the second layer, selectively heating localised tracks in the first layer to a first temperature using a first energy beam, the first temperature being sufficient to anneal the first layer to restore its electrical conductivity and provide conductive tracks in the first layer without substantially affecting the second layer, and selectively heating localised tracks in the second layer to a second temperature using a focused energy beam, the second temperture being sufficient to anneal the second layer to restore its electrical conductivity and provide conducting tracks in the second layer.
3. A method according to claim 2, in which the selective heating of the localised tracks in the second layer to the second temperature using the focused energy beam is arranged so that it heats both the first and second layer to the second temperature thereby forming a conductive path extending between both the first and second layers and any conductive paths in the first and second layers so that electrical connections can be made between conductive paths in the first and second layers, for example, at their crossing points.
4. A method according to claim 2, in which the selective heating of localised tracks in the second layer to the second temperature is arranged to restore the electrical conductivity of the second layer without substantially affecting the first layer so that criss-crossing but not connecting conductive paths can be provided in the first and second layers.
5. A method according to any one of the preceding claims, in which the focused energy beam is formed by an electron beam.
6.. A method according to claim 5, in which the electron beam heats localised tracks in the bombarded layers by having a pulsed electron beam and moving the focusing spot of the electron beam along a predetermined path beteen pulses of the electron beam, so that a series of overlapping pulses are provided by the electron beam which taken together, describe a path along the bombarded layers.
7. A method according to claim 5, in which the energy beam is continuously operating moves over the bombarded layer to "draw" the conductive tracks in the bombarded layers.
8. A method according to any one of the preceding claims, in which the ion bombardment of the compound semiconductor region is sufficient to turn the compound semiconductor region into an electrical insulator.
9. A method according to claim 1, substantially as described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8116157A GB2100057A (en) | 1981-05-27 | 1981-05-27 | Method of forming conductive tracks in a semi-conductor body by annealing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8116157A GB2100057A (en) | 1981-05-27 | 1981-05-27 | Method of forming conductive tracks in a semi-conductor body by annealing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2100057A true GB2100057A (en) | 1982-12-15 |
Family
ID=10522081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8116157A Withdrawn GB2100057A (en) | 1981-05-27 | 1981-05-27 | Method of forming conductive tracks in a semi-conductor body by annealing |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2100057A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0194519A2 (en) * | 1985-03-08 | 1986-09-17 | Energy Conversion Devices, Inc. | Electric circuits having repairable circuit lines and method of making the same |
| EP0263574A1 (en) * | 1986-09-08 | 1988-04-13 | THORN EMI North America Inc. | A method of manufacturing a semiconductor device, and a semiconductor device, having at least one selectively actuable conductive line |
| US4835118A (en) * | 1986-09-08 | 1989-05-30 | Inmos Corporation | Non-destructive energy beam activated conductive links |
| WO1997029515A2 (en) * | 1996-02-09 | 1997-08-14 | Siemens Aktiengesellschaft | Separable connecting bridge (fuse) and connectable line interruption (anti-fuse) and process for producing and activating a fuse and an anti-fuse |
| US7332030B2 (en) * | 2002-01-16 | 2008-02-19 | Michel Bruel | Method of treating a part in order to alter at least one of the properties thereof |
-
1981
- 1981-05-27 GB GB8116157A patent/GB2100057A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0194519A2 (en) * | 1985-03-08 | 1986-09-17 | Energy Conversion Devices, Inc. | Electric circuits having repairable circuit lines and method of making the same |
| EP0194519A3 (en) * | 1985-03-08 | 1988-08-03 | Energy Conversion Devices, Inc. | Electric circuits havin repairable circuit lines and method of making the same |
| EP0263574A1 (en) * | 1986-09-08 | 1988-04-13 | THORN EMI North America Inc. | A method of manufacturing a semiconductor device, and a semiconductor device, having at least one selectively actuable conductive line |
| US4835118A (en) * | 1986-09-08 | 1989-05-30 | Inmos Corporation | Non-destructive energy beam activated conductive links |
| WO1997029515A2 (en) * | 1996-02-09 | 1997-08-14 | Siemens Aktiengesellschaft | Separable connecting bridge (fuse) and connectable line interruption (anti-fuse) and process for producing and activating a fuse and an anti-fuse |
| WO1997029515A3 (en) * | 1996-02-09 | 1997-09-18 | Siemens Ag | Separable connecting bridge (fuse) and connectable line interruption (anti-fuse) and process for producing and activating a fuse and an anti-fuse |
| US7332030B2 (en) * | 2002-01-16 | 2008-02-19 | Michel Bruel | Method of treating a part in order to alter at least one of the properties thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4339869A (en) | Method of making low resistance contacts in semiconductor devices by ion induced silicides | |
| KR100301273B1 (en) | Ultra-shallow semiconductor junction formation | |
| US4704785A (en) | Process for making a buried conductor by fusing two wafers | |
| US4843034A (en) | Fabrication of interlayer conductive paths in integrated circuits | |
| US9754860B2 (en) | Redistribution layer contacting first wafer through second wafer | |
| JP2002289550A (en) | Activating method for impurity ion implanted layer | |
| EP0162061B1 (en) | Fabrication of group iii-v compound semiconductor devices having high and low resistivity regions | |
| JP2009194197A (en) | Semiconductor device and its manufacturing method | |
| GB2100057A (en) | Method of forming conductive tracks in a semi-conductor body by annealing | |
| KR940000921B1 (en) | Mobile ion getterer for metal coductors | |
| JPH02275624A (en) | Ohmic electrode and its forming method | |
| KR920008124B1 (en) | Manufacturing method of semiconductor device containing inp | |
| US5047831A (en) | Reduced resistance contact region for semiconductor device | |
| US3920485A (en) | Thin insulating film containing metallic particles | |
| US4599791A (en) | Method of making integrated circuits employing proton-bombarded AlGaAs layers | |
| EP0263574A1 (en) | A method of manufacturing a semiconductor device, and a semiconductor device, having at least one selectively actuable conductive line | |
| KR102421173B1 (en) | Contact of semiconductor device and contact formation method of semiconductor device | |
| Peacock | Ion beam suppression of hillock growth in aluminium thin films | |
| US20090166675A1 (en) | Strain engineering in semiconductor components | |
| JP2007109785A (en) | Semiconductor device and its manufacturing method | |
| KR100195326B1 (en) | Structure of metal wiring & forming method thereof | |
| Miyao et al. | Low Temperature Annealing Characteristics of Phosphorus-Implanted Silicon | |
| Harrison et al. | Applications of a continuous wave incoherent light source (CWILS) to semiconductor processing | |
| CN103733310B (en) | Semiconductor element and the manufacture method of semiconductor element | |
| KR100374230B1 (en) | Method for forming intermetal dielectric using electron flux radiation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |