DE3783404T2 - Leitende aktivierungsverbindungen fuer halbleiteranordnungen. - Google Patents

Leitende aktivierungsverbindungen fuer halbleiteranordnungen.

Info

Publication number
DE3783404T2
DE3783404T2 DE8787111603T DE3783404T DE3783404T2 DE 3783404 T2 DE3783404 T2 DE 3783404T2 DE 8787111603 T DE8787111603 T DE 8787111603T DE 3783404 T DE3783404 T DE 3783404T DE 3783404 T2 DE3783404 T2 DE 3783404T2
Authority
DE
Germany
Prior art keywords
semiconductor arrangements
guided activation
activation connections
connections
guided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787111603T
Other languages
English (en)
Other versions
DE3783404D1 (de
Inventor
Ryoichi Fujitsu Limited Mukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3783404D1 publication Critical patent/DE3783404D1/de
Publication of DE3783404T2 publication Critical patent/DE3783404T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/093—Laser beam treatment in general

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8787111603T 1986-08-12 1987-08-11 Leitende aktivierungsverbindungen fuer halbleiteranordnungen. Expired - Fee Related DE3783404T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61189094A JPS6344739A (ja) 1986-08-12 1986-08-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3783404D1 DE3783404D1 (de) 1993-02-18
DE3783404T2 true DE3783404T2 (de) 1993-05-06

Family

ID=16235236

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787111603T Expired - Fee Related DE3783404T2 (de) 1986-08-12 1987-08-11 Leitende aktivierungsverbindungen fuer halbleiteranordnungen.

Country Status (5)

Country Link
US (1) US4968643A (de)
EP (1) EP0256494B1 (de)
JP (1) JPS6344739A (de)
KR (1) KR910004038B1 (de)
DE (1) DE3783404T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070392A (en) * 1988-03-18 1991-12-03 Digital Equipment Corporation Integrated circuit having laser-alterable metallization layer
US5250465A (en) * 1991-01-28 1993-10-05 Fujitsu Limited Method of manufacturing semiconductor devices
US5451811A (en) * 1991-10-08 1995-09-19 Aptix Corporation Electrically programmable interconnect element for integrated circuits
US5321322A (en) * 1991-11-27 1994-06-14 Aptix Corporation Programmable interconnect architecture without active devices
WO1993012582A1 (en) * 1991-12-13 1993-06-24 Knights Technology, Inc. Programmable logic device cell and method
JPH0799791B2 (ja) * 1992-04-15 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 透明基板上の回路ライン接続方法
JPH06124913A (ja) * 1992-06-26 1994-05-06 Semiconductor Energy Lab Co Ltd レーザー処理方法
KR960009996B1 (ko) * 1992-08-24 1996-07-25 금성일렉트론 주식회사 반도체 소자의 리페어장치 및 그 배치방법
US5453402A (en) * 1992-12-15 1995-09-26 Advanced Micro Devices, Inc. Selective metal via plug growth technology for deep sub-micrometer ULSI
JPH06260441A (ja) * 1993-03-03 1994-09-16 Nec Corp 半導体装置の製造方法
US5920789A (en) * 1994-10-11 1999-07-06 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
JPH09510320A (ja) 1994-03-10 1997-10-14 マサチユセツツ・インスチチユート・オブ・テクノロジー 接続用導電リンクの製造方法
US5585602A (en) * 1995-01-09 1996-12-17 Massachusetts Institute Of Technology Structure for providing conductive paths
US5861325A (en) * 1994-03-10 1999-01-19 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
US5940727A (en) * 1994-10-11 1999-08-17 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
TW278229B (en) * 1994-12-29 1996-06-11 Siemens Ag Fuse structure for an integrated circuit device and method for manufacturing a fuse structure
JP3160198B2 (ja) * 1995-02-08 2001-04-23 インターナショナル・ビジネス・マシーンズ・コーポレ−ション デカップリング・コンデンサが形成された半導体基板及びこれの製造方法
US5731047A (en) * 1996-11-08 1998-03-24 W.L. Gore & Associates, Inc. Multiple frequency processing to improve electrical resistivity of blind micro-vias
JPH10229125A (ja) * 1997-02-14 1998-08-25 Nec Corp 半導体装置
US6288437B1 (en) * 1999-02-26 2001-09-11 Micron Technology, Inc. Antifuse structures methods and applications
US6472253B1 (en) 1999-11-15 2002-10-29 Vlsi Technology, Inc. Programmable semiconductor device structures and methods for making the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780738A (en) * 1980-11-07 1982-05-20 Seiko Epson Corp Semiconductor integrated device
US4585490A (en) * 1981-12-07 1986-04-29 Massachusetts Institute Of Technology Method of making a conductive path in multi-layer metal structures by low power laser beam
JPS5996746A (ja) * 1982-11-26 1984-06-04 Hitachi Ltd 半導体装置およびその製造方法
ATE56310T1 (de) * 1984-06-27 1990-09-15 Contraves Ag Verfahren zur herstellung eines basismaterials fuer eine hybridschaltung.
US4681795A (en) * 1985-06-24 1987-07-21 The United States Of America As Represented By The Department Of Energy Planarization of metal films for multilevel interconnects
US4814578A (en) * 1985-06-24 1989-03-21 The United States Of America As Represented By The Department Of Energy Planarization of metal films for multilevel interconnects
US4674176A (en) * 1985-06-24 1987-06-23 The United States Of America As Represented By The United States Department Of Energy Planarization of metal films for multilevel interconnects by pulsed laser heating
JPS62293740A (ja) * 1986-06-13 1987-12-21 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0256494A2 (de) 1988-02-24
EP0256494A3 (en) 1988-07-27
EP0256494B1 (de) 1993-01-07
US4968643A (en) 1990-11-06
JPS6344739A (ja) 1988-02-25
JPH058864B2 (de) 1993-02-03
KR910004038B1 (ko) 1991-06-22
DE3783404D1 (de) 1993-02-18
KR880003407A (ko) 1988-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee