Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/131—Digitally controlled
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K21/00—Details of pulse counters or frequency dividers
  • H03K21/08—Output circuits
  • H03K21/12—Output circuits with parallel read-out

Definitions

• the present invention balances the power consumption of a circuit configured by a semiconductor integrated circuit (IC) such as a semiconductor integrated circuit (CMOS ⁇ IC) having a CMOS structure (complementary MOS), and It relates to a heat balance circuit used to maintain a constant temperature.
• IC semiconductor integrated circuit
• CMOS ⁇ IC semiconductor integrated circuit having a CMOS structure (complementary MOS)
• CMOS structure complementary MOS
• a clock signal (pulse) having a predetermined delay time generated from a reference timing signal (pulse) is generated in order to define test timing.
• a test pattern signal is generated at the timing of the clock pulse, and the test is performed by applying the test pattern signal to the memory under test.
• a delay circuit that applies a delay time to a reference timing pulse includes a step-variable delay circuit that can switch the delay time step by step using the clock pulse pulse interval as a delay unit, and a clock pulse pulse interval.
• a small delay circuit and a force s ' that can provide a small delay time within a short pulse interval are used, and a combination of the delay time of the step-variable delay circuit and the delay time of the minute delay circuit is used. It is configured so that an arbitrary delay time can be given.
• the present invention relates to an improvement of the latter minute delay circuit.
• This kind of minute delay circuit generally uses an active element array formed as a CMOS MOS IC.
• the reason why the CMO S-IC is used as a delay circuit is that the CMO S-IC has extremely low power consumption s in a no-signal state, and therefore can suppress the heat generation.
• An object of the present invention is to provide a thermal balance circuit that can provide a constant delay time to an input signal supplied to the delay circuit even if the frequency of the signal changes.
• Another object of the present invention is to provide a dummy circuit having the same circuit configuration as a delay circuit in the vicinity of the delay circuit so that the amount of power consumed by both circuits even if the frequency of an input signal supplied to the delay circuit changes. Is to provide a heat balance circuit capable of maintaining the temperature substantially constant.
• the object is to provide a delay circuit to which a first pulse signal to be delayed is supplied, a first pulse supply path to supply the first pulse signal to the delay circuit, A counter that counts the number of first pulse signals supplied through one pulse supply path for a certain period of time, and obtains a difference between the count value of the first pulse signal counted by this counter and a predetermined value A second pulse signal having the same number as the value of the difference calculated by the calculating means, provided near the delay circuit, and a dummy circuit having the same circuit configuration as the delay circuit. Achieved by providing a balance circuit.
• the delay circuit is formed as a semiconductor integrated circuit such as a CMOS IC, and the frequency of the second pulse signal is equal to or higher than the highest frequency of the first pulse signal to be delayed. Are also selected for higher frequencies. Then, even if the frequency of the first pulse signal to be delayed changes, the amount of power consumed by both the delay circuit and the dummy circuit is maintained at a constant value.
• the number of first pulse signals input within a certain time is counted, and the number of second pulse signals equal to the difference between the counted value and a preset value is counted. Is given to the dummy circuit, so that even if the frequency of the first pulse signal to be delayed changes, the power consumption of the entire thermal balance circuit remains constant. Can be maintained. Thus, even if the frequency of the first pulse signal to be delayed changes, the delay time given to the first pulse signal can be maintained at a constant value.
• FIG. 1 is a block diagram showing one embodiment of a heat balance circuit according to the present invention.
• FIG. 2 is a waveform diagram for explaining the operation of the thermal balance circuit of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
• FIG. 1 shows an embodiment of a heat balance circuit according to the present invention.
• the thermal balance circuit includes a delay circuit 10 for giving a predetermined delay time to an input signal, and a dummy circuit provided close to the delay circuit 10 and configured by the same circuit as the delay circuit 10. Including 1 and 1.
• the delay circuit 10 and the dummy circuit 11 are formed as one CMOS IC.
• a first pulse supply path 12 is connected to the delay circuit 10, and a first pulse signal CP 1 to be delayed is input to the delay circuit 10 through the first pulse supply path 12.
• the second pulse supply path 13 is connected to the dummy circuit 11 via an AND gate 14 of a pulse extraction circuit 27 described later, and a second pulse signal CP 2 is supplied to the second pulse supply path 13.
• Frequency F 2 of the second pulse signal CP 2 supplied to the dummy circuit 1 1 is equal to the highest frequency F m of the first pulse signal CP 1 to be supplied to the delay circuit 1 0 or more frequencies Is selected. That is, F 2 ⁇ F m is selected.
• Te convex an example in which the frequency F 2 of the second pulse signal CP 2 is selected as the first higher value than the highest frequency F m of the pulse signal CP 1.
• a counter 15 is connected to the first pulse supply path 12 via an AND gate 22.
• the counter 15 performs an operation of counting the first pulse signal CP1 input to the delay circuit 10 through the first pulse supply path 12 for a predetermined period of time.
• a clock means 16 is provided, and the clock means 16 causes the counter 15 to perform a counting operation for a fixed time.
• the five output terminals Q i to Q 5 of the counter 17 are connected to the input of the AND gate 18, and the remaining output terminal Q 6 of the counter 17 is connected to one input of the AND gate 19.
• the other input of the AND gate 19 is connected to the second pulse supply path 13, and its output is connected to the clock terminals CL of the counters 15 and 17, respectively.
• the output of the AND gate 18 is connected to one input of the AND gate 22 via the inverter 21. Therefore, the AND gate 18 is used only when all of the outputs of the five output terminals QQ to Q5 of the counter 17 are at a logic high level (hereinafter abbreviated as H) (this corresponds to 32 counts).
• H logic high level
• the H signal Since the H signal is output, it detects that the count value of the counter 17 has reached 32.
• the detection output (H signal) of the AND gate 18 is supplied to one input terminal of the AND gate 22 connected to the input side of the counter 15 through the inverter 21. Since the other input terminal of the AND gate 22 is connected to the first pulse supply path 12, when the count value of the counter 17 reaches 32 counts, the output power of the inverter 21? It falls to a logic low level (hereinafter abbreviated as L) and controls the AND gate 22 to be closed. As a result, the counter 15 stops counting.
• L logic low level
• the count value counted by the counter 15 is supplied to the operation means 23 at the subsequent stage.
• the calculating means 23 calculates a difference between the value counted by the counter 15 and a predetermined value, and supplies this difference signal to a subsequent pulse extraction circuit 27 via a NAND gate 24. It works like that.
• the pulse extraction circuit 27 is composed of a flip-flop 25, an inverter 26, and an AND gate 14. An operation of extracting the second pulse signal CP2 of a number equal to the difference value from the determined value and inputting the same to the dummy circuit 11 is performed.
• a configuration using a counter that can be preset is shown as the arithmetic means 23.
• the load input terminal LD of the presettable counter is supplied with the output signal from the AND gate 18 of the timing means 16, and the input terminal is supplied with the second pulse signal CP 2.
• this presettable counter five output terminals Q 5 are connected to the input terminals of the NAND gate 24, so that the five output terminals Q i to Q 5 are similar to the counter 17 of the timer 16.
• the full count value (32 counts) is when all of the outputs at H are high.
• the count value of the counter 17 is read into the arithmetic means 23 when the count value of the counter 17 reaches 32 and the AND gate 18 outputs the H signal.
• the counter constituting the calculating means 23 stops at the state where the second pulse signal CP 2 has been counted 32 times last time. This is because the frequency of the second pulse signal is higher than the frequency of the first pulse signal as described above. Therefore, the NAND gate 24 is in the state of outputting the L signal, and the flip-flop 25 of the pulse extraction circuit 27 reads the H signal whose polarity has been inverted. As a result, the flip-flop 25 outputs the H signal from its Q output terminal, and the H signal is inverted to the L signal by the inverter 26 and supplied to the AND gate 14, so that the AND gate 14 is in a closed state. It is in.
• the calculating means 23 reads the count value of the counter 15, the count value is smaller than 32 counts, and the NAND gate 24 outputs an H signal.
• the flip-flop 25 reads the L signal and outputs the L signal to its output terminal Q. Since the polarity of this L signal output is inverted by the inverter 26, the H signal is given to the AND gate 14, and the AND gate 14 is controlled to be open.
• the AND gate 14 is controlled to be open at the same time that the arithmetic means 23 reads the count value of the counter 15, and the second pulse signal ⁇ ? 2 kami 'supplied.
• the arithmetic means 23 starts counting the second pulse signal CP2 from the read count value of the counter 15 (because it is smaller than 32 counts).
• the calculation means 23 reaches the full count value (32 counts)
• the output of the NAND gate 24 becomes L. Since the signal is read as an H signal, the output of the inverter 26 falls to L and the AND gate 14 is controlled to be closed.
• the AND gate 14 is opened when the counter 17 counts 32 second pulse signals CP 2, and the second pulse signal CP 2 is supplied to the dummy circuit 11 1 begins to supply the count value of the operation means 23 is controlled to the closed state at the time T 2 has reached the Furukaun preparative value, it stops the second supply of the pulse signal CP 2 to the dummy circuit 1 1. Therefore, in the illustrated embodiment, the flip-flop 25, the inverter 26 and the AND gate 26 constitute a pulse extraction circuit 27 for extracting the second pulse signal.
• the frequency F 2 of the second pulse signal CP 2 shown in FIG. 2 B than the highest frequency F m of the first pulse signal CP 1 shown in FIG. 2 A is a high value Is set. That is, F m ⁇ F 2 .
• the signal LOAD shown in FIG. 2C is a load signal supplied from the AND gate 18 to the calculating means 23 when the counter 17 reaches the full count value, and the signal CLEAR shown in FIG. Indicates the clear signal supplied to the clear input terminal CL of the counters 15 and 17 from.
• the delay circuit and the dummy circuit are configured as one CMOS IC.
• the present invention can be applied to a case where the delay circuit and the dummy circuit are configured by an integrated circuit other than the CMOS and IC, and the same operation and effect can be obtained.
• the number of the first pulse signals CP1 supplied to the delay circuit within a certain period of time is counted by the counter 15, and the counted value is set to a predetermined set value ( Since the number N 2 of second pulse signals CP 2 is supplied to the dummy circuit 11, the number N 2 of the second pulse signals CP 2 is equal to the number insufficient for the number of the counters constituting the arithmetic means 23.
• the total number of pulses applied to both dummy circuits 11 can be maintained at a constant value. This relationship is maintained even if the frequency of the first pulse signal CP1 changes.
• the delay time of the delay circuit 10 can be maintained at a constant value even when the frequency of the first pulse signal CP1 changes.

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• 1995
  • 1995-06-02 JP JP13640795A patent/JP3552176B2/ja not_active Expired - Fee Related
• 1996
  • 1996-05-31 KR KR1019970700672A patent/KR100211230B1/ko not_active IP Right Cessation
  • 1996-05-31 DE DE19680526T patent/DE19680526C2/de not_active Expired - Fee Related
  • 1996-05-31 WO PCT/JP1996/001481 patent/WO1996038911A1/ja active IP Right Grant
  • 1996-06-17 TW TW085107299A patent/TW295630B/zh not_active IP Right Cessation

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