Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
  • H03F1/3217—Modifications of amplifiers to reduce non-linear distortion in single ended push-pull amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
  • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
  • H03F3/3069—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor the emitters of complementary power transistors being connected to the output
  • H03F3/3076—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor the emitters of complementary power transistors being connected to the output with symmetrical driving of the end stage
  • H03F3/3079—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor the emitters of complementary power transistors being connected to the output with symmetrical driving of the end stage using parallel power transistors

Definitions

• the present invention includes an input stage, a voltage amplifying stage, and at least one SEPP output stage having an Aiura-shaped wide element, and a first and a second relay output terminal of the voltage wide stage.
• Conventional amplifiers include, for example, an input stage 10, a voltage width stage 20, and a SEFP (single 'end' push-pull) output stage 30, as shown in FIG. Is provided.
• SEFP single 'end' push-pull
• the input stage 10 is connected to the two FETs i1 and 12 of the monolithic IC, the input terminal 13 connected to the gate of the FET 11, the input terminal 13 and the ground.
• the input resistance 14 connected between the power supply and the common source of FETs 11 and 12 and a negative voltage source, the resistance 15 connected between 1 V CC and the positive voltage source + V CC power, that have a et FET 1 1 and 1 2 of the resistor 1 6 and 1 7 is connected to the de Tray down.
• Negative feedback resistors 18 and 19 that determine the amplification factor of this amplifier are connected to the gate of FET 12 between the ground and the output terminal. It is done.
• the two voltage amplification stages are connected to a PNP transistor 2 ⁇ ⁇ ⁇ having a base surrounded by the drain of the FET 11, and to a drain of F ⁇ 2 12.
• ⁇ ⁇ ⁇ ⁇ Transistor 22 with the read-in base, and the common emitters of these ⁇ Transistors 21 and 22
• a resistor 23 connected between the voltage source + Vcc and a collector and a base read from the collector of the transistor 22;
• both emitters are connected to a negative voltage source of 1 Vcc.
• the collector current of the ⁇ ⁇ transistor 22 has the same absolute value as that of the ⁇ ⁇ transistor 25. Also, the collector of the transistor transistor 22 forms the first intermediate output terminal I, and the collector of the transistor transistor 25 second in that to form a ⁇ force end I 2.
• the S ⁇ ⁇ ⁇ output stage 30 is connected to a positive voltage source + V cc and has a dc collector and a direct connection, and an NPN transistor 31 of ⁇ . 3 2, negative voltage source - and V c PNP bets each with da one Li down tons connect Se' been Collector power to c run-g is te 3 3, 3 4, output A terminal 35 and a first resistor 36, which is directly plugged into the output terminal 35 and is also surrounded by an emitter of the NPN transistor 32, is connected to the output terminal 35. A second resistor 37 connected directly to the input terminal 35 and connected to an emitter of the PNP transistor 34.
• the contact point between the emitter of the NPN transistor 31 and the base of the NPN transistor 32 is read to the output terminal 35 via the resistor 38.
• the emitter of the PNP transistor 33 and the total of the emitter of the PNP transistor 34 The connection point of the resistor is connected via the resistor 39.
• a constant voltage type bias circuit 26 is connected between the second intermediate output terminal I2 and the second intermediate output terminal I2 connected to the (second control terminal).
• the bias circuit 26 is connected to the collector connected to the base of the NPN transistor 31 and the base connected to the base of the PNP transistor 32.
• NPN transistor 27 for temperature compensation having a mounted emitter and the bases of NPN transistor 31 and 27 are connected to each other. It has a variable resistor 28 and fixed resistors 29 connected to the bases of the NPN transistor 27 and the PNP transistor 33, respectively.
• the idle current flowing between the collector of the NPN transistor 32 and the collector of the PNP transistor 34 must be adjusted by the variable resistors 2 and 8. It will be adjusted to AB class.
• the collector of the NPN transistor 27 has a variable resistor 28 and a fixed ffi resistance 2 9 is added, the sum is divided by the resistance of fixed resistor 29, and the resulting value is multiplied by the Vbe of NPN transistor 27. is there . Therefore, in the conventional constant voltage bias circuit 26, since V be is substantially constant, the bias voltage between the first and second intermediate output terminals is one; . -This conventional class AB amplifier, for example, when N.PN transistors 31 and 32 are driven to the plus side, PNP transistors 33 and 3 Is also driven to the plus side via the constant voltage bias circuit. Immediately, as the base current of the NPN transistor 31.32 increases, the collector current also increases and the NPN transistor increases. Evening 3 1.
• the base-emitter voltage Vbe of 32 also increases. Furthermore, the voltage of the first resistor 36 leap also increases due to the increased collector current. As a result, since the voltage between the collector and the emitter of the NPN transistor 27- is substantially constant, the voltage between each emitter and base of the PNP transistor 33.34 is The voltage applied to PNP transistor 2 decreases to 0FF.
• bipolar transistors such as NPN and PNP transistors, transfer holes or electrons when transitioning from the 0 FF state to the 0 N state. It takes time to refill the carrier. At the time of this filling P says? Affects the characteristics of the amplifier.
• the PNP transistors 33 and 34 are in direct proportion to the normal collector m flow when driven to the minus side from the completely turned down state of 0FF.
• a carrier current that fills the transistor with electrons is required. This carrier current degrades the operational characteristics of the amplifier.
• this carrier current can cause the NpN transistors 31, 32 and the PNP transistor to be read when the heater is read into an inductive load such as a speed. Time shift occurs when the registers 33 and 34 are 0 FF at 0 FF, which adversely affects the sound quality. Therefore, the conventional AB class turret has the drawback of deteriorating the sound quality that cannot be measured with actual measuring instruments because it uses a constant-voltage bias circuit.
• the object of the present invention is to provide an amplifier that eliminates the problem caused by the carrier current by using a constant current bias circuit. are doing.
• This constant-current bias circuit has the improved sound quality in the embodiment applied to a commercially available Class B or AB class amplifier. It offers something more outstanding, but is more difficult to adjust.
• a constant voltage bias circuit having an internal resistance higher than that of a conventional constant voltage bias circuit and a constant current bias circuit of the present invention are connected in parallel to form a conventional constant voltage bias circuit. This is to provide a constant current bias circuit that takes over part of the current flowing through the circuit.
• a feedback type constant current bias circuit that can control the current value by voltage is used, and this control voltage is applied to the emitter resistor of the power transistor, that is, the second resistor.
• a negative feedback circuit that is obtained from the average voltage generated between the second resistor and the second resistor.
• an input stage having an inverting input terminal and a non-inverting input terminal, a voltage amplifying stage operatively connected to the input stage, and a third stage of the voltage wide stage.
• a SEPP output stage having first and second control terminals respectively connected to the first and second relay output terminals,
• a constant current bias circuit is connected between the first and second middle output terminals to absorb a current bypassed between the middle output terminals.
• An amplifier is provided.
• a constant current bias circuit and a constant voltage bias circuit according to the present invention may be connected in parallel to the first and second intermediate output terminals.
• the SEPP output stage is connected to the first amplification element, the second width element having a different polarity from the first width element, the output terminal, and the output terminal.
• the first resistor connected directly to the common electrode side of the first amplifying element as well as being directly connected to the output terminal and connected to the common electrode side of the second wide element.
• a second resistor and e
• the current value is controlled by the voltage, and in the constant current bias circuit, the voltage appearing across the first and second resistors due to the integrator circuit is suspected.
• An amplifier is provided for controlling a current applied to bypass the current between the first and second middle output terminals to control the bias current flowing through the first and second resistors. Has been done.
• the present invention discloses two types of basic circuits using a constant current bias circuit.
• the operating temperature range of the electronic device is low, it is set to Q to 70, and the basic value A and the variation range B (A ⁇ B) of the bypass current in this temperature range are obtained. Then, the basic value C of the overcurrent of the constant current bias circuit and the variation width D (C soil D) are found, and the current setting value of the constant current bias circuit is (C + D) ⁇ A. It is set to be established, and the remaining bypass current is absorbed by the constant voltage bias circuit whose internal resistance is about (A-B) times higher than the conventional one. In this case, A.B.C, D is positive.
• the operating temperature range of the amplifier will be 0 to 7_0.
• the basic value of the bypass current A at C and the fluctuation range BCA ⁇ B For this reason, a constant current pulse circuit is used that has a control current range that can completely absorb this fluctuation range B and that can control the current value in voltage. Therefore, the voltage appearing at both ends of the output resistor connected to the output terminal is applied to the constant current bias circuit connected between the first and second middle output terminals via the integration circuit. Then, negative feedback is applied to stabilize the idle current of the power transistor in the output stage.
• the integrating circuit removes, for example, low-frequency components of 20 Hz or more from the signal flowing through the output resistor.
• the use of the constant current circuit, the integrator circuit, and the negative feedback technique in the bias circuit allows the drive stage transistor to be improved.
• the matching of the SEPP output stage with the transistor is a simple current addition and subtraction, and the undriven transistor of the SEPP output stage does not go down to 0FF.
• FIG. 1 is a circuit diagram showing a conventional class AB amplifier
• FIG. 2 is a basic circuit diagram of an amplifier having a constant current bias circuit according to the present invention
• FIG. 3 is a constant current element and a constant current bypass.
• FIG. 4 is a circuit diagram showing an amplifier according to a first embodiment of the present invention
• FIG. 5 is an amplifier according to a second embodiment of the present invention.
• FIG. 6 is a circuit diagram showing a part of an amplifier according to a third embodiment of the present invention
• FIG. 7 is a third embodiment of a constant current bias circuit according to the present invention.
• FIG. 8 is a circuit diagram showing a fourth embodiment of the constant current bias circuit according to the present invention, and FIG.
• FIG. 9 is a circuit diagram showing the prevention of a lash idle current when the power is turned on.
• FIG. 10 is a circuit diagram showing a constant current bias circuit provided with a protection circuit.
• FIG. 10 is a circuit diagram showing a large current type constant current bias circuit. The conventional constant voltage By A vinegar weakened the constant voltage effect
• FIG. 12 is a circuit diagram showing a constant current bias circuit connected in parallel with the circuit. A circuit diagram showing a class AB amplifier connected in parallel.
• FIG. 2 shows a basic circuit of an amplifier according to the present invention.
• components corresponding to the components used in the amplifier of FIG. 2 are denoted by the same reference numerals, and the description of the corresponding parts is omitted.
• the amplifier according to the present invention also uses a constant current bias circuit 40 instead of the constant voltage bias circuit 26, as is apparent from comparison with the conventional amplifier shown in FIG. ing.
• Constant current bus b A scan circuit 4 0 This is For example a first in the junction with the connected de Tray in to ⁇ force end I t - N and Chi catcher down, channel junction type FET 4 1 The source of the FET 4 L and the second intermediate output terminal I 2 are also provided with resistors 42 respectively converted. Also, FET 4 1 of gate is that is connected to ⁇ force end I 2 in the second.
• This constant current bias circuit 40 can be replaced with a constant current diode, for example, or a P-channel FET can be used in a similar circuit configuration. It is clear. _
• Typical current and voltage characteristics of a constant current diode are shown.
• the current rises sharply like a resistor when the drain-source voltage is in the range of 0 to 0.5 V, but when the voltage is about 0.5 V, the current rises to about 8 mA. Rises slowly from here and is almost constant It shows the constant current characteristics of the above.
• the constant current diode has a transition voltage at about 1.5 V, which changes from a resistor to a constant current characteristic. From this third illustration, the characteristics of the constant current bias circuit according to the present invention are different from those of the conventional constant voltage bias circuit shown as an example by a dotted line. It's confidential.
• FIG. 4 shows a circuit diagram of an amplifier having a feedback type constant current bias circuit according to the present invention.
• This amplifier also includes a differential input stage 10, a voltage width stage 20, and an SEPP output stage 30 of a complementary type.
• the differential input stage 10 has two FETs 11 and 1
• FET 1 1 Oyo common source over scan and negative voltages Gen'ichi V c c and resistor i 5 that will be connected between the beauty ⁇ 2, the positive voltage source + V cc or al FET 1
• Resistors 16 and I7 are connected to each of the drains 1 and 12, respectively.
• Negative feedback resistors 18 and 19 that determine the amplification factor of this amplifier are connected to the gate of FET 12 between the ground and the output terminal described later. .
• the voltage amplification stage 20 is connected to the PNP transistor 21 having a base connected to the drain of the FET 11 and to the drain of the FET 12. Between the PNP transistors 22 and 22 with a fixed base and the common emitter of these PNP transistors 21 and 22 and the positive voltage source. It has a resistor 2 _ 3 to be connected and a current mirror circuit 60 connected to a negative voltage source 1 Vcc. This current mirror circuit 60 is a collector current of the P-NP transistor 22. The current of the same pair value as -L0- flows as the collector current of NPN transistor 25. Therefore, the NPN transistor 24 having the base and the collector connected to the collector of the PNP transistor 22 has the same structure as that of the NPN transistor 24.
• This SEPP output stage 30 has a Darlington readout NPN transistor 3I.32, each with a collector read out to a positive voltage ⁇ + Vcc, and a negative
• the voltage supply is connected to a Darlington-connected PNP transistor 33.3 having a collector connected to Vcc, an output terminal 3 ⁇ , and an output terminal 35.
• the first resistor 36 read in contact with the emitter of the transistor 32 and the output terminal 35 are connected directly to the first resistor 36.
• the force end I ⁇ , between the PNP preparative run-g is te 3 3 of base over scan ⁇ force end I 2 second in that is Se', the constant current bus b
• a scan circuit 4 0 Connected to this constant current bias circuit 40, the voltage appearing at one end of the output resistor 36 and the other end of the output resistor 37 is applied via the integrating circuit 50.
• the integrating circuit 50 includes a resistor 51 connected to one end of the output resistor 36 and a capacitor connected between the other end of the resistor 51 and the other end of the output resistor 37.
• the constant current bias circuit 40 is connected to the collector of the PNP transistor 21 and the base connected to the base of the NPN transistor 31.
• N-channel junction type with a lane. Connects the FET 41 and the cascade connection with this FET 41, that is, the emitter read out to the source of FET 1. It has the FNP transistor 43 and the PNP transistor 43. The collector of the PNP transistor 43 The collector of the NPN transistor 25 And connected to the base of the PP transistor 33.
• the transistor 43 is a collector current or a drain current.
• the voltage applied between the gate of the FET 41 and the base of the PNP transistor 43 This gate is adjusted by the If the voltage between them is constant, the collector current, that is, the drain current is almost constant .. Operation of the class AB amplifier including the constant current bias circuit of the present invention will be described.
• the combined current width ratio (collector current novel current) of the NFN transistor 31.32 and the PNP transistor 333, 34 is set to 1, Assuming 0 0 0, the idling of NPN transistors 31, 32 and PNP transistors 33, 34 in the absence of signal Suppose that the collector currents of the PNP transistor N 2 and I 25 are 5 mA each.
• the constant current circuit 40 drives the indicated idling current when the base current of the NPN and PNP small transistors 31 and 34 is 0-0 5 mA. As a result, a positive current of 4.9501 A flows. This current is set at a voltage, for example, 0.1 V, which appears between the first and second lead resistors 36 and 37.
• the FP The collector current of the transistor becomes approximately 4.5 tnA, and therefore, the collector of the NPN transistor 25 of the current mirror circuit 60 -The current drops to approximately 4.5 mA. Therefore, when the base current of the NPN transistor 31 becomes 1.05 mA, the IE current of 1.05 A is taken out from the output terminal 35. I can do it.
• the present invention uses a constant current bias circuit in which the current value is controlled by voltage and eliminates the drawbacks of a bi-boller type transistor used in the SEPP output stage. It is.
• the transistor is a Darlington connection, an inverted Darling connection, and a ⁇ ⁇ ⁇ ⁇ transistor. Also includes transistors.
• the amplifier provided with the constant current bias circuit includes: T / JP87 / 00905 13-As shown in Fig. 5, it can also be applied to MOS type FETs, and it can be applied to bipolar type transistors and N and P channel MOSFETs. 63 and 64 can be mixed and connected, or another amplifying element such as a junction FET or SIT can be used. In this case, elements corresponding to those of the first embodiment of the present invention shown in FIG. 1 are denoted by the same reference numerals.
• the constant current bias circuit 40 is composed of an NPN transistor 44 having a collector connected to the base of the NPN transistor 31.
• a junction-type P-channel FET 45 having a source connected to the emitter of the NPN transistor 44.
• the drain of the P-channel FET 45 is connected to the base of the PNP transistor 33, and the base of the NPN transistor 44 is connected to the 1 is connected to one end of the output resistor 36, and the gate of the P-channel FET 45 is connected to the other end of the second output resistor 37 via the resistor 51.
• a capacitor 52 is connected between the base of the NPN transistor 44 and the gate of the P-channel FET 45.
• the N-channel M0 SFET 63 has a drain connected to the positive voltage source and connected to the emitter of the gate transistor NPN transistor 31. And the source is connected to one end of the first output resistor 36.
• the P-channel MOSFET 64 is connected to the drain power, a negative voltage source, and the gate is connected to the emitter of the PNP transistor 33. And the source is connected to the second output resistor 37.
• the NPN and PNP transistors 31 and 33 have resistors 38 connected between the emitters in order to supply a bias current with good frequency characteristics. It is.
• the integrating circuit 50 includes a second-order or higher-order high-cut filter. May be used.
• the sixth HI shows an amplifier portion provided with a constant current bias circuit according to the third embodiment of the present invention.
• This constant current bias circuit 40 is a junction type N-channel FET 47 and a source read through a resistor 49 to the source of this N-channel FET 47.
• the series-connected output resistors 36 and 37 are connected between the gates of these channel F ⁇ ⁇ . The voltage appearing at both ends is applied.
• This constant current circuit is also used for the -degree compensation of the ⁇ 1 transistor 31 and the ⁇ ⁇ transistor 33. Therefore, as shown in Fig. 6, a part of the bias current is read in parallel with the constant current-element 65 or the constant current read-in F channel F ⁇ ⁇ You may.
• the resistor 67 adjusts the drain current to obtain a predetermined constant current.
• FIG. 7 shows another embodiment of the constant current bias circuit.
• This circuit includes a constant current die Hauts de 7 1 with the connected anode to the relay output terminals I t of the I, which is connected to the constant current die Hauts de 7 1 shade pole of this base and the first An NPN transistor 72 having a collector connected to the middle output terminal IL, an emitter connected to the cathode of the constant current diode 71, and a second P A PNP transistor 73 with a collector read from the output terminal I 2 and a resistor 7 4 with one end read from the emitter of the PN transistor 72 And a PNP transistor having an emitter connected to the other end of the resistor 74 and a collector read to the second intermediate output terminal I2. 7 ⁇ and the anode read on the base of the ⁇ ⁇ ⁇ transistor 5 One ⁇ 5 —
• the constant current bias circuits used in the amplifiers shown in FIGS. 4 to 7 are suitable for a two-stage or three-stage, straight-line connected SEPP output stage.
• the SEPP output stage is the ⁇ stage
• the base of the PNP transistor 31 and the base of the NPN transistor 31 are used. Since the voltage V bb between the PNP transistor 33 is about 0.3 V, for example, the voltage on the emitter side of the driven PNP transistor 33 is set to the base (control terminal). It is preferable to control from the side.
• This constant current bias circuit is an NPN transistor having a collector connected to the positive voltage source + Vcc and an emitter connected to one end of the resistor 36.
• An output terminal 35 connected to the other end of the resistor 31, the other end of the resistor 36, and one end of the resistor 37, and an emitter connected to the other end of the resistor 37.
• It has an NPN transistor 78 connected to the base of the PNP transistor 33 and having an emitter. Therefore, the integrating circuit 50 is connected to the base of the NPN transistor 78 and one end of the resistor 36.
• the resistor 51 and the NPN transistor 78 are connected together.
• a capacitor 52 connected between the base and the emitter.
• Such a feedback-type constant current bias circuit charges a capacitor 52 that forms an integration circuit with a charge. ; ⁇ Output to the g: power transistor's emitter.
• the constant current bias circuit 40 shown in Fig. S is used to set this flush idle current in the power transistor AS0 area. Good.
• the bias current flowing between the FETs 47.48 is 2 ⁇ A
• the FET 47.48 with an absolute value of I dss of about 8 mA or more returns. It is advisable to adjust the resistance 49 to set the bias current to 2 mA.
• the mutual conductance of these FETs 47 and 48 is directly representative and preferably 30 ms or more. In this way, the FETs 47 and 4.8 during operation have a voltage V ss between the sources of about 20 times the voltage V gg between the gates, and a bias current of the bias current. The fluctuation range can be kept low.
• FIG. 9 shows a constant current bias circuit according to the present invention, a constant voltage bias circuit capable of controlling 0 N 0 FF, and a delay circuit for delaying a signal for a predetermined period from power-on.
• the constant-current bias circuit shown in Fig. 6 shows the-part of the amplifier that receives only this signal and has an isolator that turns off the constant-voltage bias circuit. Since it is _ similar to that of, the description is omitted.
• Constant-voltage bus b A scan circuit is Sejju _, to the common Collector power and medium ⁇ force end I 2 that are middle ⁇ force end I this Se' Roh Connected to the NPN transistor 81 with a drain connection with the emitter, the middle output terminal I, and the base of the NFN transistor 81 high resistance 82 that is, that have an NPN preparative run-g is te 8 1 of base and a high resistance 8 3 connected to the relay output terminal I 2.
• the isolator 85 includes, for example, a light emitting diode 86 having an anode and a cathode connected to the output terminal Q of the delay circuit 89 and the ground, respectively, and an NPN transistor 8.
• Photocoupler having a base and a phototransistor 87 having a collector and an emitter read by the emitter. It is.
• the delay circuit 89 includes, for example, a CMOS-type single-stable multivibrator, that is, an MC14528 made by Motorola. It should be noted that, between the PNP door run-g is te 3 3 of the base and Collector power., Have constant current die Wow de 8 8 Ru Oh. A similar circuit is Ru Se' ii to record "1 .
• the goodness of the constant current bias circuit according to the present invention has been pursued to the utmost.
• the present invention relates to an operational amplifier (OP amplifier), for example, a TL-X series made by TI, ⁇ A741 or 45 made by Fairfield. 58, when the constant current bias circuit according to the present invention is connected in parallel with a conventional constant voltage bias circuit, which has a lower capacity and a weaker conventional constant voltage bias circuit.
• the power to use is suitable.
• Such a monolithic integrated circuit is formed by forming active elements such as transistors or resistors on the same P-type substrate, for example.
• an amplifier is formed by arranging the electrode portions with an aluminum vapor deposition wire.
• the temperature coefficients of these elements are more easily correlated with each other than in the case of a hybrid amplifier. Therefore, the bias current that the constant current bias circuit according to the present invention takes and the constant current E bias circuit The ratio can be set higher than that of a hybrid amplifier. Further, this improvement can be easily performed from the conventional monolithic 0P pumping power.
• the area occupied by the conventional constant-voltage bias circuit is divided into 1: 9, and the reduced area of the conventional constant-voltage bias circuit is accommodated in this 1 area.
• a constant current bias circuit in this case, a constant current diode or a FET connected with a constant current may be formed.
• this constant current bias circuit can use the empty area near the bias circuit of the board even if it does not correspond to 0.9 times that of the conventional constant voltage bias circuit. In addition, since two required lines are provided, it is considerably easier to lay out these elements.
• -FIG. 10 shows an embodiment which teaches such an application.
• the bias circuit shown in this figure is a constant current bias circuit and a constant voltage bias circuit type read in parallel.
• This constant current bias circuit is composed of a FET 41 having a drain connected to the middle output terminal I and a gate connected to the middle output terminal I ⁇ 4 1 and a resistor 42 connected to the middle output terminal I 2 .
• the constant voltage Bai ⁇ scan circuit includes a NPN preparative run-Soo data 2 7 with the connected Collector power and medium ⁇ mosquito end 1 2 connected to the E Mi jitter in the middle ⁇ force terminal I , a variable resistor 2 8 connected to a middle ⁇ force end I t and NPN preparative run-g is te 2 7 based in, NPN preparative run-g is te 2 7 base and medium ⁇ force end I 2 And a resistor 29 connected to the resistor.
• the capacitor 90 serves to make the constant voltage bias circuit a constant current.
• the capacitor L 0 is L 00 / i F and the capacitor 90 is an NPN transistor 27. base that is connected middle to the ⁇ force end I 2 and.
• This capacitor 27 is a conventional constant voltage bias circuit. It is provided to make the current constant.
• the operating temperature range of the amplifier is, for example, 0 to 70 ° C in commercial standards.
• the basic value A and the fluctuation range B (A soil) of the bias current flowing between the middle output terminal It and I 2 are calculated or estimated.
• the basic value C and the variation range D (C D) of the passing current of the constant current bias circuit are obtained, and the constant current bias circuit is set so that (C + D) ⁇ A holds.
• the current value of is set.
• the remaining bias current is absorbed by a constant voltage bias circuit whose internal resistance has been increased by about (A1). However, A. ⁇ , C, D are positive.
• the bias current is measured, and the measured current, for example, 99 to 80% is determined.
• the FET 41 and the resistor 42 are selected so as to be supplied to the current bias circuit, and the variable resistor is selected so that the remaining measured current is supplied to the constant voltage bias circuit.
• the values of 28 and 29 are set to 1 (0.99) to 1 (0.8) times the conventional value.
• Fig. 11 shows that the current supplied to the constant current bias circuit was 10 mA or more because the I dss of the FET 41 was usually 10 mA or less. This is the circuit used in the case.
• This circuit, and the PNP door run-g is te 9 1. with a connection has been appraised jitter in the middle ⁇ force end I t, is connected to the PNP door run-g is te 9 1 of the database was de Tray ting FET 4 1 with the connected gate to medium ⁇ force end I 2 and, connected to the middle ⁇ force end I t and PNP preparative run-g is te 9 1 total one scan Resistor 9 2 and PNP transistor 9 1 It has a read point between the collector of the FET 4 I and the source of the FET 4 I, and a resistor 42 read from the middle output terminal 2.
• FIG. 12 shows a class-based amplifier (a pioneer in Japan, sold by N.O.M-4), which is said to provide the best sound quality at present.
• FIG. 1 shows a circuit diagram of a configuration in which a constant current bias circuit is connected in parallel with a conventional bias circuit in parallel to form a class AB amplifier.
• This circuit has four sets of NPN transistors 32 and PNP transistors 34 connected in parallel, and a variable resistor with one end connected to the middle output terminal IL. 6 and a constant voltage element 95 having an anode mounted on the other end of the variable resistor 96.
• This constant-voltage element 95 has a three-valued temperature. It is well-connected by connecting a diode for recovery in series and sealed in a resin container with good conductivity. ⁇ Output terminal
• the amplifier according to the present invention does not generate the 0FF state in the bipolar transistors of the positive power supply side and the negative power supply lavage used in the output stage. Therefore, the dynamic distortion rate of the output signal is reduced.
• the class AB power amplifier using the constant current circuit of the present invention can be used for power NPN transistors and PNP transistors even when connected to an inductive load such as a speaker. The advantage is that it can reproduce very subtle sounds very realistically, even if it is not in the FF state. Therefore, it can be used for general household and commercial audio equipment and PA. In particular, it is suitable for use in operational amplifiers in integrated circuits used in other performance equipment. .

Landscapes

• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Amplifiers (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=17569952

Family Applications (1)

Country Status (5)

Families Citing this family (36)

Citations (3)

Family Cites Families (15)

• 1987
  • 1987-11-21 EP EP87907681A patent/EP0293486B1/en not_active Expired - Lifetime
  • 1987-11-21 WO PCT/JP1987/000905 patent/WO1988004115A1/ja active IP Right Grant
  • 1987-11-21 US US07/243,337 patent/US4933645A/en not_active Expired - Lifetime
  • 1987-11-21 DE DE8787907681T patent/DE3768655D1/de not_active Expired - Lifetime
  • 1987-11-21 JP JP62507106A patent/JPH07101822B1/ja not_active Withdrawn
• 1990
  • 1990-03-21 US US07/496,768 patent/US5049834A/en not_active Expired - Fee Related

Patent Citations (3)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events