US9761681B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US9761681B2
US9761681B2 US15/303,597 US201515303597A US9761681B2 US 9761681 B2 US9761681 B2 US 9761681B2 US 201515303597 A US201515303597 A US 201515303597A US 9761681 B2 US9761681 B2 US 9761681B2
Authority
US
United States
Prior art keywords
trenches
trench
insulation film
gate insulation
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/303,597
Other languages
English (en)
Other versions
US20170069729A1 (en
Inventor
Katsuhiko Nishiwaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Assigned to TOYOTA JIDOSHA KABUSHIKI KAISHA reassignment TOYOTA JIDOSHA KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NISHIWAKI, KATSUHIKO
Publication of US20170069729A1 publication Critical patent/US20170069729A1/en
Application granted granted Critical
Publication of US9761681B2 publication Critical patent/US9761681B2/en
Assigned to DENSO CORPORATION reassignment DENSO CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TOYOTA JIDOSHA KABUSHIKI KAISHA
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 Japanese Patent Application Publication No. 2013-232533 discloses a semiconductor device having a semiconductor substrate, and a plurality of trenches provided in the semiconductor substrate. In the semiconductor device of the Patent Document 1, the trenches are arranged in an offset grid-like pattern.
  • a semiconductor device disclosed herein comprises a first trench provided in a front surface of a semiconductor substrate, and a second trench provided in the front surface, extending in a direction different from a direction of the first trench, and intersecting the first trench in a plan view of the front surface. Further, the semiconductor device comprises a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an intersection of the first trench and the second trench, and a gate electrode provided in the first trench and the second trench, and facing the semiconductor substrate via the gate insulation film.
  • the semiconductor device comprises a first semiconductor region of a first conductive type provided in the semiconductor substrate, exposed on the front surface, being in contact with the gate insulation film in the second trench, and not being in contact with the gate insulation film covering the inner surface of the intersection of the first trench and the second trench.
  • the semiconductor device comprises a second semiconductor region of a second conductive type provided in the semiconductor substrate, and being in contact with the gate insulation film in the second trench on a deeper side than the first semiconductor region.
  • the semiconductor device comprises a third semiconductor region of the first conductive type provided in the semiconductor substrate, being in contact with the gate insulation film in the second trench on a deeper side than the second semiconductor region, and separated from the first semiconductor region by the second semiconductor region.
  • the trench becomes deeper at the intersection where the first trench and the second trench intersect than in other surrounding portions.
  • the first semiconductor region is not in contact with the gate insulation film provided in the intersection, thus an influence by the deep trench at the intersection can be avoided.
  • a threshold voltage of the semiconductor device can be stabilized.
  • FIG. 1 is a plan view of a semiconductor device
  • FIG. 2 is a cross sectional view along II-II in FIG. 1 ;
  • FIG. 3 is a cross sectional view along III-III in FIG. 1 ;
  • FIG. 4 is an enlarged view of a primary portion IV in FIG. 1 ;
  • FIG. 5 is a plan view of a semiconductor device of another embodiment
  • FIG. 6 is an enlarged view of a primary portion of a semiconductor device of yet another embodiment.
  • FIG. 7 is a plan view of a semiconductor device of yet another embodiment.
  • a semiconductor device may comprise a plurality of first trenches and a plurality of second trenches.
  • the plurality of the first trenches and the plurality of the second trenches may be arranged in a grid-like pattern in a plan view of a front surface of a semiconductor substrate.
  • a first semiconductor region may not be in contact with a gate insulation film in the first trenches.
  • Grids formed by the first trenches and the second trenches may be arranged in a staggered pattern in the plan view of the front surface of the semiconductor substrate.
  • a semiconductor device 1 shown in FIGS. 1 to 3 is an IGBT (Insulated Gate Bipolar Transistor).
  • the semiconductor device 1 comprises a semiconductor substrate 10 , electrodes, insulating layers, and the like.
  • the semiconductor substrate 10 is constituted of silicon (Si). In other embodiments, the semiconductor substrate 10 may be constituted of silicon carbide (SiC), gallium nitride (GaN), or the like. As shown in FIG. 2 , the semiconductor substrate 10 comprises emitter regions 24 (corresponding to an example of a first semiconductor region), contact regions 25 , body regions 23 (corresponding to an example of a second semiconductor region), a drift region 22 (corresponding to an example of a third semiconductor region), and a collector region 21 provided therein.
  • the semiconductor substrate 10 comprises, in this order from its rear surface side, the p-type collector region 21 , the n-type drift region 22 provided on the collector region 21 , the p-type body regions 23 provided on the drift region 22 , the n-type emitter regions 24 provided on the body regions 23 , and the p-type contact regions 25 provided on the body regions 23 .
  • the collector region 21 is exposed on a rear surface of the semiconductor substrate 10 .
  • the collector region 21 is separated from the body regions 23 by the drift region 22 .
  • the drift region 22 is separated from the emitter regions 24 by the body regions 23 .
  • the emitter regions 24 are exposed on a front surface of the semiconductor substrate 10 .
  • the contact regions 25 are exposed on the front surface of the semiconductor substrate 10 .
  • a p-type impurity concentration of the contact regions 25 is higher than a p-type impurity concentration of the body regions 23 .
  • the n-type corresponds to an example of a first conductive type
  • the p-type corresponds to an example of a second conductive type.
  • a front surface electrode 70 is provided on the front surface of the semiconductor substrate 10 .
  • the front surface electrode 70 is connected to the emitter regions 24 and the contact regions 25 .
  • a rear surface electrode 72 is provided on the rear surface of the semiconductor substrate 10 .
  • the rear surface electrode 72 is connected to the collector region 21 .
  • the front surface of the semiconductor substrate 10 is provided with a plurality of trenches 61 (that is, a plurality of first trenches 611 and a plurality of second trenches 612 ).
  • the first trenches 611 extend along an x direction (a first direction).
  • the plurality of the first trenches 611 is provided aligning along a y direction with intervals between each other.
  • the y direction is a direction different from the x direction, and more specifically, the y direction is a direction orthogonally intersecting with the x direction.
  • the plurality of the first trenches 611 extends parallel to each other.
  • the second trenches 612 extend along the y direction (a second direction).
  • the plurality of the second trenches 612 is provided aligning along the x direction with intervals between each other.
  • the plurality of the second trenches 612 extends parallel to each other.
  • the second trenches 612 that are adjacent in the y direction are offset from each other in the x direction.
  • Each second trench 612 is provided between two first trenches 611 .
  • Each of the second trenches 612 intersects with the first trenches 611 at its both ends (at intersections 30 in FIG. 1 ).
  • the trenches 61 extend in three directions from each intersection 30 .
  • the front surface of the semiconductor substrate 10 is partitioned into a grid-like pattern by the first trenches 611 and the second trenches 612 .
  • Grids formed by the first trenches 611 and the second trenches 612 are arranged so as to be in a staggered pattern.
  • regions partitioned in the grid-like pattern will be termed element regions 20 .
  • the emitter regions 24 are provided in respective element regions 20 .
  • the emitter regions 24 are adjacent to corresponding second trenches 612 .
  • the emitter regions 24 are provided along the corresponding second trenches 612 .
  • the emitter regions 24 extend in the y direction (the second direction).
  • the emitter regions 24 are provided on both sides of each second trench 612 in the x direction.
  • the emitter regions 24 on both sides of each second trench 612 are provided symmetrically with the second trench 612 between those emitter regions 24 .
  • the emitter regions 24 are not adjacent to the first trenches 611 . Further, the emitter regions 24 are not adjacent to the intersections 30 .
  • the emitter regions 24 are arranged so as to be separated from the first trenches 611 as well as from the intersections 30 .
  • the contact regions 25 are arranged so as to be in contact with corresponding first trenches 611 , second trenches 612 , and intersections 30 . That is, each contact region 25 is arranged between corresponding emitter regions 24 and first trenches 611 .
  • the trenches 61 extend from the front surface of the semiconductor substrate 10 in a z direction (a depth direction).
  • the first trenches 611 penetrate the emitter regions 24 and the body regions 23 , and reach the drift region 22 .
  • the second trenches 612 penetrate the contact regions 25 and the body regions 23 , and reach the drift region 22 .
  • a depth of the trenches 61 is made deeper compared to outside of the intersections 30 .
  • a gate insulation film 62 is provided on inner surfaces of the trenches 61 .
  • the gate insulation film 62 covers an entirety of the inner surfaces of the trenches 61 .
  • a gate electrode 63 is provided inside the respective trenches 61 (an inner side of the gate insulation film 62 ).
  • the gate electrode 63 is arranged inside the first trenches 611 as well as inside the second trenches 612 .
  • the gate electrode 63 opposes the semiconductor substrate 10 via the gate insulation film 62 .
  • the gate electrode 63 is insulated from the front surface electrode 70 by an interlayer insulation film 74 . Further, as shown in FIG. 4 , the gate insulation film 62 covers the inner surfaces of the first and second trenches 611 , 612 as well as the inner surfaces of the intersections 30 of the first and second trenches 611 , 612 .
  • an inner surface 301 of each intersection 30 corresponds to an inner surface of a portion (corner) where ends of the first trenches 611 and an end of the corresponding second trench 612 make contact. Further, the inner surface 301 of each intersection 30 corresponds to inner surfaces of portions of the first trenches 611 that oppose the second trench 612 extending towards the first trenches 611 . This inner surface 301 faces the corresponding intersection 30 .
  • the contact regions 25 , the emitter regions 24 , the body regions 23 , and the drift region 22 are in contact with the gate insulation film 62 .
  • the emitter regions 24 are in contact with the gate insulation film 62 in a vicinity of the front surface of the semiconductor substrate 10 .
  • the contact regions 25 are in contact with the gate insulation film 62 in the vicinity of the front surface of the semiconductor substrate 10 .
  • the contact regions 25 are in contact with the gate insulation film 62 in the corresponding first trenches 611 , the corresponding second trenches 612 , and the corresponding intersections 30 .
  • the emitter regions 24 are in contact with the gate insulation film 62 inside the corresponding second trenches 612 .
  • the emitter regions 24 are not in contact with the gate insulation film 62 in the first trenches 611 and the intersections 30 .
  • the body regions 23 are in contact below the emitter regions 24 with the gate insulation film 62 on a deeper side than the emitter regions 24 .
  • the body regions 23 are in contact below the contact regions 25 with the gate insulation film 62 on the deeper side than the contact regions 25 .
  • the drift region 22 is in contact below the body regions 23 with the gate insulation film 62 on a deeper side than the body regions 23 .
  • the semiconductor device 1 comprising the aforementioned configuration, when the gate electrode 63 in the trenches 61 is brought to an ON potential (a potential equal to or greater than a threshold), channels are formed along the depth. direction of the trenches 61 in the body regions 23 in a vicinity of the gate insulation film 62 . Further, when a voltage is applied between the front surface electrode 70 and the rear surface electrode 72 , electrons flow from an emitter region 24 side to the collector region 21 through the channels and the drift region 22 . Further, holes flow from the collector region 21 to the contact regions 25 through the drift region 22 and the body regions 23 . Accordingly, a current flows from the collector region 21 to the emitter regions 24 . That is, the IGBT turns on.
  • an ON potential a potential equal to or greater than a threshold
  • the trenches 61 are deeper in the intersections 30 than in other surrounding portions.
  • the threshold that is, the gate potential required to form the channels
  • the threshold may vary between positions where the trenches 61 are deep (that is, in the vicinities of the intersections 30 ) and positions where the trenches 61 are shallow (that is, positions away from the intersections 30 ), resulting in threshold variations among IGBTs being large.
  • the aforementioned semiconductor device 1 arranges the emitter regions 24 so as not to be adjacent to the gate insulation film 62 provided in the intersections 30 . Due to this, in the semiconductor device 1 , areas below the emitter regions 24 become the main passages of the electrons, and not so much electrons flow in the vicinities of the intersections 30 . Due to this, an influence of the deep trenches 61 in the intersections 30 can be avoided. As a result, the threshold variations among the semiconductor devices 1 can be suppressed, and the threshold can be stabilized. Further, switching performance can be stabilized.
  • the vicinities of the intersections 30 are used as the main passages of the electron flow, the electron flow tends to concentrate in the vicinities of the intersections 30 .
  • the concentration of the current in the vicinities of the intersections 30 can be suppressed due to the emitter regions 24 not being adjacent to the intersections 30 .
  • the current flows uniformly since the emitter regions 24 are arranged symmetrically with the corresponding second trench 612 therebetween. Due to this, a local heat generation at the intersections 30 can be suppressed.
  • the contact regions 25 can be secured at portions where the emitter regions 24 are separated from the intersections 30 . Due to this, regions where the holes are to flow can be ensured, and fast speed switching is enabled.
  • the plurality of the first trenches 611 and the plurality of the second trenches 612 are provided so that the plurality of the grids (element regions 20 ) is arranged in the staggered pattern.
  • a variation may occur among depths of the first trenches 611 and the second trenches 612 .
  • the thresholds may vary among the electron passages along the first trenches 611 and the electron passages along the second trenches 612 , depending on a difference in the depths between the first trenches 611 and the second trenches 612 .
  • the emitter regions 24 are not in contact with the gate insulation film 62 inside the first trenches 611 . Due to this, an influence from the difference in the depths between the first trenches 611 and the second trenches 612 can be avoided, and the threshold voltage can be stabilized.
  • the plurality of the second trenches 612 is arranged in the staggered pattern, however, no limitation is made hereto.
  • the plurality of the second trenches 612 may be provided so as to be aligned with each other along the y direction (the second direction).
  • the plurality of the second trenches 612 are aligned in straight lines.
  • the trenches 61 are extend in four directions from each intersection 30 .
  • the emitter regions 24 are adjacent to their corresponding second trenches 612 but are not adjacent to the first trenches 611 , however, no limitation is made hereto.
  • the emitter regions 24 may be adjacent to each of the corresponding first and second trenches 611 , 612 .
  • the emitter regions 24 adjacent to the first trenches 611 are provided so as to be separated from the second trenches 612 .
  • the emitter regions 24 adjacent to the second trenches 612 are provided so as to be separated from the first trenches 611 .
  • the emitter regions 24 are provided symmetrically with the corresponding second trench 612 therebetween, however, no limitation is made hereto, and the emitter regions 24 may be provided asymmetrically.
  • the emitter region 24 is provided on one side of each second trench 612 in the x direction, and no emitter region 24 is provided on another side thereof. According to this configuration, portions where the current flows can be scattered, and current concentration can be suppressed.
  • the plurality of the trenches 61 is arranged in the grid-like pattern, however, no limitation is made hereto.
  • the plurality of the trenches 61 may be arranged in a polygonal pattern.
  • the plurality of the trenches 61 is arranged in a hexagonal pattern.
  • the plurality of the trenches 61 is arranged in a honeycomb pattern.
  • the intersections 30 are provided at portions where the trenches 61 arranged in the hexagonal pattern intersect.
  • the IGBT is provided in the semiconductor substrate 10 , however, a MOSFET may be provided instead of the IGBT.
  • a MOSFET may be provided instead of the IGBT.
  • a structure in which an n-type high concentration region is provided instead of the collector region 21 , and the high concentration region is electrically connected to the rear surface electrode 72 may be employed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Electrodes Of Semiconductors (AREA)
US15/303,597 2014-05-26 2015-03-27 Semiconductor device Active US9761681B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014107824A JP6256192B2 (ja) 2014-05-26 2014-05-26 半導体装置
JP2014-107824 2014-05-26
PCT/JP2015/059721 WO2015182233A1 (ja) 2014-05-26 2015-03-27 半導体装置

Publications (2)

Publication Number Publication Date
US20170069729A1 US20170069729A1 (en) 2017-03-09
US9761681B2 true US9761681B2 (en) 2017-09-12

Family

ID=54698575

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/303,597 Active US9761681B2 (en) 2014-05-26 2015-03-27 Semiconductor device

Country Status (5)

Country Link
US (1) US9761681B2 (ja)
JP (1) JP6256192B2 (ja)
CN (1) CN106463542B (ja)
DE (1) DE112015002496B4 (ja)
WO (1) WO2015182233A1 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6304221B2 (ja) * 2015-12-08 2018-04-04 トヨタ自動車株式会社 Ｉｇｂｔ
WO2017099096A1 (ja) * 2015-12-11 2017-06-15 富士電機株式会社 半導体装置
JP6588363B2 (ja) 2016-03-09 2019-10-09 トヨタ自動車株式会社 スイッチング素子
JP6299789B2 (ja) 2016-03-09 2018-03-28 トヨタ自動車株式会社 スイッチング素子
JP6958093B2 (ja) * 2017-08-09 2021-11-02 富士電機株式会社 半導体装置
US10998403B2 (en) * 2019-03-04 2021-05-04 Infineon Technologies Americas Corp. Device with increased forward biased safe operating area (FBSOA) through using source segments having different threshold voltages
CN112992682A (zh) * 2019-12-13 2021-06-18 华润微电子（重庆）有限公司 沟槽型场效应晶体管结构及其制备方法
JP7439746B2 (ja) * 2020-12-23 2024-02-28 株式会社デンソー 炭化珪素半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005109521A1 (ja) 2004-05-12 2005-11-17 Kabushiki Kaisha Toyota Chuo Kenkyusho 半導体装置
JP2012190938A (ja) 2011-03-09 2012-10-04 Toyota Motor Corp Ｉｇｂｔ
JP2013149836A (ja) 2012-01-20 2013-08-01 Toyota Motor Corp 半導体装置とその製造方法
JP2013232533A (ja) 2012-04-27 2013-11-14 Rohm Co Ltd 半導体装置および半導体装置の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005109521A1 (ja) 2004-05-12 2005-11-17 Kabushiki Kaisha Toyota Chuo Kenkyusho 半導体装置
US20080012040A1 (en) 2004-05-12 2008-01-17 Kabushiki Kaisha Toyota Chuo Kenkyusho Semiconductor Devices
JP2012190938A (ja) 2011-03-09 2012-10-04 Toyota Motor Corp Ｉｇｂｔ
US20140054645A1 (en) * 2011-03-09 2014-02-27 Toyota Jidosha Kabushiki Kaisha Insulated-gate bipolar transistor
JP2013149836A (ja) 2012-01-20 2013-08-01 Toyota Motor Corp 半導体装置とその製造方法
JP2013232533A (ja) 2012-04-27 2013-11-14 Rohm Co Ltd 半導体装置および半導体装置の製造方法
US20150295079A1 (en) 2012-04-27 2015-10-15 Rohm Co., Ltd. Semiconductor device and semiconductor device manufacturing method

Also Published As

Publication number Publication date
JP2015225872A (ja) 2015-12-14
US20170069729A1 (en) 2017-03-09
DE112015002496B4 (de) 2018-08-16
DE112015002496T5 (de) 2017-03-02
WO2015182233A1 (ja) 2015-12-03
CN106463542B (zh) 2020-01-10
JP6256192B2 (ja) 2018-01-10
CN106463542A (zh) 2017-02-22

Similar Documents

Publication Publication Date Title
US9761681B2 (en) Semiconductor device
US10818782B2 (en) Insulated-gate bipolar transistor (IGBT) including a branched gate trench
JP6197773B2 (ja) 半導体装置
TWI575737B (zh) 半導體裝置
WO2017141998A1 (ja) 半導体装置
US9142627B2 (en) Semiconductor device
TW201611275A (zh) 半導體裝置
JP2014060362A (ja) 半導体装置
JP6563639B2 (ja) 半導体装置及び半導体装置の製造方法
US9318590B2 (en) IGBT using trench gate electrode
JP5867484B2 (ja) 半導体装置の製造方法
JPWO2019116696A1 (ja) 半導体装置
US20110284923A1 (en) Semiconductor device and manufacturing method of the same
JP5971218B2 (ja) 半導体装置
JP2013161918A (ja) 半導体装置
JP7052315B2 (ja) 半導体装置
JP2016096307A (ja) 半導体装置
US20170053991A1 (en) Semiconductor device
KR102030465B1 (ko) 레터럴 타입의 전력 반도체 소자
JP2008198652A (ja) 半導体装置
JP2015188104A (ja) トレンチゲート型電力半導体素子
JP5774744B2 (ja) 半導体装置
WO2024095578A1 (ja) 半導体装置とその製造方法
JP6708530B2 (ja) 炭化珪素半導体装置
JP2008251710A (ja) 半導体装置とその製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: TOYOTA JIDOSHA KABUSHIKI KAISHA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NISHIWAKI, KATSUHIKO;REEL/FRAME:039999/0184

Effective date: 20160921

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: DENSO CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TOYOTA JIDOSHA KABUSHIKI KAISHA;REEL/FRAME:052285/0419

Effective date: 20191224

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4