US7379333B2 - Page-buffer and non-volatile semiconductor memory including page buffer - Google Patents

Page-buffer and non-volatile semiconductor memory including page buffer Download PDF

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US7379333B2
US7379333B2 US11/228,189 US22818905A US7379333B2 US 7379333 B2 US7379333 B2 US 7379333B2 US 22818905 A US22818905 A US 22818905A US 7379333 B2 US7379333 B2 US 7379333B2
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latch
memory device
line
data
internal data
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US20060120172A1 (en
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Sung-Soo Lee
Young-Ho Lim
Hyun-Chul Cho
Dong-Hyuk Chae
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Samsung Electronics Co Ltd
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Priority to US12/752,213 priority patent/US8174888B2/en
Priority to US13/465,246 priority patent/US8493785B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

Definitions

  • the present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to page buffer circuits and other circuits utilized in non-volatile semiconductor memory devices.
  • Flash memories such as NAND-type flash memories, are capable of storing large amounts of data in a relatively small area.
  • FIG. 1A illustrates a typical configuration in which a flash memory cell transistor is connected to word and bit lines of a memory device
  • FIG. 1B shows the circuit symbol of a flash memory cell transistor
  • FIG. 1C shows the threshold voltage characteristics of a flash memory cell transistor.
  • a flash memory cell transistor includes a source region 4 and a drain region 5 located at the surface of a substrate 3 .
  • the substrate is P-type
  • the source and drain regions 4 and 5 are N + -type.
  • a gate structure is aligned over a channel region defined between the source and drain regions 4 and 5 .
  • the gate structure includes a floating gate 1 and a control gate 2 .
  • a tunneling dielectric layer is interposed between the floating gate 1 and surface of the substrate Psub, and another thin oxide layer (or control dielectric) is interposed between the floating gate 1 and the control gate 2 .
  • the drain voltage Vd is supplied from a bit line BL
  • the control gate voltage Vcg is supplied from a word line WL
  • the source voltage Vs is connected to a reference potential such as ground.
  • the threshold voltage of the flash memory cell transistor defines its stored logic value. That is, when the flash memory cell transistor is in its initial state (also called an “erased” state), the threshold voltage Vth is relatively low as shown in FIG. 1C . In this state, the cell transistor is designated to have a logic value “1”, which generally corresponds to the ON state of a conventional transistor device. On the other hand, when the cell transistor is in its “programmed” state (PGM), the threshold voltage Vth is relatively high. This high threshold state is designated to have a logic value “0”, which generally corresponds to the OFF state of a conventional transistor device.
  • FN tunneling In order to change (program) the cell transistor from its initial state to its programmed state, a process known as Fowler-Nordheim (FN) tunneling is utilized. Briefly, a relatively large positive potential difference is created between the control gate 2 and the substrate Psub, and excited electrons within the channel on the surface of the substrate Psub are caused to be pushed through and trapped in the floating gate 1 . These negatively charged electrons act as a barrier between the control gate 2 and the channel on the substrate Psub, thus increasing the threshold voltage of the cell transistor as represented in FIG. 1C .
  • FN Fowler-Nordheim
  • the cell transistor can be brought back to its initial state by forming a large negative potential difference between the control gate 2 and the substrate Psub, whereby resultant FN tunneling draws the trapped electrons back across the thin oxide layer between the floating gate 1 and substrate Psub, thus removing the electron barrier and decreasing the threshold voltage Vth.
  • the ON and OFF threshold voltages Vth of the large numbers of flash cell transistors found in flash memory devices generally exhibit bell curve distributions.
  • the threshold voltages Vth of the erased cell transistors (having logic value “1”) may be distributed between ⁇ 3v and ⁇ 1v
  • the threshold voltages Vth of the programmed cell transistors (having logic value “0”) may be distributed between +1v and +3v.
  • NAND flash memories are characterized by serially connected “strings” 6 of flash memory cell transistors, where multiple parallel strings 6 constitute a memory block 7 of the flash memory.
  • each string 6 is comprised of a plurality of flash memory cell transistors connected in series along a bit line B/L in the memory block 7 .
  • Word lines W/L are connected to the control gates of each respective row of cell transistors in the memory block 7 .
  • a flash memory device may contain 16 or 32 cell transistors in each string 6 , and 4224 strings (B/L 0 . . . B/L 4223 ) in each memory block 7 .
  • each string 6 At opposite ends of each string 6 are string select transistors having control gates which receive a string select signals SSL and a ground select signal GSL. Generally, the select signals SSL and GSL are utilized in reading and programming of the cell transistors. Further, at the end of each string is a common source line CSL which sets a source line voltage of the cell transistor strings 6 of each memory block 7 .
  • the table of FIG. 3B generally shows the various voltage conditions of the signals illustrated in FIG. 3A for each of erase, program and read operations.
  • “Sel. W/L” denotes the selected word line for which the program or read operation is to be executed
  • “Unsel.W/L” denotes the remaining word lines of the memory block.
  • “Sel. W/L” denotes the word lines of the selected memory block for which the erase operation is to be executed
  • “Unsel. W/L denotes the word lines of the remaining memory blocks in the memory cell array.
  • string select signal SSL is set to VDD
  • ground select signal GSL is set to 0v
  • the common source line CSL voltage is set to between VSS and VDD (e.g., 1.5v)
  • the bulk voltage is set to 0v.
  • programming occurs one word line at a time, and accordingly, one word line is selected per memory block for each programming operation.
  • the selected word line W/L receives a programming voltage Vpgm
  • the remaining unselected word lines W/L receive a voltage Vpass, where Vpgm is greater than Vpass.
  • Vpgm is of a sufficiently high voltage (e.g., 18v) that FN tunneling results when the bit line B/L voltage of any cell transistor of the selected word line is 0v.
  • the program voltage Vpgm creates a voltage difference (e.g., 18v) which is sufficient to initiate FN tunneling, thus placing the cell transistor in a programmed state.
  • the bit line B/L voltage of any cell transistor is VDD
  • FN tunneling is inhibited as a result of insufficient voltage difference (e.g., 10v).
  • the cell is said to be “program inhibited”.
  • the pass voltage Vpass is sufficiently high to place the non-selected cell transistors in a conductive state, but not so high as to cause FN tunneling.
  • string select signal SSL is set to Vread
  • ground select signal GSL is set to Vread
  • the common source line CSL voltage is set to 0v
  • the bulk voltage is set to 0v.
  • the read operation typically occurs one word line at a time, and accordingly, one word line is selected per memory block for each read operation.
  • the selected word line W/L is set to 0v, while the remaining unselected word lines W/L receive a read voltage Vread.
  • Vread is 4.5v, which exceeds the threshold voltage distributions of the “1” and “0” cell transistors. Therefore, the cell transistors coupled to the non-selected word lines become conductive.
  • the 0v voltage applied to the selected word line falls between the threshold voltage distributions of the “1” and “0” cell transistors.
  • the “1” cell transistors connected to the selected word line become conductive, whereas the remaining cell transistors of the selected word line are nonconductive.
  • the result is a voltage difference among the bit lines B/L of the memory block.
  • a bit line B/L voltage of about 1.2v is read as having a “0” state cell transistor at the selected word line, and a bit line voltage of less than 0.8v is read as having a “1” state cell transistor at the selected word line.
  • the bit lines B/L, string select signal SSL, ground select signal GSL, common source line CSL, and the word lines of the unselected memory blocks are all set to a floating state.
  • the selected word line voltage is set to 0v
  • the bulk voltage is set to Verase (e.g., 19-21v).
  • Verase e.g. 19-21v
  • a negative voltage difference is formed between the control gate and the bulk, resulting in FN tunneling across the gate oxide between the floating gate and the substrate.
  • the threshold voltage distribution is reduced from the programmed “0” state to the erased “1” state. Note that all the cell transistors of the selected memory block are in the erased “1” state after the erase operation.
  • bit lines BL ⁇ k: 0 > are divided into even and odd bit lines BL_E ⁇ k: 0 > and BL_O ⁇ k: 0 >.
  • the cell transistors of each word line constitute pages of the memory block, and in the example of FIG. 7 , each word line is connected to an odd page and an even page of the memory block.
  • the page buffers PB ⁇ k: 0 > contained in a page buffer block are utilized to transmit read data from, and program data to, the flash memory block.
  • one page buffer PB is provided for each pair of odd and even bit lines.
  • FIG. 8 is a block diagram illustrating core elements of one example of a NAND-type flash memory, in which a so-called “Y-gating” technique is utilized to access bit lines of the memory.
  • a plurality of page buffer blocks PBB ⁇ 31 : 0 > are connected via bit lines BL ⁇ 255 : 0 > to a memory cell array MCARR.
  • Each page buffer block PBB interfaces with eight bit lines BL.
  • each bit line BL is actually constituted by a pair of odd and even bit lines as discussed previously in connection with FIG. 7 .
  • a plurality of page buffer decoders PBDE ⁇ 31 : 0 > are operatively coupled to the respective page buffer blocks PBB ⁇ 31 : 0 >, y address lines Ya ⁇ 7 : 0 >, y address lines Yb ⁇ 31 : 0 >, and a global data bus GDB.
  • the y address lines Ya ⁇ 7 : 0 > are commonly applied to all of the page buffer decoders PBDE ⁇ 31 : 0 >, whereas individual ones of the y address lines Yb ⁇ 31 : 0 > are applied to the respective page buffer decoders PBDE ⁇ 31 : 0 >.
  • page buffer decoder PBDE 0 receives y addresses Ya ⁇ 7 : 0 > and Yb 0
  • page buffer decoder PBDE 1 receives y addresses Ya ⁇ 7 : 0 > and Yb 1 , and so on.
  • Internal data lines IDB ⁇ 255 : 0 > are coupled between the page buffer blocks PBB ⁇ 31 : 0 > and page buffer decoders PBDE ⁇ 31 : 0 >.
  • eight internal data lines IDB are provided between each corresponding pair of page buffer block PBB and page buffer decoder PBDE.
  • page buffer blocks PBB ⁇ 31 : 0 > are also applied to the page buffer blocks PBB ⁇ 31 : 0 >, the functions of which are described below in connection with FIG. 9 .
  • FIG. 9 is a schematic circuit diagram for explaining the page buffers PB and the page buffer decoders PBDE illustrated in FIG. 8 .
  • FIG. 9 illustrates the page buffers PB ⁇ 7 : 0 > in a side-by-side arrangement (i.e., juxtaposed in the word line direction). In reality, however, the page buffers are stacked one over the other (i.e., juxtaposed in the bit line direction).
  • the page buffer decoder PBDE 0 of FIG. 9 includes a first transistor connected between the global data bus GDB and a common internal data line IDBC, and a plurality of second transistors connected between the common internal data line and respective internal lines IDB ⁇ 7 : 0 > of the page buffers PB ⁇ 7 : 0 >.
  • the gate of the first transistor receives the y address signal Yb 0
  • the respective gates of the second transistors receive the y address signals Ya ⁇ 7 : 0 >.
  • the y address Yb ⁇ 31 : 0 > is used to selected any one of the page buffer blocks PBB ⁇ 31 : 0 >, and the y address Ya ⁇ 7 : 0 > is used to select a bit line BL within the selected page buffer block PBB.
  • the page buffer PB 0 includes a latch circuit having a latch node CMNLA and an inverted latch node CMNLAn.
  • First and second transistors of the page buffer PB 0 are respectively controlled by the data input selection signals DI and nDI, and these transistors are connected between internal data line IDB 0 and the inverted latch node CMNLAn and latch node CMNLA, respectively.
  • Another transistor is controlled by a page buffer select signal PBSLT, and is connected between the latch node CMNLA and a sense node NSEN 0 .
  • the sense node NSEN 0 which is connected to a memory cell string of the memory cell array, is selectively connected to voltage VDD by operation of another transistor which is controlled by a load control signal PLOAD.
  • the latch circuit of the page buffer PB 0 stores a logic value as dictated by the data input selection signals DI and nDI and the voltage of the internal data line IDB, and this logic value (i.e., the voltage appearing on latch node CMNLA) is then transferred to the bit line of the memory cell string for programming.
  • this logic value i.e., the voltage appearing on latch node CMNLA
  • the sensed voltage appearing on the sense node NSEN 0 is temporarily stored in the latch circuit, and then transferred to the global data bus GDB via the internal data line IDB.
  • the internal data line IDB functions as a shared input and output line.
  • Parasitic capacitive coupling between internal data lines can result as illustrated in FIG. 10 .
  • the page buffers ⁇ 7 : 0 > of each page buffer block PBB are juxtaposed (stacked) in the bit line direction, i.e., between the page buffer decoder PBDE and the memory cell array MCARR.
  • a sense node blocking signal SOBLK which are controlled by a sense node blocking signal SOBLK so as to selectively couple the sense nodes SON ⁇ 7 : 0 > to the bit lines BL ⁇ 7 : 0 >, respectively.
  • the internal data lines IDB of the respective page buffers PB all extend in parallel to each other within the page buffer block PBB. As the layout area of the page buffers PB is reduced, the pitch P between adjacent internal data lines IDB becomes smaller, and accordingly, capacitive coupling increases between adjacent internal data lines IDB. The resultant coupling noise between adjacent internal data lines IDB can cause signal distortion and data errors.
  • the large parasitic capacitance of the internal data lines IDB can also create a charge sharing condition with the low capacitive latch node of the latch circuit of each page buffer PB. In some cases, this can result in the data being flipped. Further, the heavy output load of the internal data lines IDB makes it necessary to increase the output drive capability of the page buffers, which can be problematic when space and power resources are limited.
  • the bus region of the illustrated example includes 40 y address lines. This relatively large number of lines must be attended by a large layout area for the bus region of the device, thus occupying scarce space resources.
  • a non-volatile memory device which is operable in a programming mode and a read mode.
  • the memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines.
  • the memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line.
  • the page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal data output line according to the logic voltage of the latch node.
  • a non-volatile memory device which includes a memory cell array which includes a plurality of non-volatile memory cells, a page buffer which includes a latch circuit for temporarily storing data read from and programmed into the non-volatile memory cells of the memory cell array, an internal data output line which outputs data read from the memory cell array and temporarily stored in the page buffer, a latch input path which is separate from the internal data output line and which sets the latch circuit when data is to be programmed into the non-volatile memory cells of the memory cell array and when data is read from the non-volatile memory cells of the memory cell array.
  • a non-volatile memory device which includes a memory cell array which includes a plurality of non-volatile memory cells, an input data bus which inputs data to be programmed into the non-volatile memory cells of the memory cell array, an output data bus which is separate from the input data bus and which outputs data read from the non-volatile memory cells of the memory cell array, a latch circuit for temporarily storing data read from and programmed into the non-volatile memory cells of the memory cell array, an internal data output line connected to the output data bus, a latch input path connected to the input data bus which sets the latch circuit when data is to be programmed into the non-volatile memory cells of the memory cell array, and an output drive circuit which transfers read data temporarily stored in the latch circuit to the internal data output line.
  • a non-volatile memory device which includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines.
  • the memory device further includes an internal data output line and a plurality of page buffers connected to the memory cell array and the internal data output line.
  • the page buffer are arranged one after the other to define a corresponding plurality of juxtaposed page buffer regions, where each of the page buffers includes a latch circuit which temporarily stores data read from the memory cell array, and an address gate connected between the latch circuit and the internal data output line.
  • the address gate is responsive to an address signal to selectively output the data from the latch circuit of each page buffer to the internal data output line.
  • a non-volatile memory device which includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines, where the plurality of bit lines extend lengthwise in a first direction.
  • the memory device further includes a shared internal data output line which outputs data read from the memory cell array, a plurality of internal data input lines, and a plurality of page buffers which are each operatively connected between the memory cell array, the shared internal data output line, and the plurality of internal data input lines.
  • a non-volatile memory device which includes a memory cell array which includes a plurality of non-volatile memory cells, and a page buffer which includes a local data input line and a latch circuit.
  • the latch circuit is responsive to the local data input line to temporarily store data read from and programmed into the non-volatile memory cells of the memory cell array.
  • the memory device further includes a global data input line which supplies external input signals, where the external input signals include programming signals to program the memory cell array and control signals to read the memory cell array, and a gate circuit which selectively outputs the external input signals to the local data input line according to an address signal supplied to the gate circuit.
  • a nonvolatile memory device which includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines.
  • the memory device further includes an internal data output line which outputs data read from the memory cell array, a plurality of page buffers which are operatively connected between the memory cell array and the internal data output line, and a plurality of address lines operatively connected to at least one gate circuit of the plurality of page buffers.
  • a page buffer for a non-volatile memory device includes a latch circuit including a latch node, an internal data input line which controls a voltage of the latch node, an internal data output line which is electrically isolated from the latch node, and an output drive circuit which controls a voltage of the internal output data line according to the voltage of the latch node.
  • a nonvolatile semiconductor memory device which includes a memory cell array having a plurality of electrically programmable and erasable memory cells, a plurality of word lines, and a plurality of bit lines.
  • the memory device further includes at least one page buffer block including a plurality of page buffers and an internal data output line.
  • the page buffers are respectively connected to the bit lines and each is enabled in response to at least one of a plurality of buffer selection addresses.
  • the page buffers each store data corresponding to data on a bit line thereof on a latch node thereof.
  • the internal data output line is shared between the plurality of page buffers and is driven by data on a latch node of an enabled page buffer.
  • the internal data output line is electrically isolated from latch nodes of the page buffers.
  • FIGS. 1A through 1C are a schematic diagram of a flash memory cell, a circuit symbol of a flash memory cell, and a threshold voltage characteristic diagram of a flash memory cell, respectively;
  • FIG. 2 illustrates threshold voltage distributions of flash memory cells
  • FIGS. 3A and 3B are a schematic diagram of NAND-flash memory cell block, and a table showing erase, program and read voltages of a NAND-flash memory cell block, respectively;
  • FIG. 4 is a diagram for explaining the programming of the NAND-flash memory cell block shown in FIG. 3A ;
  • FIG. 5 is a diagram for explaining the reading of the NAND-flash memory cell block shown in FIG. 3A ;
  • FIG. 6 is a diagram for explaining the erasing of the NAND-flash memory cell block shown in FIG. 3A .
  • FIG. 7 is a schematic diagram of a memory block and a page buffer block
  • FIG. 8 is a schematic diagram of a conventional nonvolatile memory device
  • FIG. 9 is a schematic diagram of a page buffer and a page buffer decoder contained in the nonvolatile memory device of FIG. 8 ;
  • FIG. 10 is diagram illustrating the layout of page buffers within the page buffer block contained in the nonvolatile memory device of FIG. 8 ;
  • FIG. 11 is a block diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of an example of a memory array contained in the nonvolatile memory of FIG. 11 ;
  • FIG. 13 is a diagram of an example of a page buffer block contained in the nonvolatile memory of FIG. 11 ;
  • FIG. 14 is a schematic diagram of an example of a page buffer contained in the page buffer block of FIG. 13 ;
  • FIG. 15 is a schematic diagram of an example of a page buffer decoder contained in the nonvolatile memory of FIG. 11 ;
  • FIGS. 16A and 16B are flow charts for describing a read mode of a nonvolatile memory according to an embodiment of the present invention.
  • FIG. 17 is a timing diagram for describing a read mode of a nonvolatile memory according to an embodiment of the present invention.
  • FIG. 18 is a flow chart for describing a programming mode of a nonvolatile memory according to an embodiment of the present invention.
  • FIG. 19 is a timing diagram for describing a programming mode of a nonvolatile memory according to an embodiment of the present invention.
  • FIG. 20 is a timing diagram for describing erase mode of a nonvolatile memory according to an embodiment of the present invention
  • FIG. 11 is a schematic block diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention.
  • the nonvolatile semiconductor memory device of this example includes a memory cell array MCARR, page buffer blocks NWPBB ⁇ 63 : 0 >, first and second global input lines GDI and nGDI, a global output line GDOUT, y address signal lines Yp ⁇ 7 : 0 >, Yq ⁇ 7 : 0 > and Yr ⁇ 7 : 0 >, read latch signal lines LCH ⁇ 7 : 0 >, and page buffer decoders NWDE ⁇ 63 : 0 >.
  • the memory cell array MCARR includes a matrix array of memory cells, word lines WL (not shown in FIG. 11 ) and bit lines BL ⁇ 511 : 0 >.
  • the memory cells are flash memory cell transistors.
  • Internal input lines IDI ⁇ 63 : 0 > and nIDI ⁇ 63 : 0 >, and internal output lines IDOUT ⁇ 63 : 0 >, are connected between the page buffer decoders NWDE ⁇ 63 : 0 > and corresponding page buffer blocks NWPBB ⁇ 63 : 0 >.
  • the first global input line GDI and the second global input line nGDI transmit input data of opposite logic states during predetermined operational intervals, such as a read mode, a program mode and an erase mode.
  • each of the page buffer decoders NWDE ⁇ 63 : 0 > decodes the input data GDI and nGDI, together with the y address data Yq ⁇ 7 : 0 > and Yr ⁇ 7 : 0 >, to output the data of the internal input lines IDI ⁇ 63 : 0 > and nIDI ⁇ 63 : 0 >.
  • each of the page buffer decoders NWDE ⁇ 63 : 0 > provides data corresponding to the data on the internal output lines IDOUT ⁇ 63 : 0 > to the global output line GDOUT.
  • the page buffer blocks NWPBB ⁇ 63 : 0 > are responsive to the latch signal lines LCH ⁇ 7 : 0 > and the y address Yp ⁇ 7 : 0 >.
  • the page buffer blocks NWPBB ⁇ 63 : 0 > function to temporarily store and then transmit input data corresponding to data on the internal input lines IDI ⁇ 63 : 0 > and nIDI ⁇ 63 : 0 > to the bit lines BL ⁇ 511 : 0 >, and to temporarily store and then transmit output data corresponding to data on bit lines BL ⁇ 511 : 0 > to the internal output lines IDOUT ⁇ 63 : 0 >.
  • FIG. 12 is a view of a portion of the memory cell array MCARR of FIG. 11 according to the example of this embodiment.
  • FIG. 12 illustrates circuitry associated with the memory cell strings of the first bit line BL 0 of FIG. 11 .
  • Bit lines BL ⁇ 511 : 1 > are similarly configured.
  • the memory cell array MCARR generally includes a matrix array of memory cells MC, a plurality of word lines WL ⁇ n- 1 : 0 >, and a plurality of bit lines BL ⁇ 511 : 0 >.
  • the memory cells MC of the nonvolatile semiconductor memory device of the embodiment are NAND-type flash memory cells.
  • FIG. 12 illustrates the first and second strings STe 0 and STo 0 connected to the even and odd bit lines BLe 0 and BLo 0 which make up the bit line BL 0 of FIG. 11 .
  • Each string STe 0 and STo 0 includes transistors at opposite ends of the memory cells MC which are connected to select lines SSL and GSL. As shown, the select lines SSL and GSL run parallel to the word lines WL ⁇ n- 1 : 0 >. Also, each string STe 0 and STo 0 terminates at a common source line CSL.
  • bit line control block BLCONBK The even and odd bit lines are connected to a bit line control block BLCONBK.
  • bit line control block BLCONBK is described here as forming part of the memory cell array MCARR.
  • bit line control block BLCONBK may also be viewed as a circuit that is separate and distinct from the memory cell array MCARR.
  • the bit line control block BLCONBK selects one of the even bit line BLe 0 and the odd bit line BLo 0 and connects the selected bit line to the bit line BL 0 .
  • This operation is executed by the transistor 515 which is controlled by the sense node blocking signal SOBLK, and by the transistors 513 and 514 which are respectively controlled by the even bit line selection signal BLSLTe and the odd bit line selection signal BLSLTo.
  • bit line control block BLCONBK functions to pre-charge or condition the voltages of the even bit line BLe 0 and the odd bit line BLo 0 in the read, program mode and erase operational modes.
  • Transistors 511 and 512 are provided for this purpose. That is, transistor 511 is responsive to an even shielding signal SHLDe to selectively connect a bit line power voltage BLPWR to the even bit line BLe 0 , and the transistor 512 is responsive to an odd shielding signal SHLDo to selectively connect the bit line power voltage BLPWR to the odd bit line BLo 0 .
  • FIG. 13 illustrates an example of the page buffer block NWPBB 0 illustrated in FIG. 11 .
  • the remaining page buffer blocks NWPBB ⁇ 63 : 1 > have similar configurations.
  • the page buffer block NWPBB 0 of FIG. 13 includes a plurality of page buffers NWBUF ⁇ 7 : 0 >, an internal output line IDOUT 0 , a first internal input line IDI 0 , and a second internal input line nIDI 0 .
  • the page buffers NWBUF ⁇ 7 : 0 > store data that is transmitted to and received from the bit lines BL ⁇ 7 : 0 >, respectively.
  • the internal output line IDOUT 0 is a common internal output line for the page buffer block NWPBB 0 , and transmits output data corresponding to the data stored in any one of the page buffers NWBUF ⁇ 7 : 0 >.
  • the first internal input line IDI 0 and the second internal input line nIDI 0 supply signals which control the storing of data in the page buffers NWBUF ⁇ 7 : 0 > based on input data.
  • the page buffers NWBUF ⁇ 7 : 0 > included in the page buffer block NWPBB 0 are positioned in a stacked structure, i.e., juxtaposed between the page buffer decoder NWDE 0 and the memory cell array MCARR.
  • Each of the page buffers NWBUF ⁇ 7 : 0 > of the page buffer block NWPBB is connected between the internal input lines IDI 0 and nIDI 0 and a corresponding one of bit lines BL ⁇ 7 : 0 >. Further, each is equipped with a transistor 870 a that is responsive to a bit line shutoff signal BLSHF to connect the corresponding bit line BL ⁇ 7 : 0 > to a respective sense node NSEN ⁇ 7 : 0 >.
  • each of the page buffers NWBUF ⁇ 7 : 0 > receives a respective one of y address signals Yp ⁇ 7 : 0 >.
  • these address signals Yp ⁇ 7 : 0 > are connected directly to the respective page buffers NWBUF ⁇ 7 : 0 > (also see FIG. 1 ).
  • the Yp ⁇ 7 : 0 > address signals are referred to as buffer selection address signals.
  • the internal output line IDOUT 0 preferably extends in a direction in which the page buffers NWBUF ⁇ 7 : 0 > are stacked. As such, variations in transmission line distances from the respective page buffers NWBUF ⁇ 7 : 0 > to the internal output line IDOUT 0 are minimized. This in turn increases signal uniformity when loading data from the page buffers NWBUF ⁇ 7 : 0 > to the internal output line IDOUT 0 , thus enhancing the sensing margin of the non-volatile memory.
  • the internal output line IDOUT 0 is shared among the page buffers NWBUF ⁇ 7 : 0 >.
  • NWBUF ⁇ 7 : 0 > One advantage resulting from this configuration is that the problems associated with parasitic coupling of the internal data lines IDB ⁇ 7 : 0 > of a conventional memory (see FIG. 10 ) can be avoided.
  • FIG. 14 illustrates an example of the page buffers NWBUF 0 of FIG. 13 .
  • the remaining page buffers NWBUF ⁇ 7 : 1 > are similarly configured.
  • the page buffer NWBUF 0 includes the sensing node NSEN 0 , a latch unit 810 , a latch transmission unit 820 , a latch driving unit 825 , a sensing response unit 830 , an output driving unit 840 , a buffer selection unit 850 , a sensing setting unit 860 , a bit line shutoff unit 870 and the internal output line IDOUT 0 .
  • the sensing node NSEN 0 receives data provided from the bit line BL 0 , and is connected to the bit line BL 0 through the bit line shutoff unit 870 .
  • the bit line shutoff unit 870 controls the connection of the bit line BL 0 to the sensing node NSEN 0 in response to a bit line shutoff signal BLSHF.
  • the bit line shutoff unit 870 is implemented using a bit line shutoff transistor 870 a , which is a low voltage NMOS transistor gated in response to the bit line shutoff signal BLSHF.
  • the latch unit 810 includes a latch node NLAT which stores data corresponding to data of the bit line BL 0 .
  • the latch driving unit 825 is enabled in response to the buffer selection address Yp 0 to provide a predetermined latch driving voltage.
  • the latch driving voltage is the ground voltage VSS, and is independent of the data on the first and second internal input lines IDI 0 and nIDI 0 provided to the latch transmission unit 820 .
  • the latch driving unit 825 of this example includes a latch driving transistor 825 a , and preferably, the latch driving transistor 825 a is an NMOS transistor that is gated in response to the buffer selection address Yp 0 and has a source terminal connected to the ground voltage VSS.
  • the latch transmission unit 820 of this example includes first and second latch transmission transistors 820 a and 820 b .
  • the first latch transmission transistor 820 a provides the latch driving voltage provided from the latch driving transistor 825 a to a node N 810 a of the latch unit 810 in response to the first internal input line IDI 0 .
  • the first latch transmission transistor 820 a is connected to the latch driving transistor 825 a and is gated in response to the data on the first internal input line IDI 0 .
  • the first latch transmission transistor 820 a provides the ground voltage VSS to the node N 810 a of the latch unit 810 .
  • the second latch transmission transistor 820 b of this example provides the latch driving voltage provided from the latch driving transistor 825 a to the latch node NLAT of the latch unit 810 in response to the second internal input line nIDI 0 .
  • the second latch transmission transistor 820 b is connected in series with the latch driving transistor 825 a and is gated in response to the data on the second internal input line NIDI 0 . Therefore, if data of a logic “H” state is applied to the second internal input line nIDI 0 when the buffer selection address Yp 0 is in a logic “H” state, the second latch transmission transistor 820 b provides the ground voltage VSS to the latch node NLAT of the latch unit 810 .
  • RBIN 1 and RBIN 2 denote buffer input paths through which the latch driving voltage is transmitted to the latch unit 810 . That is, the transmission path through the latch driving transistor 825 a and the first latch transmission transistor 820 a to the latch node NLAT is designated as the first buffer input path RBIN 1 , and the transmission path through the latch driving transistor 825 a and the second latch transmission transistor 820 b to the latch node NLAT is designated as the second buffer input path RBIN 2 .
  • the sensing response unit 830 of this example is driven by the sensing node NSEN 0 to selectively transmit a sensing response voltage to the latch transmission unit 820 , to thereby control the data stored at the latch node NLAT.
  • the sensing response voltage is the ground voltage VSS.
  • the sensing response unit 830 includes, for example, a sensing response transistor 830 a and an output sensing transistor 830 b.
  • the sensing response transistor 830 a is an NMOS transistor that is gated in response to the data on the sensing node NSEN 0 .
  • the output sensing transistor 830 b is an NMOS transistor that is arranged in series with the sensing response transistor 820 a and is provided with a source terminal connected to the ground voltage VSS.
  • the sensing response transistor 830 a is turned on, the output sensing transistor 830 b is responsive to a read latch signal LCH to provide the sensing response voltage to the latch unit 810 through the latch transmission unit 820 .
  • the latch node NLAT stores data corresponding to the sensing node NSEN 0 in response to the sensing response voltage.
  • the sensing setting unit 860 sets the sensing node NSEN 0 at a predetermined setting voltage.
  • the setting voltage is a supply voltage VDD
  • the sensing setting unit 860 includes a sensing setting transistor 860 a .
  • the sensing setting transistor 860 a is preferably a PMOS transistor that has a source terminal connected to the supply voltage VDD (for example, 2.2V) and is gated in response to a sensing setting signal/PLOAD.
  • the output driving unit 840 is enabled in response to the buffer selection address Yp 0 . When enabled, the output driving unit 840 drives the internal output line IDOUT 0 to a predetermined drive voltage in response to the data stored on the latch node NLAT. As is apparent in FIG. 14 , the internal output line IDOUT 0 is separated from and electrically isolated from the latch node NLAT and the buffer input paths RBIN 1 and RBIN 2 .
  • the output driving unit 840 includes, for example, a first output driving transistor 840 a and a second output driving transistor 840 b .
  • the first output driving transistor 840 a is gated by the data stored on the latch node NLAT of the latch unit 810 .
  • the first output driving transistor 840 a is turned on when the data stored on the latch node NLAT of the latch unit 810 is logic “H”.
  • the second output driving transistor 840 b is connected in series with the first output driving transistor 840 a .
  • the second output driving transistor 840 b is gated in response to the buffer selection address Yp 0 to drive the internal output line IDOUT 0 to the drive voltage.
  • the drive voltage is the ground voltage VSS which is connected to the source terminal of the first output driving transistor 840 a .
  • the internal output line IDOUT 0 is driven to the ground voltage VSS in response to a transition of the buffer selection address Yp 0 to the logic “H” state.
  • the buffer selection unit 850 of this example controls the connection of the latch node NLAT with the sensing node NSEN 0 .
  • the buffer selection unit 850 includes a buffer selection transistor 850 a , which is an NMOS transistor gated in response to a buffer selection signal PBSLT.
  • PBSLT buffer selection signal
  • the buffer selection transistor 850 a When the voltage level of the buffer selection signal PBSLT is changed to a logic “H” state, the data on the latch node NLAT is transmitted to the sensing node NSEN 0 through the buffer selection transistor 850 a , where it can then be transmitted to the bit line BL 0 .
  • FIG. 15 illustrates an example of the page buffer decoder NWDE 0 shown in FIG. 11 .
  • the remaining page buffer decoders NWDE ⁇ 63 : 1 > may be similarly configured.
  • the page buffer decoder NWDE 0 has two primary functions. First, the page buffer decoder NWDE 0 transmits output data corresponding to data on the internal output line IDOUT 0 to the global output line GDOUT. Second, the page buffer decoder NWED 0 transmits data corresponding to input data on the first global input line GDI and the second global input line nGDI to the first internal input line IDI 0 and the second internal input line nIDI 0 , respectively.
  • the page buffer decoder NWED 0 in the example of FIG. 15 includes first to third decoder logic gates 1201 , 1203 and 1205 , an inverter 1206 , and a decoder transistor 1207 .
  • the y address signals Yq ⁇ 7 : 0 > are referred to as main selection addresses, and the y address signals Yr ⁇ 7 : 0 > are referred to as sub-selection addresses (see FIG. 11 ).
  • the first decoder logic gate 1201 performs a logic operation on a main selection address Yq 0 and a sub-selection address Yr 0 , and outputs the logic operation result as a block decoding signal /BLDEC.
  • the first decoder logic gate 1201 is a NAND gate which executes NAND operation on the main selection address Yq 0 and the sub-selection address Yr 0 , and outputs the NAND operation results as the block decoding signal/BLDEC.
  • the block decoding signal/BLDEC is activated to a logic “L” state.
  • the second decoder logic gate 1203 is enabled in response to the block decoding signal/BLDEC, and provides logic operation results to the first internal input line IDI 0 in accordance with data on the first global input line GDI.
  • the second decoder logic gate 1203 is a NOR gate which executes a NOR operation on the block decoding signal/BLDEC and the first global input line GDI.
  • the second decoder logic gate 1203 inverts the data on the first global input line GDI and provides the inverted result to the first internal input line IDI 0 when the block decoding signal/BLDEC is in a logic “L” state (i.e., when both the main selection address Yq 0 and the sub-selection address Yr 0 are in a logic “H” state).
  • the third decoder logic gate 1205 is enabled in response to the block decoding signal/BLDEC and provides logic operation results to the second internal input line nIDI 0 in accordance with data on the second global input line nGDI.
  • the third decoder logic gate 1205 is a NOR gate which executes a NOR operation on the block decoding signal/BLDEC and the second global input line nGDI.
  • the third decoder logic gate 1205 inverts data on the second global input line nGDI and provides the inverted data to the second internal input line nIDI 0 thereof when the block decoding signal/BLDEC is in a logic “L” state (i.e., when both the main selection address Yq 0 and the sub-selection address Yr 0 are in a logic “H” state).
  • the inverter 1206 inverts the block decoding signal/BLDEC to gate the decoder transistor 1207 .
  • the decoder transistor 1207 provides data on the internal output line IDOUT 0 to the global output line GDOUT when the block decoding signal/BLDEC is activated to a logic “L” state.
  • the nonvolatile memory includes 64 page buffer decoders NWDE ⁇ 63 : 0 >.
  • the page buffer decoders NWDE ⁇ 63 : 0 > are individually selected based on a combination of the main selection addresses Yq ⁇ 7 : 0 > and sub-selection addresses Yr ⁇ 7 : 0 >.
  • the main selection addresses Yq ⁇ 7 : 0 > are used to select one of 8 groups (having 8 buffer decoders each) among the 64 page buffer decoders NWDE ⁇ 63 : 0 >, and the sub-selection addresses Yr ⁇ 7 : 0 > are used to select any one of 8 page buffer decoders contained in the selected group.
  • the buffer selection addresses Yp ⁇ 7 : 0 > are used to select individual ones of 8 page buffers associated with the selected buffer decoder.
  • the total number of column address bus lines is 24, which compares quite favorably to the 40 column address lines of the conventional memory device illustrated in FIG. 8 .
  • internal output line IDOUT 0 is electrically isolated from the latch node NLAT and the buffer input paths RBIN 1 and RBIN 2 .
  • distortion of data stored on the latch node NLAT of a selected page buffer e.g., NWBUF 0
  • other page buffers e.g., NWBUF ⁇ 7 : 1 >
  • a read operational mode will be described first with reference to FIGS. 16A and 16B .
  • FIG. 16A is a flowchart for describing a method of operating a page buffer NVVBUF to output data stored in a selected memory cell MCsel (see FIG. 12 ).
  • the latch node NLAT is initialized to data of a logic “H” state (a “first logic state”) or a logic “L” state (a “second logic state”).
  • the initialization of the latch node NLAT may be performed by either of the first internal input line IDI 0 and the second internal input line nIDI 0 .
  • the latch node NLAT is initialized to data of the second logic state.
  • the buffer selection address Yp 0 becomes a logic “H” pulse
  • the second internal input line nIDI 0 also becomes a logic “H” pulse.
  • the first internal input line IDI 0 maintains a logic “L” state.
  • the latch node NLAT is initialized to data of a logic “L” state, that is, the second logic state.
  • the latch node NLAT is initialized to data of the first logic state.
  • the buffer selection address Yp 0 becomes a logic “H” pulse
  • the first internal input line IDI 0 also becomes a logic “H” pulse.
  • the second internal input line nIDI 0 maintains a logic “L” state.
  • the latch node NLAT is initialized to data of a logic “H” state, that is, the first logic state.
  • step S 950 the data developed on the bit line BL 0 , which corresponds to the data stored in the selected memory cell MCsel, is stored on the latch node NLAT.
  • FIG. 16B is a flowchart for describing the steps S 951 , S 953 and S 955 which may be executed as the step S 950 of FIG. 16A .
  • execution of step S 951 a is considered preferable, but may be omitted.
  • the sensing node NSEN 0 is adjusted to the supply voltage VDD, that is, the setting voltage, by the sensing setting transistor 860 a of the sensing setting unit 860 .
  • the setting voltage controls the sensing response unit 830 (enabled in response to the read latch signal LCH) to provide the sensing response voltage to the latch transmission unit 820 .
  • the bit line shutoff signal BLSHF is changed to a logic “L” state.
  • Step S 951 includes steps S 951 a and S 951 b .
  • the voltage level of the sensing setting signal/PLOAD is maintained at a first preliminary voltage VPRE 1 for a predetermined period of time, to prevent the undershooting of supply voltage VDD.
  • the sensing setting signal/PLOAD is changed to a logic “L” state.
  • Step S 953 the sensing response unit 830 provides the sensing response voltage to the latch transmission unit 820 in response to the data developed on the bit line BL 0 .
  • Step S 953 includes steps S 953 a , S 953 b and S 953 c.
  • the sensing setting signal/PLOAD becomes a logic “H” state. As such, the setting state of the sensing node NSEN 0 is released, and the sensing node NSEN 0 is changed to a floating state. Further, at step S 953 b , the bit line shutoff transistor 870 a is turned on, so that the floating sensing node NSEN 0 is connected to the bit line BL 0 . Therefore, the sensing node NSEN 0 receives the data developed on the bit line BL 0 .
  • the selected memory cell MCsel is an OFF cell, the voltage level of the sensing node NSEN 0 is maintained at about the supply voltage VDD.
  • the selected memory cell MCsel is an ON cell, the voltage level of the sensing node NSEN 0 is maintained at about the ground voltage VSS.
  • the sensing response unit 830 selectively provides a sensing response voltage according to the sensing node NSEN 0 to the latch transmission unit 820 . That is, if the read latch signal LCH is generated as an “H” pulse when the selected memory cell MCsel is an OFF cell and the voltage level of the sensing node NSEN 0 is maintained at about the supply voltage VDD, the sensing response unit 830 provides the sensing response voltage (VSS in this example) to the latch transmission unit 820 .
  • the sensing response voltage is not provided to the latch transmission unit 820 even though the read latch signal LCH is generated as an “H” pulse.
  • step S 955 the latch node NLAT is flipped in response to the sensing response voltage supplied to the latch transmission unit 820 .
  • the latch node NLAT is initialized to data of the second logic state.
  • the first internal input line IDI 0 is in a logic “H” state and the second internal input line NIDI 0 is in a logic “L” state. Therefore, when the selected memory cell MCsel is an OFF cell, that is, a programmed cell, the latch node NLAT is flipped from a logic “L” state (second logic state) to a logic “H” state (first logic state). However, when the selected memory cell MCsel is an ON cell, that is, an erased cell, the latch node NLAT maintains the logic “L” state (second logic state).
  • the latch node NLAT is initialized to data of a first logic state.
  • the first internal input line IDI 0 is in a logic “L” state
  • the second internal input line nIDI 0 is in a logic “H” state at step S 955 . Therefore, if the selected memory cell MCsel is an OFF cell, that is, an unerased cell, the latch node NLAT is flipped from a logic “H” state (first logic state) to a logic “L” state (second logic state).
  • the selected memory cell MCsel is an ON cell, that is, an erased cell
  • the latch node NLAT maintains the logic “H” state (first logic state).
  • the output driving unit 840 is controlled by the data stored on the latch node NLAT. Therefore, the internal output line IDOUT 0 is selectively driven to a drive voltage, that is, the ground voltage VSS. That is, if the data stored on the latch node NLAT is logic “H”, the internal output line IDOUT 0 is driven to the ground voltage VSS in response to the buffer selection address Yp 0 . However, if the data stored on the latch node NLAT is logic “L”, the internal output line IDOUT 0 maintains its initial logic state, which is the supply voltage VDD, even when the buffer selection address Yp 0 changes to a logic “H” state.
  • FIG. 17 is a normal read operational mode (read mode) timing diagram showing various signal voltages and node voltages of the nonvolatile memory device illustrated in the examples of FIGS. 11 through 15 . Again, reference should be made to these earlier figures in the explanation that follows.
  • the read mode illustrated in FIG. 17 is divided into six intervals, namely, a bit line discharge and page buffer reset interval (hereinafter referred to as a “READ 1 interval”), a bit line precharge interval (hereinafter referred to as a “READ 2 interval”), a bit line develop interval (hereinafter referred to as a “READ 3 interval”), a sensing interval (hereinafter referred to as a “READ 4 interval”), a recovery interval (hereinafter referred to as a “READ 5 interval”), and a data fetch interval (hereinafter referred to as a “READ 6 interval”).
  • a bit line discharge and page buffer reset interval hereinafter referred to as a “READ 1 interval”
  • a bit line precharge interval hereinafter referred to as a “READ 2 interval”
  • a bit line develop interval hereinafter referred to as a “READ 3 interval”
  • a sensing interval hereinafter referred to as a “READ 4 interval”
  • the “READ 1 interval” is divided into a page buffer reset interval (hereinafter referred to as a “READ 1 a interval”) and a bit line discharge interval (hereinafter referred to as a “READ 1 b interval”).
  • the latch node NLAT of the page buffer is reset to a logic “L” state, that is, the ground voltage VSS.
  • the even bit line BLe 0 , the odd bit line BLo 0 and the bit line BL 0 are discharged to the ground voltage VSS, that is, data of a logic “L” state.
  • Reset of the latch node NLAT during the READ 1 a interval occurs as follows.
  • the buffer selection address Yp 0 since the buffer selection address Yp 0 is in a logic “H” state, the latch driving transistor 825 a is turned ON (tR 1 ).
  • the block decoding signal/BLDEC is changed to a logic “L” state (tR 2 ).
  • the first global input line GDI is logic “H”
  • the second global input line nGDI is logic “L”.
  • the first internal input line IDI 0 is logic “L”
  • the second internal input line nIDI 0 is logic “H” (tR 3 ). Therefore, the first latch transmission transistor 820 a is turned OFF, and the second latch transmission transistor 820 b is turned ON. Accordingly, the node N 810 a of the latch unit 810 is changed to a logic “H” state, and the latch node NLAT is reset to a logic “L” state.
  • a read voltage VREAD (for example, 5V) is applied to unselected word lines WL ⁇ n- 2 : 0 > and the ground voltage VSS is applied to a selected word line WLn- 1 . Further, the read voltage VREAD is applied to both the string selection line SSL and the ground selection line GSL, and the ground voltage VSS is applied to the common source line CSL.
  • bit line voltage line BLPWR maintains the ground voltage VSS, and the even shielding signal SHLDe, the odd shielding signal SHLDo, the voltage levels of the even bit line selection signal BLSLTe and the sensing node blocking signal SOBLK are changed to the supply voltage VDD. Therefore, the bit lines BLe, BLe 0 and BLo 0 are discharged to the ground voltage VSS, that is, data of a logic “L” state.
  • the even bit line BLe 0 and the bit line BL 0 are precharged to a predetermined precharge voltage (for example, 0.8V) to sense a data value in the selected memory cell MCsel.
  • a predetermined precharge voltage for example, 0.8V
  • a first voltage is applied to the selected word line WLn- 1
  • a second voltage is applied to the remaining unselected word lines WL ⁇ n- 2 : 0 >.
  • the first voltage is the ground voltage VSS
  • the second voltage is the read voltage VREAD. Therefore, the ON/OFF state of the selected memory cell MCsel is controlled by the data stored therein. That is, if the data stored in the selected memory cell MCsel is logic “1”, the selected memory cell MCsel is in an ON state, while if the stored data is logic “0”, the selected memory cell MCsel is in an OFF state.
  • the even shielding signal SHLDe is changed to a logic “L” state to turn off the NMOS transistor 511 for connecting the even bit line BLe 0 to the bit line voltage line BLPWR (tR 4 ). Therefore, the discharge of the even bit line BLe 0 and the bit line BL 0 is released.
  • the odd shielding signal SHLDo is maintained at the supply voltage VDD, so that the NMOS transistor 512 maintains an ON state. Therefore, the odd bit line BLo 0 is maintained at the ground voltage VSS, and functions as a shielding line between even bit lines BLe 0 .
  • the voltage of the sensing setting signal /PLOAD is dropped from the supply voltage VDD to a first preliminary voltage VPRE 1 for a predetermined period of time, and then drops to the ground voltage VSS (tR 5 ). Therefore, the sensing setting transistor 860 a is turned on, so that the sensing node NSEN 0 is changed to the supply voltage VDD, which is the setting voltage.
  • the preliminary voltage VPRE 1 of the sensing setting signal /PLOAD is about 1.0V, which is between the ground voltage VSS and the supply voltage VDD.
  • the sensing setting signal /PLOAD is maintained at the first preliminary voltage VPRE 1 for the predetermined period of time so as to reduce power noise resulting from undershooting.
  • the bit line shutoff signal BLSHF is changed to a second preliminary voltage VPRE 2 , which is between the supply voltage VDD and the ground voltage VSS.
  • the sensing node NSEN 0 and the bit line BL 0 become electrically connected to each other.
  • the bit line shutoff signal BLSHF gates the bit line shutoff transistor 870 a at the second preliminary voltage VPRE 2 , thus allowing the bit lines BL 0 and BLe 0 to be pre-charged to a given level due to current provided from the sensing setting transistor 860 a .
  • the given level is lower than the second preliminary voltage VPRE 2 by the threshold voltage of the bit line shutoff transistor 870 a.
  • the voltage levels of the even bit line selection signal BLSLTe and the sensing node blocking signal SOBLK are changed to the read voltage VREAD such that sufficient current flows through the bit line shutoff transistor 870 a.
  • the READ 3 interval is executed in which the bit line BL 0 senses data stored in the selected memory cell MCsel and develops the data.
  • the bit line shutoff signal BLSHF is the ground voltage VSS to turn OFF the bit line shutoff transistor 870 a (tR 6 ).
  • the bit line BL 0 becomes electrically isolated from the sensing node NSEN 0 , and the bit line BL 0 proceeds to develop the data.
  • the selected memory cell MCsel is an ON cell, data on the bit line BL 0 is discharged to the common source line CSL. Therefore, the voltage level of the bit line BL 0 approximates the ground voltage VSS. On the other hand, if the selected memory cell is an OFF cell, the voltage level of the bit line BL 0 remains substantially unchanged (except for variations resulting from leakage current).
  • the sensing setting transistor 860 a maintains an ON state for most of the READ 3 interval, but is turned OFF (tR 8 ) immediately before the end of the READ 3 interval.
  • the sensing node NSEN 0 thus maintains the supply voltage VDD and becomes a floating state.
  • the READ 4 interval is executed in which the data developed on the bit line BL 0 , that is, data corresponding to the voltage level of the bit line, is stored on the latch node NLAT of the page buffer NWBUF 0 .
  • the floating state of the sensing node NSEN 0 generated during the READ 3 interval is initially maintained while the bit line shutoff signal BLSHF is changed to a third preliminary voltage VPRE 3 to turn on the bit line shutoff transistor 870 a.
  • the third preliminary voltage VPRE 3 is between the ground voltage VSS and the supply voltage VDD, and is lower than the second preliminary voltage VPRE 2 by a predetermined voltage difference which corresponds to a sensing margin.
  • the voltage level of the sensing node NSEN 0 is thus determined according to the voltage level developed on the bit line BL 0 .
  • the data value on the first internal input line IDI 0 changes to a logic “H” state (tR 9 ), so that the first latch transmission transistor 820 a is turned ON.
  • the latch node NLAT In response to the read latch signal LCH, the latch node NLAT stores data on the sensing node NSEN 0 as determined by the voltage level of the bit line BL 0 , such data corresponding to the data stored in the selected memory cell MCsel.
  • the selected memory cell MCsel is an OFF cell
  • the voltage level of the bit line BL 0 and the sensing node NSEN 0 may slightly drop from the pre-charged voltage level due to the influence of leakage current
  • the voltage level is maintained at a logic “H” state since the bit line shutoff transistor 870 a cannot be turned on due to the difference between the second and third preliminary voltages VPRE 2 and VPRE 3 . Therefore, if the read latch signal LCH is enabled to a logic “H” state, the data on the latch node NLAT is flipped to a logic “H” state.
  • the READ 5 interval is executed in which the bit line BL 0 and the sensing node NSEN 0 are reset.
  • the even shielding signal SHLDe is changed to the supply voltage VDD, and both the even bit line selection signal BLSLTe and the sensing node blocking signal SOBLK are changed from the read voltage VREAD to the supply voltage VDD. Therefore, the bit line BL 0 and the sensing node NSEN 0 are reset to the ground voltage VSS (tR 11 ).
  • the unselected word lines WL ⁇ n- 2 : 0 >, the string selection line SSL and the ground selection line GSL are all changed from the read voltage VREAD to the ground voltage VSS.
  • the READ 6 interval is executed in which data corresponding to the latch node NLAT (stored during the READ 4 interval) is output to the global output line GDOUT through the internal output line IDOUT 0 .
  • the buffer selection address Yp 0 and the block decoding signal/BLDEC are activated in the form of respective pulse signals.
  • data corresponding to the latch node NLAT is transmitted to the global output line GDOUT through the internal output line IDOUT 0 .
  • the global output line GDOUT is pre-charged to the supply voltage VDD by an output line pre-charge circuit (not shown) before the block decoding signal/BLDEC is activated.
  • a program operational mode (program mode) according to an embodiment of the present invention will now be described with reference to the flowchart of FIG. 18 .
  • the program mode is executed to load input data in a selected memory cell MCsel of the memory cell array.
  • the latch node NLAT is initialized.
  • the latch node NLAT is initialized to data of a first logic state (that is, a logic “H” state) or a second logic state (that is, a logic “L” state) by either the first internal input line IDI 0 or the second internal input line nIDI 0 .
  • the latch node NLAT is initialized to a program inhibited state, which is a first logic state (that is, logic “H” state), by the first internal input line IDI 0 .
  • the latch transmission unit 820 provides the latch driving voltage, which is the ground voltage VSS provided from the latch driving unit 825 , to the latch unit 810 by either of the first and second internal input lines IDI 0 and NIDI 0 . Further, the latch unit 810 loads data of a first logic state (that is, logic “H” state) or a second logic state (that is, logic “L” state) on the latch node NLAT using the latch driving voltage.
  • a first logic state that is, logic “H” state
  • a second logic state that is, logic “L” state
  • the buffer selection address Yp 0 becomes a logic “H” pulse
  • the first internal input line IDI 0 also becomes a logic “H” pulse.
  • the second internal input line nIDI 0 maintains a logic “L” state.
  • the latch node NLAT maintains the program inhibited state, which is a logic “H” state.
  • the buffer selection address Yp 0 becomes a logic “H” pulse
  • the second internal input line nIDI 0 also becomes a logic “H” pulse.
  • the first internal input line IDI 0 maintains a logic “L” state.
  • the latch node NLAT is then changed from a logic “H” state to a logic “L” state.
  • the first internal input line IDI 0 and the second internal input line nIDI 0 have opposite logic states. If data of a logic “H” state is transmitted to the first internal input line IDI 0 when the buffer selection address Yp 0 is in a logic “H” state, the data of a logic “H” state is stored on the latch node NLAT of the latch unit 810 . If instead data of a logic “H” state is transmitted to the second internal input line nIDI 0 , the data of a logic “L” state is stored on the latch node NLAT of the latch unit 810 .
  • step S 1150 data loaded on the latch node NLAT is transmitted to the bit line BL 0 . This process is explained in more detail below as steps S 1151 and S 1153 .
  • the buffer selection unit 850 is controlled to connect the latch node NLAT to the sensing node NSEN 0 , and ultimately, to the bit line BL 0 . That is, the buffer selection signal PBSLT changes to a logic “H” level so as to turn ON the buffer selection transistor 850 a . The data on the latch node NLAT is then transmitted to the sensing node NSEN 0 .
  • the bit line shutoff unit 870 is controlled to connect the sensing node NSEN 0 with the bit line BL 0 . More specifically, in this example, the bit line shutoff signal BLSHF changes to a logic “H” level so as to turn ON the bit line shutoff transistor 870 a . The data on the sensing node NSEN 0 is then transmitted to the bit line BL 0 .
  • the selected memory cell MCsel is programmed to correspond to the data transmitted to the bit line BL 0 .
  • FIG. 19 is a program mode timing diagram showing various signal voltages and node voltages of the nonvolatile memory device illustrated in the examples of FIGS. 11 through 15 . Again, reference should be made to these earlier figures in the explanation that follows.
  • the timing diagram of FIG. 19 is divided into eight intervals, namely, a page buffer setup interval (hereinafter referred to as a “PROG 1 interval”), a data loading interval (hereinafter referred to as a “PROG 2 interval”), a high voltage enabling interval (hereinafter referred to as a “PROG 3 interval”), a bit line setup interval (hereinafter referred to as a “PROG 4 interval”), a program execution interval (hereinafter referred to as a “PROG 5 interval”), a recovery interval (hereinafter referred to as a “PROG 6 interval”), a verification read interval (hereinafter referred to as a “PROG 7 interval”), and a Y-scan interval (hereinafter referred to as a “PROG 8 interval”).
  • PROG 1 interval page buffer setup interval
  • PROG 2 interval data loading interval
  • PROG 3 interval high voltage enabling interval
  • PROG 4 interval bit line setup interval
  • PROG 5 interval program execution interval
  • PROG 6 interval
  • the latch node NLAT is adjusted to a program inhibited state before externally applied data is loaded.
  • the program inhibited state represents a state in which the execution of cell programming is not required with respect to externally applied specific data. In this example, when data of a logic “H” state is externally applied, cell programming is not required.
  • the buffer selection address Yp 0 is in a logic “H” state (tP 1 ) so as to turn ON the latch driving transistor 825 a .
  • the block decoding signal/BLDEC is activated to a logic “L” state.
  • the first global input line GDI is an active pulse having a logic “L” state
  • the second global input line nGDI is in a logic “H” state.
  • the first internal input line IDI 0 is an active pulse having a logic “H” state (tP 2 ), and the second internal input line nIDI 0 is in a logic “L” state.
  • the first latch transmission transistor 820 a is therefore temporarily turned ON, and the second latch transmission transistor 820 b is in an OFF state. In this manner, the latch node NLAT is set to the program inhibited state, i.e., a logic “H” state.
  • the PROG 2 interval is executed next in which externally applied data is loaded on the latch node NLAT of the page buffer NWBUF 0 .
  • data corresponding to the externally input data is stored on the latch node NLAT in response to the first internal input line IDI 0 or the second internal input line NIDI 0 . Further, the data stored on the latch node NLAT is provided through the buffer input paths RBIN 1 and RBIN 2 . The logic state of the data stored on the latch node NLAT in response to the first internal input line IDI 0 is opposite to the logic state of the data stored on the latch node NLAT in response to the second internal input line nIDI 0 .
  • the data stored on the latch node NLAT in response to the first internal input line IDI 0 is logic “H”
  • the data stored on the latch node NLAT in response to the second internal input line nIDI 0 is logic “L”.
  • the buffer selection address Yp 0 is logic “H”. Since both the main selection address Yq 0 and the sub-selection address Yr 0 are both logic “H”, the block decoding signal/BLDEC is logic “L”. At this time, the first global input line GDI or the second global input line nGDI is changed to a logic “H” state.
  • the second global input line nGDI is changed to a logic “L” state. More precisely, the first internal input line IDI 0 is changed to a logic “L” state, and the second internal input line nIDI 0 is changed to a logic “H” state. Therefore, data of a logic “L” state is stored on the latch node NLAT.
  • the first global input line GDI is changed to a logic “L” state. More precisely, the second internal input line nIDI 0 is changed to a logic “L” state, and the first internal input line IDI 0 is changed to a logic “H” state. Therefore, data of a logic “H” state is stored on the latch node NLAT.
  • the PROG 3 interval is executed next.
  • a group of high voltage pumping circuits included in the nonvolatile semiconductor memory device is enabled. Generally, these circuits are for generating a voltage which is greater than the supply voltage VDD.
  • the high voltage pumping circuit group includes circuits for generating a program voltage (VPGM, for example, 20V), a pass voltage (VPASS, for example, 7 to 9V), a read voltage (VREAD, for example, 5V), etc. Further, the high voltage pumping circuit group may also include a circuit for generating a boosting voltage VPP (not shown) which is utilized by a row decoder (not shown).
  • the supply voltage VDD in the example of the present embodiment is about 2.2 V.
  • the even bit line BLe 0 connected to the selected memory cell MCsel is adjusted to a voltage level corresponding to data stored on the latch node NLAT.
  • the odd bit line BLo 0 that is not connected to the selected memory cell MCsel is adjusted to a program inhibited state.
  • the voltage level of the bit line voltage line BLPWR increases to the supply voltage VDD (tP 5 ). Further, the voltage levels of the even shielding signal SHLDe and the odd shielding signal SHLDo increase to the read voltage VREAD (tP 6 ). Therefore, without causing a voltage drop, the voltage levels of the even bit line BLe 0 and the odd bit line BLo 0 are changed to the supply voltage VDD, which is the voltage of the bit line voltage line BLPWR.
  • the voltage levels of the even bit line selection signal BLSLTe and the sensing node blocking signal SOBLK also increase to the read voltage VREAD.
  • the voltage level of the bit line shutoff signal BLSHF increases to a voltage “VDD+Vt 1 ”.
  • the voltage “Vt 1 ” is a predetermined voltage of about 1.5 V.
  • the voltage level of the even shielding signal SHLDe decreases again to the ground voltage VSS.
  • the buffer selection signal PBSLT is changed to a first reference voltage VREF 1 (tP 8 )
  • the fifth voltage is equal to “VDD+Vt 1 ”
  • the first reference voltage VREF 1 is about 1.3V, which is between the ground voltage VSS and the fifth voltage.
  • the data stored on the latch node NLAT is transmitted to the even bit line BLe 0 connected to the selected memory cell MCsel. That is, if the data stored on the latch node NLAT is logic “L”, the voltage of the even bit line BLe 0 becomes “0V”. Further, if the data stored on the latch node NLAT is logic “H”, the even bit line BLe 0 maintains the supply voltage VDD.
  • the PROG 5 interval is executed next in which data transmitted to the even bit line BLe 0 is stored in the selected memory cell MCsel.
  • the program voltage VPGM which is a third voltage, is applied to the selected word line (tP 10 ).
  • the program voltage VPGM allows data corresponding to the voltage level of the even bit line BLe 0 , that is, the bit line BL 0 , to be programmed in the selected memory cell MCsel.
  • the pass voltage VPASS is applied to the unselected word lines WL ⁇ n- 2 : 0 > (tP 11 ). Therefore, the unselected memory cells MC maintain their ON states without being programmed.
  • the program inhibited state is maintained.
  • the selected memory cell MCsel is programmed by F-N tunneling. Therefore, in this example, the memory cell MCsel in which data of a logic “L” state is stored can be designated as a “programmed cell”.
  • the string selection line SSL is changed to the supply voltage VDD
  • the ground selection line GSL is the ground voltage VSS
  • the common source line CSL has a voltage of about 1.5V.
  • the PROG 6 interval is executed next in which word lines WL ⁇ n- 1 : 0 >, bit lines BL 0 , BLe 0 and BLo 0 , and the sensing node NSEN 0 are discharged to the ground voltage VSS.
  • the bit line voltage line BLPWR maintains the ground voltage VSS.
  • the even shielding signal SHLDe, the odd shielding signal SHLDo, the even bit line selection signal BLSLTe, the sensing node blocking signal SOBLK, and the bit line shutoff signal BLSHF are changed to the supply voltage VDD. Therefore, the word lines WL ⁇ n- 1 : 0 >, the bit lines BL 0 , BLe 0 and BLo 0 , and the sensing node NSEN 0 , are discharged to the ground voltage VSS.
  • the buffer selection signal PBSLT is changed to the ground voltage VSS to electrically isolate the bit line BL 0 from the latch node NLAT.
  • the PROG 7 interval is executed next to sense (verify) the data programmed in the memory cell MCsel.
  • the operation performed during the PROG 7 interval is almost identical to that performed in the previously described read mode.
  • the PROG 7 interval differs from the read mode in that a predetermined verification read voltage is applied to the selected word line WLn- 1 and the resetting of the page buffer NWBUF 0 can be omitted. Since the remaining operations performed during the PROG 7 interval are similar to those of the read mode, a detailed description thereof is omitted here to avoid redundancy.
  • the PROG 8 interval is executed next in which a determination is made as to whether the selected memory cell MCsel has been correctly programmed using the data stored on the latch node NLAT during the PROG 7 interval.
  • erase mode An example of an erase operational mode (erase mode) is described below with reference to the timing diagram of FIG. 20 .
  • FIG. 20 is an erase mode timing diagram showing various signal voltages and node voltages of the nonvolatile memory device illustrated in the examples of FIGS. 11 through 15 . As before, reference should be made to these earlier figures in the explanation that follows.
  • the erase mode timing diagram of FIG. 20 is divided into six intervals, namely, an erase execution interval (hereinafter referred to as an “ERS 1 interval”), a first recovery interval (hereinafter referred to as an “ERS 2 interval”), a second recovery interval (hereinafter referred to as an “ERS 3 interval”), a first verification read interval (hereinafter referred to as an “ERS 4 interval”), a second verification read interval (hereinafter referred to as an “ERS 5 interval”), and a Y-scan interval (hereinafter referred to as an “ERS 6 interval”).
  • an erase execution interval hereinafter referred to as an “ERS 1 interval”
  • ERS 2 interval first recovery interval
  • ERS 3 interval a second recovery interval
  • ERS 4 interval a first verification read interval
  • ERS 5 interval a second verification read interval
  • Y-scan interval hereinafter referred to as an “ERS 6 interval”.
  • an erase voltage VERS is applied to the bulk of the memory cells MC, and a sixth voltage is applied to selected word lines to erase data from corresponding memory cells.
  • the erase voltage VERS is about 20V
  • the sixth voltage is about 0.3V (tE 1 ).
  • unselected word lines are adjusted to a floating state. The voltage of these unselected word lines is close to the erase voltage VERS due to the coupling with the bulk (tE 2 ). Therefore, an erase operation is not performed in the memory cells connected to the unselected word lines.
  • the even shielding signal SHLDe, the odd shielding signal SHLDo, the even bit line selection signal BLSLTe, and the odd bit line selection signal BLSLTo are changed to a voltage “VERS ⁇ Vt 2 ” (tE 3 to tE 6 ), while the sensing node blocking signal SOBLK maintains the supply voltage VDD (tE 7 ).
  • the voltage “Vt 2 ” represents a threshold voltage of high voltage NMOS transistors. In this example, Vt 2 is about 1.3V.
  • the ERS 2 and ERS 3 intervals are executed next in which the voltages of the bulk of the memory cells MC and the bit line BL 0 are controlled to sense the data stored in the selected memory cell.
  • the common source line CSL is discharged. More precisely, the ERS 2 interval is a period during which the bulk of the memory cell MC is floated and a voltage of “VERS ⁇ Vt” charged on the common source line CSL is discharged to the ground voltage VSS.
  • bit lines BL 0 , BLe 0 and BLo 0 are discharged. That is, the bit line voltage line BLPWR is changed to the ground voltage VSS (tE 8 ), and the even shielding signal SHLDe, the odd shielding signal SHLDo, the even bit line selection signal BLSLTe and the odd bit line selection signal BLSLTo are changed to the supply voltage VDD (tE 9 to tE 12 ). Therefore, the bit lines BL 0 , BLe 0 and BLo 0 are discharged to the ground voltage VSS.
  • the ERS 4 interval and the ERS 5 interval are executed next in which the latch node NLAT is set to sense any non-erased data of the memory cell MC. As such, the data in the memory cell MC is sensed and stored on the latch node NLAT.
  • the data of the memory cell MC that is connected to the even bit line BLe 0 and was not erased during the ERS 1 interval is sensed after the latch node NLAT is set to a logic “H” state.
  • the operation performed during the ERS 4 interval is similar to that performed in the normal read mode. However, as described previously in connection with the read mode, the ERS 4 interval and the normal read mode differ with respect to the value reset on the latch node NLAT. That is, in the normal read mode the latch node NLAT is reset to a logic “L” state, while the operation performed during the ERS 4 interval resets the latch node NLAT to a logic “H” state.
  • the operation performed during the ERS 4 interval further differs from the normal read mode in that the sensing of the read data is performed by activation of the second internal input line nIDI 0 during the ERS 4 interval. Remaining operations performed during the ERS 4 interval are closely similar to those performed in the read mode, and accordingly, a detailed description thereof is omitted here to avoid redundancy.
  • the ERS 5 interval is a period during which the data in the memory cell MC connected to the odd bit line BLo 0 was not been erased during the ERS 1 interval is sensed.
  • the operation performed during the ERS 5 interval differs from that performed during the ERS 4 interval in that setting of the latch node NLAT is not performed. Remaining operations performed during the ERS 5 interval are closely similar to those performed during the ERS 4 interval, and accordingly, a detailed description thereof is omitted here to avoid redundancy.
  • the ERS 6 interval is executed next in which a determination is made as to whether the erase operation for the memory cells MC has been correctly performed using the data sensed during the ERS 4 and ERS 5 intervals.
  • latch node NLAT is logic “H” during the ERS 6 interval, data of a logic “L” state is output to the global output line GDOUT, so that a pass signal is generated. In contrast, if the latch node NLAT is logic “L”, data of a logic “H” state is output to the global output line GDOUT, so that a fail signal is generated.
  • the latch node NLAT maintains a logic “H” state when the memory cell is sensed as an ON cell with respect to both the ERS 4 and ERS 5 intervals. If the even bit line BLe 0 is connected to an OFF cell (non-erased), the latch node NLAT is discharged to the ground voltage VSS during the ERS 4 interval. Therefore, even if a memory cell MC connected to the odd bit line BLo 0 is detected as an ON cell during the ERS 5 interval, data on the latch node NLAT is logic “L”.
  • the pass signal is generated only when both the even bit line BLe 0 and the odd bit line BLo 0 are sensed as being connected to an ON cells.

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US8493785B2 (en) 2013-07-23

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