US7288786B2 - Integrated circuit configuration with analysis protection and method for producing the configuration - Google Patents

Integrated circuit configuration with analysis protection and method for producing the configuration Download PDF

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Publication number
US7288786B2
US7288786B2 US10/444,552 US44455203A US7288786B2 US 7288786 B2 US7288786 B2 US 7288786B2 US 44455203 A US44455203 A US 44455203A US 7288786 B2 US7288786 B2 US 7288786B2
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Prior art keywords
interconnects
integrated circuit
wiring
wiring plane
circuit configuration
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US10/444,552
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US20030205816A1 (en
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Marcus Janke
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention lies in the integrated technology field. More specifically, the present invention relates to an integrated circuit configuration with a substrate, which has circuit elements, and a wiring plane with interconnects, and also to a method for producing an integrated circuit configuration.
  • the object has been to prevent or at least render more difficult the analysis and manipulation of the integrated circuits; on the one hand.
  • An attempt to achieve that object has involved concealed structuring of the critical lines in the wiring plan.
  • that object has been tackled by application of a dedicated, covering protective plane above the relevant wiring planes.
  • these protective planes called “shields”, meander-shaped or lattice-shaped lines are typically realized e.g. in pairs in the protective plane, in the event of whose interruption or short circuit for the case where different voltages are present the detecting sensor initiates an erasure of the memory, a reset or the non-functionality of other circuit sections.
  • These lines, referred to as “passive” can likewise be embodied as unconnected, voltageless lines. In this case, they serve merely for increasing the complexity during the attack or for the purpose of confusion.
  • the security of the modules can be additionally increased by the passive lines described being replaced by so-called active lines in the design of the wiring plan.
  • the active lines signals are applied to the lines of the shield by drive circuits, which signals are analyzed by evaluation circuits and compared e.g. with reference signals owing to the possible variation of the signals, in this case the shield can only be circumvented by the very complicated laying of a bypass line by means of the FIB method.
  • an integrated circuit configuration comprising:
  • a driving an evaluation circuit connected to the second interconnects, for detecting one of an interruption of the second interconnects, a short circuit of one of the second interconnects with a further interconnect, or a bypass of the second interconnects.
  • the at least one wiring plane is one of a plurality of wiring planes, and at least one of the second interconnects extends over at least two of the wiring planes.
  • one of the second interconnects runs directly below or above one of the first interconnects.
  • the second interconnects are assigned to active lines.
  • a method of producing an integrated circuit configuration as outlined above i.e., a circuit with a substrate, circuit elements, and at least one wiring plane with first interconnects.
  • the novel method comprises generating a wiring plan for the integrated circuit, and thereby leaving regions of the wiring plane free of first interconnects and filling the regions with second interconnects for protection of the integrated circuit in the wiring plan.
  • the present invention proposes an integrated circuit configuration in which a maximum occupancy of interconnects is made possible for each plane by filling the regions which are left free of the interconnects that support the intended function of the integrated circuit with the interconnects that serve for protection of the integrated circuit.
  • this increases the number of interconnects to be examined per wiring plane; on the other hand, the potential attacker cannot ascertain from the outset which interconnects in the wiring plane serve for the actual integrated circuit and which serve only for the protection of this circuit.
  • the advantage thus arises that the filling and the joint positioning of the two assignments of interconnects in a wiring plane leads to a considerably higher complexity in the case of reverse engineering.
  • the integrated circuit configuration according to the invention may comprise substrates with active circuit elements and those integrated circuit configurations without active circuit elements that are used e.g. as so-called flip-chips, the latter usually being turned and bonded by the patterned side again onto the structure side of a substrate comprising active circuit elements. These together again produce precisely a circuit configuration according to the invention.
  • circuit elements also encompasses interconnects.
  • the integrated circuit configuration according to the invention can also be employed in the above-mentioned flip-chips, e.g. merely comprising interconnects, which can accordingly serve as extended protection for a chip comprising active circuit elements.
  • the method for producing the configuration according to the present invention proves to be particularly advantageous for integrated circuits created using synthesis methods.
  • Critical interconnects that are possibly not covered by interconnects in upper wiring planes in the synthesis method and are thus uncovered and at a deeper level can be covered, according to the present invention, by filling the left-free regions that lie precisely above the interconnect concerned with the interconnects serving for protection of the integrated circuit, after the end of the synthesis method.
  • the configurations and the method according to the present invention are preferably realized by means of a filling program which ideally follows the synthesis method.
  • a further aspect is constituted by the possible multilayer nature of regions with interconnects for protection of the integrated circuit.
  • different protective mechanisms such as, for instance, capacitive censor lines in a first plane and signal and sensor lines provided with comparators in a second plane, by which the successive removal of planes and examination of interconnects is advantageously made considerably more difficult.
  • FIG. 1A is a cross section taken through an exemplary circuit configuration, created in a synthesis method, with transistors and interconnects in four metal planes in accordance with the prior art;
  • FIG. 1B is a cross section taken through an exemplary circuit device according to the invention, after filling, i.e., after application of the method according to the invention for producing the circuit configuration.
  • FIG. 1A there is shown a wiring plan—created by a synthesis method—of a prior art integrated circuit configuration.
  • three transistors T 1 , T 2 and T 3 are illustrated on a substrate 9 .
  • the transistors T 1 and T 2 constitute a CMOS inverter.
  • the corresponding gate electrodes G 1 -G 3 and also metal contacts to the source regions S 1 -S 3 and drain regions D 1 -D 3 of the three transistors are situated in an insulating layer 91 lying on the substrate. Situated on this layer is the first metal plane 10 with an insulation layer thereon, with the interconnects 20 serving for the wiring of the components.
  • crossovers of the interconnects 20 the latter also have to switch to higher metal planes 11 , 12 and 13 that are mutually isolated by insulation layers. It is generally the case that, in particular, supply lines are laid in the topmost metal layers.
  • the VHDL program code reflecting the relationships and modes of operation of the respective components is translated by a compilation program to produce an optimized wiring plan specifying e.g. the shortest possible wiring routes.
  • the bottommost metal layer 10 is occupied to the greatest extent with interconnects, while this occupancy decreases to a greater extent towards upper metal layers.
  • regions, 1 , 1 ′ which are left free of interconnects and which widen towards high metal layers are produced in the wiring plan, but the left-free regions 1 ′ which are not utilized further by the compilation program can also be produced, which are surrounded and enclosed by interconnects.
  • a potential hacker for the purpose of attack after removal of the insulation layers between the metal layers 10 - 13 , could use e.g. needles to get at the safety-relevant interconnects 21 of the transistor T 3 , which are located in the first metal layer 10 , or the interconnects 22 of the transistors T 2 , T 3 , which are additionally located in the second metal layer 11 , in order to carry out probing or forcing here.
  • the regions 1 which are left free of interconnects e.g. in the synthesis method are filled (i.e., populated) with further interconnects 30 serving for protection of the integrated circuit.
  • This can be done manually but should ideally be realized by a computational filling program which detects the left-free regions and fills them with interconnects while complying with protective functions that are to be prescribed.
  • regions that are possibly still free on the substrate can be utilized for the components of the sensor lines, such as the transistor T 4 shown in FIG. 1B .
  • the interconnects 30 serving as sensor lines fill the left-free regions 1 as densely as possible in order just by virtue of their position to impede access through needles from a point measurement location or through the FIB method to the critical interconnects 21 , 22 .
  • the evaluation and/or drive devices which comprise e.g. transistors T 4 , it is possible to check the intactness of the interconnects 30 with respect to short circuit or bypassing by means of a comparison with a reference signal. If the signals are unequal, the evaluation device initiates, say, a reset or erasure of the memory of the integrated circuit.
  • the potential attack is made particularly more difficult by virtue of a lattice-shaped or meander-shaped shaping of the interconnects 31 , 32 . If the orientation of the interconnects 31 in the metal plane 13 is thereby chosen to be perpendicular to the interconnects 32 positioned in the underlying metal plane 12 , then it becomes particularly difficult for the potential attacker to get to the underlying lines, since in this case, by cutting out the hole through which the needle or the FIB is intended to reach the interconnect 22 , it is necessary to interrupt very many overlying interconnects 31 of the metal plane 13 and interconnects 32 of the metal plane 12 , which the potential attacker then has to individually examine or bypass in each case.
  • a further advantage is afforded by the checking of interconnects of the integrated circuit which lie in upper metal layers by means of underlying interconnects serving for protection purposes.
  • this is illustrated by the interconnect 23 of the metal plane 12 , below which the interconnect 33 runs parallel over the greatest possible length.
  • detection of the interruption of the interconnect 33 makes it possible to immediately infer the concurrent interruption of the interconnect 23 or an attack on the latter. It is safe to infer, then, that a hacking event has occurred and a change in the operating mode of the integrated circuit can be initiated by way of the evaluation logic unit.
  • connectionless interconnects 34 that serve only for the purpose of confusion. Furthermore, the generally implemented step of inserting a metal area for the stabilization of layer surfaces becomes superfluous as a result of filling with interconnects. Consequently, the security of the module is advantageously increased in conjunction with no or only little additional outlay.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US10/444,552 2000-11-23 2003-05-23 Integrated circuit configuration with analysis protection and method for producing the configuration Expired - Lifetime US7288786B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10058078.5 2000-11-23
DE10058078A DE10058078C1 (de) 2000-11-23 2000-11-23 Integrierte Schaltungsanordnung mit Analysierschutz und Verfahren zur Herstellung der Anordnung
PCT/DE2001/004198 WO2002043147A1 (fr) 2000-11-23 2001-11-08 Systeme de circuit integre protege de l'analyse, et procede de realisation du systeme

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/004198 Continuation WO2002043147A1 (fr) 2000-11-23 2001-11-08 Systeme de circuit integre protege de l'analyse, et procede de realisation du systeme

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Publication Number Publication Date
US20030205816A1 US20030205816A1 (en) 2003-11-06
US7288786B2 true US7288786B2 (en) 2007-10-30

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US (1) US7288786B2 (fr)
EP (1) EP1336201B1 (fr)
JP (1) JP2004514299A (fr)
KR (1) KR100515555B1 (fr)
CN (1) CN100359684C (fr)
BR (1) BR0115535A (fr)
DE (1) DE10058078C1 (fr)
MX (1) MXPA03004572A (fr)
RU (1) RU2263372C2 (fr)
UA (1) UA75379C2 (fr)
WO (1) WO2002043147A1 (fr)

Cited By (7)

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US20100001757A1 (en) * 2008-07-02 2010-01-07 Infineon Technologies Ag Integrated circuit and method of protecting a circuit part to be protected of an integrated circuit
EP2624296A1 (fr) 2012-02-06 2013-08-07 Altis Semiconductor Protection d'un circuit integre contre des attaques invasives
US20130285246A1 (en) * 2012-04-27 2013-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device With Self-Aligned Interconnects and Blocking Portions
US20130292836A1 (en) * 2012-05-01 2013-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Via-free interconnect structure with self-aligned metal line interconnections
US20150091185A1 (en) * 2013-09-30 2015-04-02 SK Hynix Inc. Semiconductor device and method for forming the same
US10181430B2 (en) 2013-07-02 2019-01-15 Qinetiq Limited Tamper resistant electronic hardware assembly with a non-functional die used as a protective layer
WO2022161590A1 (fr) 2021-01-26 2022-08-04 Tallinn University Of Technology Obscurcissement physique de matériel par couplage capacitif

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DE10218096A1 (de) * 2002-04-23 2003-11-13 Infineon Technologies Ag Integrierte Schaltung
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US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6924552B2 (en) * 2002-10-21 2005-08-02 Hrl Laboratories, Llc Multilayered integrated circuit with extraneous conductive traces
DE10337256A1 (de) * 2002-11-21 2004-06-09 Giesecke & Devrient Gmbh Integrierte Schaltkreisanordnung und Verfahren zur Herstellung derselben
AU2003293540A1 (en) * 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
JP2007528121A (ja) * 2003-07-11 2007-10-04 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 機密性を要する半導体製品、特にスマートカード・チップ
DE102004023462B4 (de) * 2004-05-12 2006-06-08 Infineon Technologies Ag Verfahren zur Ausbildung von Leiterbahnstrukturen auf Halbleiterbauelementen
WO2005117115A1 (fr) * 2004-05-28 2005-12-08 Koninklijke Philips Electronics N.V. Puces a lignes utiles et lignes fictives
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
JP2006228910A (ja) * 2005-02-16 2006-08-31 Matsushita Electric Ind Co Ltd 半導体装置
DE102005042790B4 (de) 2005-09-08 2010-11-18 Infineon Technologies Ag Integrierte Schaltungsanordnung und Verfahren zum Betrieb einer solchen
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
EP2115652B1 (fr) * 2007-02-20 2019-04-10 Nxp B.V. Dispositif semi-conducteur avec protection anti-sabotage en face arrière
CN102184270A (zh) * 2010-11-24 2011-09-14 天津蓝海微科技有限公司 安全芯片的版图保护电路自动生成方法
US9627310B2 (en) * 2012-04-11 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with self-aligned interconnects
US11211342B1 (en) * 2020-07-21 2021-12-28 Taiwan Semiconductor Manufacturing Company Ltd. Multiplexer cell and semiconductor device having camouflage design, and method for forming multiplexer cell

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WO2000067319A1 (fr) 1999-05-03 2000-11-09 Infineon Technologies Ag Procede et dispositif de securite d'une pile de puces montee en saillie et multidimensionnelle
US20030008432A1 (en) 1999-05-03 2003-01-09 Andreas Kux Method and device for securing a multi-dimensionally constructed chip stack and chip configuration
US6717267B1 (en) * 2000-01-13 2004-04-06 Renesas Technology Corp. Semiconductor device having multilayer interconnection structure
JP2001284357A (ja) 2000-03-30 2001-10-12 Sony Corp 半導体装置
US6486558B2 (en) * 2000-10-10 2002-11-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a dummy pattern

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* Cited by examiner, † Cited by third party
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US20100001757A1 (en) * 2008-07-02 2010-01-07 Infineon Technologies Ag Integrated circuit and method of protecting a circuit part to be protected of an integrated circuit
US8195995B2 (en) 2008-07-02 2012-06-05 Infineon Technologies Ag Integrated circuit and method of protecting a circuit part of an integrated circuit
EP2624296A1 (fr) 2012-02-06 2013-08-07 Altis Semiconductor Protection d'un circuit integre contre des attaques invasives
US20130285246A1 (en) * 2012-04-27 2013-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device With Self-Aligned Interconnects and Blocking Portions
US8907497B2 (en) * 2012-04-27 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with self-aligned interconnects and blocking portions
US20130292836A1 (en) * 2012-05-01 2013-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Via-free interconnect structure with self-aligned metal line interconnections
US8779592B2 (en) * 2012-05-01 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Via-free interconnect structure with self-aligned metal line interconnections
US9716032B2 (en) 2012-05-01 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Via-free interconnect structure with self-aligned metal line interconnections
US10181430B2 (en) 2013-07-02 2019-01-15 Qinetiq Limited Tamper resistant electronic hardware assembly with a non-functional die used as a protective layer
US20150091185A1 (en) * 2013-09-30 2015-04-02 SK Hynix Inc. Semiconductor device and method for forming the same
US9397039B2 (en) * 2013-09-30 2016-07-19 SK Hynix Inc. Semiconductor device and method for forming the same
WO2022161590A1 (fr) 2021-01-26 2022-08-04 Tallinn University Of Technology Obscurcissement physique de matériel par couplage capacitif

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UA75379C2 (en) 2006-04-17
DE10058078C1 (de) 2002-04-11
EP1336201B1 (fr) 2015-02-11
CN1476635A (zh) 2004-02-18
CN100359684C (zh) 2008-01-02
KR20040010564A (ko) 2004-01-31
JP2004514299A (ja) 2004-05-13
EP1336201A1 (fr) 2003-08-20
RU2263372C2 (ru) 2005-10-27
WO2002043147A1 (fr) 2002-05-30
MXPA03004572A (es) 2004-05-05
US20030205816A1 (en) 2003-11-06
BR0115535A (pt) 2004-02-03
KR100515555B1 (ko) 2005-09-16

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